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soc/intel/tigerlake: Move PMC PCI resources under PMC device

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Historically in coreboot, the PMC's fixed PCI resources were described
by the System Agent (the MMIO resource), and eSPI/LPC (the I/O
resource). This patch moves both of those to a new Intel SoC-specific
function, soc_pmc_read_resources(). On TGL, this new function takes care
of providing the MMIO and I/O resources for the PMC.

BUG=b:156388055
TEST=verified on volteer that the resource allocator is aware of and
does not touch these two resources:
("PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0
	flags f0000200 index 0
  PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff
	flags c0000100 index 1")

Also verify that the MEM resource is described in the coreboot table:
("BIOS-e820: [mem 0x00000000fe000000-0x00000000fe00ffff] reserved")

Verified the memory range is also untouchable from Linux:
("system 00:00: [mem 0xfe000000-0xffffffff] could not be reserved")

Change-Id: Ia7c6ae849aefaf549fb682416a87320907fb3fe3
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41385
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Wawrzynczak
2020-05-13 17:00:33 -06:00
committed by Patrick Georgi
parent dbcf7b1621
commit 6d20d0c140
9 changed files with 42 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
src/soc/intel/tigerlake/systemagent.c
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@@ -32,17 +32,6 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index)
{ EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
{ REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
/*
* PMC pci device gets hidden from PCI bus due to Silicon
* policy hence binding PMCBAR aka PWRMBASE (offset 0x10) with
* SA resources to ensure that PMCBAR falls under PCI reserved
* memory range.
*
* Note: Don't add any more resource with same offset 0x10
* under this device space.
*/
{ PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE,
"PMCBAR" },
};
sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,