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rockchip/rk3288: refactor pwm driver

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3288 and 3399 use the same pwm controller.

With this patch in place it is easy to add support for 3399.

BRANCH=none
BUG=none
TEST=booted veyron_jerry to kernel login prompt

Change-Id: If8f5697b4003d078b46de3fa3cebad6c8310a688
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: acf6132619167743c0c991b75f0f49c8d0e51ca7
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Change-Id: I79428f9ec71017ad8f3ad67dac1468178ccc3a1e
Original-Reviewed-on: https://chromium-review.googlesource.com/338019
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14336
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Lin Huang
2016-03-23 19:35:46 +08:00
committed by Patrick Georgi
parent d4c175b97b
commit 6d6b129ea4
4 changed files with 16 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
src/soc/rockchip/rk3288/pwm.c → src/soc/rockchip/common/pwm.c
View File

@@ -32,12 +32,12 @@ struct pwm_ctl {
u32 pwm_ctrl;
};
struct rk3288_pwm_regs {
struct rk_pwm_regs {
struct pwm_ctl pwm[4];
u32 intsts;
u32 int_en;
};
check_member(rk3288_pwm_regs, int_en, 0x44);
check_member(rk_pwm_regs, int_en, 0x44);
#define RK_PWM_DISABLE (0 << 0)
#define RK_PWM_ENABLE (1 << 0)
@@ -62,23 +62,25 @@ check_member(rk3288_pwm_regs, int_en, 0x44);
#define PWM_SEL_SCALE_CLK (1 << 9)
#define PWM_SEL_SRC_CLK (0 << 9)
struct rk3288_pwm_regs *rk3288_pwm = (void *)RK_PWM0123_BASE;
struct rk_pwm_regs *rk_pwm = (void *)RK_PWM_BASE;
void pwm_init(u32 id, u32 period_ns, u32 duty_ns)
{
unsigned long period, duty;
#if IS_ENABLED(CONFIG_SOC_ROCKCHIP_RK3288)
/*use rk pwm*/
write32(&rk3288_grf->soc_con2, RK_SETBITS(1 << 0));
#endif
write32(&rk3288_pwm->pwm[id].pwm_ctrl, PWM_SEL_SRC_CLK |
write32(&rk_pwm->pwm[id].pwm_ctrl, PWM_SEL_SRC_CLK |
PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_CONTINUOUS |
PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE | RK_PWM_DISABLE);
period = (PD_BUS_PCLK_HZ / 1000) * period_ns / USECS_PER_SEC;
duty = (PD_BUS_PCLK_HZ / 1000) * duty_ns / USECS_PER_SEC;
period = (PWM_CLOCK_HZ / 1000) * period_ns / USECS_PER_SEC;
duty = (PWM_CLOCK_HZ / 1000) * duty_ns / USECS_PER_SEC;
write32(&rk3288_pwm->pwm[id].pwm_period_hpr, period);
write32(&rk3288_pwm->pwm[id].pwm_duty_lpr, duty);
setbits_le32(&rk3288_pwm->pwm[id].pwm_ctrl, RK_PWM_ENABLE);
write32(&rk_pwm->pwm[id].pwm_period_hpr, period);
write32(&rk_pwm->pwm[id].pwm_duty_lpr, duty);
setbits_le32(&rk_pwm->pwm[id].pwm_ctrl, RK_PWM_ENABLE);
}

4
src/soc/rockchip/rk3288/Makefile.inc
View File

@@ -49,7 +49,7 @@ romstage-y += gpio.c
romstage-y += ../common/spi.c
romstage-y += sdram.c
romstage-y += ../common/rk808.c
romstage-y += pwm.c
romstage-y += ../common/pwm.c
romstage-y += tsadc.c
ramstage-y += soc.c
@@ -62,7 +62,7 @@ ramstage-y += ../common/spi.c
ramstage-y += sdram.c
ramstage-y += gpio.c
ramstage-y += ../common/rk808.c
ramstage-y += pwm.c
ramstage-y += ../common/pwm.c
ramstage-y += vop.c
ramstage-y += edp.c
ramstage-y += hdmi.c

2
src/soc/rockchip/rk3288/include/soc/addressmap.h
View File

@@ -52,7 +52,7 @@
#define I2C0_BASE 0xFF650000
#define I2C2_BASE 0xFF660000
#define DW_PWM0123_BASE 0xFF670000
#define RK_PWM0123_BASE 0xFF680000
#define RK_PWM_BASE 0xFF680000
#define UART2_BASE 0xFF690000
#define TIMER0_BASE 0xFF6B0000

2
src/soc/rockchip/rk3288/include/soc/clock.h
View File

@@ -39,6 +39,8 @@ enum apll_frequencies {
#define PERI_HCLK_HZ (148500*KHz)
#define PERI_PCLK_HZ (74250*KHz)
#define PWM_CLOCK_HZ PD_BUS_PCLK_HZ
void rkclk_init(void);
void rkclk_configure_spi(unsigned int bus, unsigned int hz);
void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy);