diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c
index 32ada9f4cb..e909b87ca8 100644
--- a/src/soc/intel/xeon_sp/cpx/romstage.c
+++ b/src/soc/intel/xeon_sp/cpx/romstage.c
@@ -3,6 +3,7 @@
 
 #include <arch/romstage.h>
 #include <fsp/api.h>
+#include <soc/romstage.h>
 #include "chip.h"
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
@@ -10,4 +11,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
 
 	(void)m_cfg;
+
+	mainboard_memory_init_params(mupd);
 }
diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c
index 9d3665c9fe..7881b0adb9 100644
--- a/src/soc/intel/xeon_sp/romstage.c
+++ b/src/soc/intel/xeon_sp/romstage.c
@@ -55,3 +55,8 @@ asmlinkage void car_stage_entry(void)
 
 	run_postcar_phase(&pcf);
 }
+
+__weak void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	printk(BIOS_SPEW, "WARNING: using default FSP-M parameters!\n");
+}