sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/ocp/deltalake: Configure FSP DCI via VPD

Browse Source 
Tested on OCP Delta Lake, with FSP WW34 DCI can be connected if enabled.

Change-Id: I8e0dff921cef02dfc66467a2b8fa3e196fb36ac2
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Johnny Lin
2020-08-11 10:35:39 +08:00
committed by Angel Pons
parent d5f24dd99b
commit 6da1710fbc
2 changed files with 14 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/mainboard/ocp/deltalake/romstage.c
View File

@@ -49,6 +49,16 @@ static void mainboard_config_upd(FSPM_UPD *mupd)
mupd->FspmConfig.DebugPrintLevel = FSP_LOG_LEVEL_DEFAULT; mupd->FspmConfig.DebugPrintLevel = FSP_LOG_LEVEL_DEFAULT;
} }
} }
/* Enable DCI */
if (vpd_get_bool(FSP_DCI, VPD_RW_THEN_RO, &val)) {
printk(BIOS_DEBUG, "Setting DciEn %d from VPD\n", val);
mupd->FspmConfig.PchDciEn = val;
} else {
printk(BIOS_INFO, "Not able to get VPD %s, default set "
"DciEn to %d\n", FSP_DCI, FSP_DCI_DEFAULT);
mupd->FspmConfig.PchDciEn = FSP_DCI_DEFAULT;
}
} }
/* Update bifurcation settings according to different Configs */ /* Update bifurcation settings according to different Configs */

4
src/mainboard/ocp/deltalake/vpd.h
View File

@@ -28,4 +28,8 @@
#define FSP_LOG_LEVEL "fsp_log_level" #define FSP_LOG_LEVEL "fsp_log_level"
#define FSP_LOG_LEVEL_DEFAULT 8 /* Default value when the VPD variable is not found */ #define FSP_LOG_LEVEL_DEFAULT 8 /* Default value when the VPD variable is not found */
/* DCI enable */
#define FSP_DCI "fsp_dci_enable" /* 1 or 0: enable or disable DCI */
#define FSP_DCI_DEFAULT 0 /* Default value when the VPD variable is not found */
#endif #endif