mb/google/kahlee/*/devicetree: disable unused PCIe root ports

Disable the unused PCIe root ports that are disabled in the PCIe port
corresponding descriptor list passed to AGESA/binaryPI. This descriptor
list is in src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
and it only has B0D2F2 (gpp_bridge_1) and B0D2F4 (gpp_bridge_3) enabled.
Since the PCIe engines marked as unused in the port descriptor list
won't show up as PCI devices, don't enable those PCI devices in the
devicetree so that coreboot won't complain about static PCI devices not
being found on the PCI bus.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If8378e343a2eb13de66171cf4f38d77ae3401016
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68382
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
This commit is contained in:
Felix Held
2022-10-12 23:28:19 +02:00
parent 2c341c1fea
commit 6dbded495e
6 changed files with 6 additions and 24 deletions

View File

@ -48,16 +48,13 @@ chip soc/amd/stoneyridge
device ref iommu off end # IOMMU (Disabled for performance and battery)
device ref gfx on end
device ref gfx_hda on end
device ref gpp_bridge_0 on end
device ref gpp_bridge_1 on end
device ref gpp_bridge_2 on end
device ref gpp_bridge_1 on end # WLAN
device ref gpp_bridge_3 on
chip drivers/generic/bayhub
register "power_saving" = "1"
device pci 00.0 on end
end
end
device ref gpp_bridge_4 on end
device ref hda_bridge on end
device ref hda on end
device ref xhci on end

View File

@ -48,16 +48,13 @@ chip soc/amd/stoneyridge
device ref iommu off end # IOMMU (Disabled for performance and battery)
device ref gfx on end
device ref gfx_hda on end
device ref gpp_bridge_0 on end
device ref gpp_bridge_1 on end
device ref gpp_bridge_2 on end
device ref gpp_bridge_1 on end # WLAN
device ref gpp_bridge_3 on
chip drivers/generic/bayhub
register "power_saving" = "1"
device pci 00.0 on end
end
end
device ref gpp_bridge_4 on end
device ref hda_bridge on end
device ref hda on end
device ref xhci on end

View File

@ -48,16 +48,13 @@ chip soc/amd/stoneyridge
device ref iommu off end # IOMMU (Disabled for performance and battery)
device ref gfx on end
device ref gfx_hda on end
device ref gpp_bridge_0 on end
device ref gpp_bridge_1 on end
device ref gpp_bridge_2 on end
device ref gpp_bridge_1 on end # WLAN
device ref gpp_bridge_3 on
chip drivers/generic/bayhub
register "power_saving" = "1"
device pci 00.0 on end
end
end
device ref gpp_bridge_4 on end
device ref hda_bridge on end
device ref hda on end
device ref xhci on end

View File

@ -47,16 +47,13 @@ chip soc/amd/stoneyridge
device ref iommu off end # IOMMU (Disabled for performance and battery)
device ref gfx on end
device ref gfx_hda on end
device ref gpp_bridge_0 on end
device ref gpp_bridge_1 on end
device ref gpp_bridge_2 on end
device ref gpp_bridge_1 on end # WLAN
device ref gpp_bridge_3 on
chip drivers/generic/bayhub
register "power_saving" = "1"
device pci 00.0 on end
end
end
device ref gpp_bridge_4 on end
device ref hda_bridge on end
device ref hda on end
device ref xhci on end

View File

@ -51,9 +51,7 @@ chip soc/amd/stoneyridge
device ref iommu off end # IOMMU (Disabled for performance and battery)
device ref gfx on end
device ref gfx_hda on end
device ref gpp_bridge_0 on end
device ref gpp_bridge_1 on end
device ref gpp_bridge_2 on end
device ref gpp_bridge_1 on end # WLAN
device ref gpp_bridge_3 on
chip drivers/generic/bayhub
register "power_saving" = "1"
@ -61,7 +59,6 @@ chip soc/amd/stoneyridge
device pci 00.0 on end
end
end
device ref gpp_bridge_4 on end
device ref hda_bridge on end
device ref hda on end
device ref xhci on end

View File

@ -51,9 +51,7 @@ chip soc/amd/stoneyridge
device ref iommu off end # IOMMU (Disabled for performance and battery)
device ref gfx on end
device ref gfx_hda on end
device ref gpp_bridge_0 on end
device ref gpp_bridge_1 on end
device ref gpp_bridge_2 on end
device ref gpp_bridge_1 on end # WLAN
device ref gpp_bridge_3 on
chip drivers/generic/bayhub
register "power_saving" = "1"
@ -61,7 +59,6 @@ chip soc/amd/stoneyridge
device pci 00.0 on end
end
end
device ref gpp_bridge_4 on end
device ref hda_bridge on end
device ref hda on end
device ref xhci on end