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soc/intel/apollolake: Add PM methods to power gate SD card

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This implements dynamic generation of sdcard GpioInt in SSDT.
GpioInt in SSDT generation is based on the card detect GPIO if
it is provided by the mainboard in devicetree.

This implements GNVS variable to store the address of sdcard cd pin.
GNVS used to store rxstate of the sdcard cd pin to get card presence.

Add _PS0/_PS3 methods to power gate the sd card controller in
S0ix and runtime PM.

CQ-DEPEND=448173
BUG=chrome-os-partner:63070
TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
System should enter S0ix and resume with no issue.

Change-Id: Id2c42fc66062f0431385607cff1a83563eaeef87
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/18496
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
This commit is contained in:
Venkateswarlu Vinjamuri
2017-02-24 15:37:30 -08:00
committed by Martin Roth
parent d4f92fa603
commit 6dd7b402d5
8 changed files with 147 additions and 1 deletions
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14
src/soc/intel/apollolake/chip.c
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@ -113,6 +113,20 @@ static const char *soc_acpi_name(struct device *dev)
return NULL;
}
static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
if (!vendor || !device)
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
else
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
(device << 16) | vendor);
}
struct pci_operations soc_pci_ops = {
.set_subsystem = &pci_set_subsystem
};
static void pci_domain_set_resources(device_t dev)
{
assign_resources(dev->link_list);