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arch/x86: Refactor the SMBIOS type 17 write function

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List of changes:
1. Create Module Type macros as per Memory Type
(i.e. DDR2/DDR3/DDR4/DDR5/LPDDR4/LPDDR5) and fix compilation
issue due to renaming of existing macros due to scoping the Memory
Type.
2. Use dedicated Memory Type and Module type for `Form Factor`
and `TypeDetail` conversion using `get_spd_info()` function.
3. Create a new API (convert_form_factor_to_module_type()) for
`Form Factor` to 'Module type' conversion as per `Memory Type`.
4. Add new argument as `Memory Type` to
smbios_form_factor_to_spd_mod_type() so that it can internally
call convert_form_factor_to_module_type() for `Module Type`
conversion.
5. Update `test_smbios_form_factor_to_spd_mod_type()` to
accommodate different memory types.
6. Skip fixed module type to form factor conversion using DDR2 SPD4
specification (inside dimm_info_fill()).

Refer to datasheet SPD4.1.2.M-1 for LPDDRx and SPD4.1.2.L-3 for DDRx.

BUG=b:194659789
TEST=Refer to dmidecode -t 17 output as below:
Without this code change:

Handle 0x0012, DMI type 17, 40 bytes
Memory Device
        Array Handle: 0x000A
        Error Information Handle: Not Provided
        Total Width: 16 bits
        Data Width: 16 bits
        Size: 2048 MB
        Form Factor: Unknown
        ....

With this code change:

Handle 0x0012, DMI type 17, 40 bytes
Memory Device
        Array Handle: 0x000A
        Error Information Handle: Not Provided
        Total Width: 16 bits
        Data Width: 16 bits
        Size: 2048 MB
        Form Factor: Row Of Chips
        ....

Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Subrata Banik
2021-10-26 20:46:21 +05:30
parent 9a3bde0581
commit 6de8b42482
15 changed files with 404 additions and 107 deletions
Download Patch File Download Diff File Expand all files Collapse all files

72
src/include/spd.h
View File

@ -197,18 +197,70 @@ enum spd_memory_type {
#define MODULE_BUFFERED 1
#define MODULE_REGISTERED 2
/* Byte 3: Module type information */
#define SPD_UNDEFINED 0x00
#define SPD_RDIMM 0x01
#define SPD_UDIMM 0x02
#define SPD_SODIMM 0x04
#define SPD_72B_SO_CDIMM 0x06
#define SPD_72B_SO_RDIMM 0x07
#define SPD_MICRO_DIMM 0x08
#define SPD_MINI_RDIMM 0x10
#define SPD_MINI_UDIMM 0x20
#define SPD_ECC_8BIT (1<<3)
#define SPD_ECC_8BIT_LP5_DDR5 (1<<4)
/* Byte 3: Module type information */
enum ddr2_module_type {
DDR2_SPD_RDIMM = 0x01,
DDR2_SPD_UDIMM = 0x02,
DDR2_SPD_SODIMM = 0x04,
DDR2_SPD_72B_SO_CDIMM = 0x06,
DDR2_SPD_72B_SO_RDIMM = 0x07,
DDR2_SPD_MICRO_DIMM = 0x08,
DDR2_SPD_MINI_RDIMM = 0x10,
DDR2_SPD_MINI_UDIMM = 0x20,
};
enum ddr3_module_type {
DDR3_SPD_RDIMM = 0x01,
DDR3_SPD_UDIMM = 0x02,
DDR3_SPD_SODIMM = 0x03,
DDR3_SPD_MICRO_DIMM = 0x04,
DDR3_SPD_MINI_RDIMM = 0x05,
DDR3_SPD_MINI_UDIMM = 0x06,
DDR3_SPD_MINI_CDIMM = 0x07,
DDR3_SPD_72B_SO_UDIMM = 0x08,
DDR3_SPD_72B_SO_RDIMM = 0x09,
DDR3_SPD_72B_SO_CDIMM = 0x0a,
DDR3_SPD_LRDIMM = 0x0b,
DDR3_SPD_16B_SO_DIMM = 0x0c,
DDR3_SPD_32B_SO_RDIMM = 0x0d,
};
enum ddr4_module_type {
DDR4_SPD_RDIMM = 0x01,
DDR4_SPD_UDIMM = 0x02,
DDR4_SPD_SODIMM = 0x03,
DDR4_SPD_LRDIMM = 0x04,
DDR4_SPD_MINI_RDIMM = 0x05,
DDR4_SPD_MINI_UDIMM = 0x06,
DDR4_SPD_72B_SO_UDIMM = 0x08,
DDR4_SPD_72B_SO_RDIMM = 0x09,
DDR4_SPD_16B_SO_DIMM = 0x0c,
DDR4_SPD_32B_SO_RDIMM = 0x0d,
};
enum ddr5_module_type {
DDR5_SPD_RDIMM = 0x01,
DDR5_SPD_UDIMM = 0x02,
DDR5_SPD_SODIMM = 0x03,
DDR5_SPD_LRDIMM = 0x04,
DDR5_SPD_MINI_RDIMM = 0x05,
DDR5_SPD_MINI_UDIMM = 0x06,
DDR5_SPD_72B_SO_UDIMM = 0x08,
DDR5_SPD_72B_SO_RDIMM = 0x09,
DDR5_SPD_SOLDERED_DOWN = 0x0b,
DDR5_SPD_16B_SO_DIMM = 0x0c,
DDR5_SPD_32B_SO_RDIMM = 0x0d,
DDR5_SPD_1DPC = 0x0e,
DDR5_SPD_2DPC = 0x0f,
};
enum lpx_module_type {
LPX_SPD_LPDIMM = 0x07,
LPX_SPD_NONDIMM = 0x0e,
};
#endif