From 6e1a07ca56bf6cfb3b0969971a886a59bb18a3e2 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Thu, 22 Jun 2023 09:28:18 -0600 Subject: [PATCH] bonw15: Fix SSD2 and DGPU PCIe definitions Change-Id: I717a0b87927e3084e56651f9241ee8ae086caf80 --- .../system76/rpl/variants/bonw15/overridetree.cb | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/system76/rpl/variants/bonw15/overridetree.cb b/src/mainboard/system76/rpl/variants/bonw15/overridetree.cb index cb6193470b..7e632c5458 100644 --- a/src/mainboard/system76/rpl/variants/bonw15/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/bonw15/overridetree.cb @@ -42,19 +42,19 @@ chip soc/intel/alderlake end device ref pcie5_0 on - # CPU PCIe RP#2 x8, Clock 14 (DGPU) + # CPU PCIe RP#3 x4, CLKOUT 2, CLKREQ 11 (SSD2) register "cpu_pcie_rp[CPU_RP(2)]" = "{ - .clk_src = 14, - .clk_req = 14, + .clk_src = 2, + .clk_req = 11, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end device ref pcie5_1 on - # CPU PCIe RP#3 x4, Clock 2 (SSD2) + # CPU PCIe RP#2 x8, Clock 14 (DGPU) register "cpu_pcie_rp[CPU_RP(3)]" = "{ - .clk_src = 2, - .clk_req = 2, + .clk_src = 14, + .clk_req = 14, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end