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arm64: save and restore cntfrq for secondary cpus

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CNTFRQ_EL0 can only be set in highest implemented exception level.
Save and restore CNTFRQ_EL0 for secondary cpus in coreboot.

This patch fix the error below:

SANITY CHECK: Unexpected variation in cntfrq. Boot CPU:
0x00000000c65d40, CPU1: 0x00000000000000

BRANCH=none
BUG=none
TEST=boot to kernel on oak board and check secondary cpu's cntfrq.
     confirmed cpu1's cntfrq is same as boot cpu's.

Change-Id: I9fbc3c82c2544f0b59ec34b1d631dadf4b9d40eb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b47e4e649efc7f79f016522c7d8a240f98225598
Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Original-Change-Id: I2d71b0ccfe42e8a30cd1367d10b0f8993431ef8c
Original-Reviewed-on: https://chromium-review.googlesource.com/264914
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9921
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Jimmy Huang
2015-04-01 18:27:12 +08:00
committed by Patrick Georgi
parent 5d302c75d8
commit 6e41523e70
5 changed files with 33 additions and 1 deletions
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15
src/arch/arm64/armv8/lib/sysctrl.c
View File

@@ -1051,3 +1051,18 @@ void raw_write_vbar(uint64_t vbar, uint32_t el)
{
SWITCH_CASE_WRITE(raw_write_vbar, vbar, el);
}
uint32_t raw_read_cntfrq_el0(void)
{
uint32_t cntfrq_el0;
__asm__ __volatile__("mrs %0, CNTFRQ_EL0\n\t" : "=r" (cntfrq_el0) : :
"memory");
return cntfrq_el0;
}
void raw_write_cntfrq_el0(uint32_t cntfrq_el0)
{
__asm__ __volatile__("msr CNTFRQ_EL0, %0\n\t" : : "r" (cntfrq_el0) :
"memory");
}