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- Merge from linuxbios-lnxi (Linux Networx repository) up to public tree.

Browse Source 
- Special version for HDAMA rev G with 33Mhz test and reboot out.
        - Support for CPU rev E, dual core, memory hoisting,
        - corrected an SST flashing problem. Kernel bug work around (NUMA)
        - added a Kernel bug work around for assigning CPU's to memory.

 r2@gog:  svnadmin | 2005-08-03 08:47:54 -0600
 Create local LNXI branch
 r1110@gog:  jschildt | 2005-08-09 10:35:51 -0600
 - Merge from Tom Zimmerman's additions to the hdama code for dual core
   and 33Mhz fix.
 
 
 r1111@gog:  jschildt | 2005-08-09 11:07:11 -0600
 Stable Release tag for HDAMA-1.1.8.10 and HDAMA-1.1.8.10LANL
 r1112@gog:  jschildt | 2005-08-09 15:09:32 -0600
 - temporarily removing hdama tag to update to public repository.  Will
   reset tag after update.
 
 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Jason Schildt
2005-08-09 21:53:07 +00:00
parent dc2454eb94
commit 6e44b422b3
31 changed files with 903 additions and 1263 deletions
Download Patch File Download Diff File Expand all files Collapse all files

184
src/cpu/amd/dualcore/amd_sibling.c
View File

@ -1,4 +1,5 @@
/* 2004.12 yhlu add dual core support */
/* 24 June 2005 Cleaned up dual core support Eric Biederman */
#include <console/console.h>
#include <cpu/cpu.h>
@ -14,59 +15,87 @@
static int first_time = 1;
static int disable_siblings = !CONFIG_LOGICAL_CPUS;
int is_e0_later_in_bsp(int nodeid)
void amd_sibling_init(device_t cpu, struct node_core_id id)
{
uint32_t val;
uint32_t val_old;
int e0_later;
if(nodeid==0) { // we don't need to do that for node 0 in core0/node0
return !is_cpu_pre_e0();
unsigned long i;
unsigned siblings, max_siblings;
/* On the bootstrap processor see if I want sibling cpus enabled */
if (first_time) {
first_time = 0;
get_option(&disable_siblings, "dual_core");
}
// d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0
device_t dev;
dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid,2));
if(!dev) return 0;
val_old = pci_read_config32(dev, 0x80);
val = val_old;
val |= (1<<3);
pci_write_config32(dev, 0x80, val);
val = pci_read_config32(dev, 0x80);
e0_later = !!(val & (1<<3));
if(e0_later) { // pre_e0 bit 3 always be 0 and can not be changed
pci_write_config32(dev, 0x80, val_old); // restore it
siblings = cpuid_ecx(0x80000008) & 0xff;
printk_debug("%d Sibling Cores found\n", siblings);
/* For now assume all cpus have the same number of siblings */
max_siblings = siblings + 1;
/* Wishlist? make dual cores look like hyperthreading */
/* See if I am a sibling cpu */
if (disable_siblings && (id.coreid != 0)) {
cpu->enabled = 0;
}
if (id.coreid == 0) {
/* On the primary cpu find the siblings */
for (i = 1; i <= siblings; i++) {
struct device_path cpu_path;
device_t new;
/* Build the cpu device path */
cpu_path.type = DEVICE_PATH_APIC;
cpu_path.u.apic.apic_id =
(id.nodeid*max_siblings) + i;
new = alloc_dev(cpu->bus, &cpu_path);
if (!new) {
continue;
}
/* Report what I have done */
printk_debug("CPU: %s %s\n",
dev_path(new), new->enabled?"enabled":"disabled");
}
}
return e0_later;
}
unsigned int read_nb_cfg_54(void)
struct node_core_id get_node_core_id(void)
{
msr_t msr;
msr = rdmsr(NB_CFG_MSR);
return ( ( msr.hi >> (54-32)) & 1);
}
struct node_core_id get_node_core_id(unsigned int nb_cfg_54) {
struct node_core_id id;
// get the apicid via cpuid(1) ebx[27:24]
if(nb_cfg_54) {
// when NB_CFG[54] is set, nodid = ebx[27:25], coreid = ebx[24]
id.coreid = (cpuid_ebx(1) >> 24) & 0xf;
id.nodeid = (id.coreid>>1);
id.coreid &= 1;
} else { // single core should be here too
unsigned siblings;
/* Get the apicid at reset */
id.nodeid = (cpuid_ebx(1) >> 24) & 0xff;
id.coreid = 0;
/* Find out how many siblings we have */
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings) {
unsigned bits;
msr_t msr;
bits = 0;
while ((1 << bits) <= siblings)
bits++;
msr = rdmsr(NB_CFG_MSR);
if ((msr.hi >> (54-32)) & 1) {
// when NB_CFG[54] is set, nodeid = ebx[27:25], coreid = ebx[24]
id.coreid = id.nodeid & ((1 << bits) - 1);
id.nodeid >>= bits;
} else {
// when NB_CFG[54] is clear, nodeid = ebx[26:24], coreid = ebx[27]
id.nodeid = (cpuid_ebx(1) >> 24) & 0xf;
id.coreid = (id.nodeid>>3);
id.nodeid &= 7;
id.coreid = id.nodeid >> 3;
id.nodeid &= 7;
}
} else {
if (!is_cpu_pre_e0()) {
id.nodeid >>= 1;
}
}
return id;
return id;
}
#if 0
static int get_max_siblings(int nodes)
{
device_t dev;
@ -169,76 +198,5 @@ unsigned get_apicid_base(unsigned ioapic_num)
return apicid_base;
}
#if 0
void amd_sibling_init(device_t cpu)
{
unsigned i, siblings;
struct cpuid_result result;
unsigned nb_cfg_54;
struct node_core_id id;
/* On the bootstrap processor see if I want sibling cpus enabled */
if (first_time) {
first_time = 0;
get_option(&disable_siblings, "dual_core");
}
result = cpuid(0x80000008);
/* See how many sibling cpus we have */
/* Is dualcore supported */
siblings = (result.ecx & 0xff);
if ( siblings < 1) {
return;
}
#if 1
printk_debug("CPU: %u %d siblings\n",
cpu->path.u.apic.apic_id,
siblings);
#endif
nb_cfg_54 = read_nb_cfg_54();
#if 1
id = get_node_core_id(nb_cfg_54); // pre e0 nb_cfg_54 can not be set
/* See if I am a sibling cpu */
//if ((cpu->path.u.apic.apic_id>>(nb_cfg_54?0:3)) & siblings ) { // siblings = 1, 3, 7, 15,....
//if ( ( (cpu->path.u.apic.apic_id>>(nb_cfg_54?0:3)) % (siblings+1) ) != 0 ) {
if(id.coreid != 0) {
if (disable_siblings) {
cpu->enabled = 0;
}
return;
}
#endif
/* I am the primary cpu start up my siblings */
for(i = 1; i <= siblings; i++) {
struct device_path cpu_path;
device_t new;
/* Build the cpu device path */
cpu_path.type = DEVICE_PATH_APIC;
cpu_path.u.apic.apic_id = cpu->path.u.apic.apic_id + i * (nb_cfg_54?1:8);
/* See if I can find the cpu */
new = find_dev_path(cpu->bus, &cpu_path);
/* Allocate the new cpu device structure */
if(!new) {
new = alloc_dev(cpu->bus, &cpu_path);
new->enabled = 1;
new->initialized = 0;
}
#if 1
printk_debug("CPU: %u has sibling %u\n",
cpu->path.u.apic.apic_id,
new->path.u.apic.apic_id);
#endif
/* Start the new cpu */
if(new->enabled && !new->initialized)
start_cpu(new);
}
}
#endif

56
src/cpu/amd/dualcore/dualcore.c
View File

@ -1,12 +1,15 @@
/* 2004.12 yhlu add dual core support */
#ifndef SET_NB_CFG_54
#define SET_NB_CFG_54 1
#endif
#include "cpu/amd/dualcore/dualcore_id.c"
#if 0
static inline unsigned get_core_num_in_bsp(unsigned nodeid)
{
return ((pci_read_config32(PCI_DEV(0, 0x18+nodeid, 3), 0xe8)>>12) & 3);
@ -97,3 +100,56 @@ static inline void start_other_cores(void) {
}
}
#endif
static void k8_init_and_stop_secondaries(void)
{
struct node_core_id id;
device_t dev;
unsigned apicid;
unsigned max_siblings;
int init_detected;
msr_t msr;
/* Skip this if there was a built in self test failure */
init_detected = early_mtrr_init_detected();
amd_early_mtrr_init();
enable_lapic();
init_timer();
if (init_detected) {
asm volatile ("jmp __cpu_reset");
}
if (is_cpu_pre_e0()) {
id.nodeid = lapicid() & 0x7;
id.coreid = 0;
} else {
/* Which cpu are we on? */
id = get_node_core_id_x();
/* Set NB_CFG_MSR
* Linux expect the core to be in the least signficant bits.
*/
msr = rdmsr(NB_CFG_MSR);
msr.hi |= (1<<(54-32)); // InitApicIdCpuIdLo
wrmsr(NB_CFG_MSR, msr);
}
/* For now assume all cpus have the same number of siblings */
max_siblings = (cpuid_ecx(0x80000008) & 0xff) + 1;
/* Set the lapicid */
lapic_write(LAPIC_ID,((id.nodeid*max_siblings) + id.coreid) << 24);
/* Remember the cpuid */
if (id.coreid == 0) {
dev = PCI_DEV(0, 0x18 + id.nodeid, 2);
pci_write_config32(dev, 0x9c, cpuid_eax(1));
}
/* Maybe call distinguish_cpu_resets only on the last core? */
distinguish_cpu_resets(id.nodeid);
if (!boot_cpu()) {
stop_this_cpu();
}
}

4
src/cpu/amd/dualcore/dualcore_id.c
View File

@ -11,8 +11,8 @@ static inline unsigned int read_nb_cfg_54(void)
}
struct node_core_id {
unsigned nodeid;
unsigned coreid;
unsigned nodeid:8;
unsigned coreid:8;
};
static inline struct node_core_id get_node_core_id(unsigned nb_cfg_54) {

98
src/cpu/amd/model_fxx/model_fxx_init.c
View File

@ -21,10 +21,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/mem.h>
#if CONFIG_LOGICAL_CPUS==1
#include <cpu/amd/dualcore.h>
#endif
#include "model_fxx_msr.h"
@ -152,9 +149,6 @@ static void set_init_ecc_mtrrs(void)
static void init_ecc_memory(unsigned node_id)
{
unsigned long startk, begink, endk;
#if K8_E0_MEM_HOLE_SIZEK != 0
unsigned long hole_startk = 0, hole_endk = 0;
#endif
unsigned long basek;
struct mtrr_state mtrr_state;
device_t f1_dev, f2_dev, f3_dev;
@ -199,25 +193,13 @@ static void init_ecc_memory(unsigned node_id)
startk = (pci_read_config32(f1_dev, 0x40 + (node_id*8)) & 0xffff0000) >> 2;
endk = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000;
#if K8_E0_MEM_HOLE_SIZEK != 0
if (!is_cpu_pre_e0()) {
uint32_t val;
val = pci_read_config32(f1_dev, 0xf0);
if((val & 1)==1) {
hole_startk = ((val & (0xff<<24)) >> 10);
hole_endk = ((val & (0xff<<8))<<(16-10)) - startk;
hole_endk += hole_startk;
}
}
#endif
/* Don't start too early */
begink = startk;
if (begink < CONFIG_LB_MEM_TOPK) {
begink = CONFIG_LB_MEM_TOPK;
}
printk_debug("Clearing memory %uK - %uK: ", startk, endk);
printk_debug("Clearing memory %uK - %uK: ", begink, endk);
/* Save the normal state */
save_mtrr_state(&mtrr_state);
@ -234,9 +216,6 @@ static void init_ecc_memory(unsigned node_id)
unsigned long size;
void *addr;
#if K8_E0_MEM_HOLE_SIZEK != 0
if ((basek >= hole_startk) && (basek < hole_endk)) continue;
#endif
/* Report every 64M */
if ((basek % (64*1024)) == 0) {
/* Restore the normal state */
@ -340,6 +319,7 @@ static inline void k8_errata(void)
/* Erratum 91 prefetch miss is handled in the kernel */
/* Erratum 106 ... */
msr = rdmsr_amd(LS_CFG_MSR);
msr.lo |= 1 << 25;
@ -350,7 +330,7 @@ static inline void k8_errata(void)
msr.hi |= 1 << (43 - 32);
wrmsr_amd(BU_CFG_MSR, msr);
if(is_cpu_d0()) {
if (is_cpu_pre_e0() && !is_cpu_pre_d0()) {
/* Erratum 110 ...*/
msr = rdmsr_amd(CPU_ID_HYPER_EXT_FEATURES);
msr.hi |=1;
@ -362,26 +342,34 @@ static inline void k8_errata(void)
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
msr.hi |=1;
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
/* Erratum 113 ... */
msr = rdmsr_amd(BU_CFG_MSR);
msr.hi |= (1 << 16);
wrmsr_amd(BU_CFG_MSR, msr);
}
/* Erratum 122 */
msr = rdmsr(HWCR_MSR);
msr.lo |= 1 << 6;
wrmsr(HWCR_MSR, msr);
if (!is_cpu_pre_c0()) {
msr = rdmsr(HWCR_MSR);
msr.lo |= 1 << 6;
wrmsr(HWCR_MSR, msr);
}
/* Erratum 123? dual core deadlock? */
/* Erratum 131 */
msr = rdmsr(NB_CFG_MSR);
msr.lo |= 1 << 20;
wrmsr(NB_CFG_MSR, msr);
}
void model_fxx_init(device_t dev)
void model_fxx_init(device_t cpu)
{
unsigned long i;
msr_t msr;
#if CONFIG_LOGICAL_CPUS
struct node_core_id id;
unsigned siblings;
id.coreid=0;
#else
unsigned nodeid;
#endif
/* Turn on caching if we haven't already */
x86_enable_cache();
@ -404,43 +392,18 @@ void model_fxx_init(device_t dev)
/* Enable the local cpu apics */
setup_lapic();
#if CONFIG_LOGICAL_CPUS == 1
siblings = cpuid_ecx(0x80000008) & 0xff;
/* Find our node and core */
id = get_node_core_id();
id = get_node_core_id(read_nb_cfg_54()); // pre e0 nb_cfg_54 can not be set
if(siblings>0) {
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
msr.lo |= 1 << 28;
wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
msr = rdmsr_amd(LOGICAL_CPUS_NUM_MSR);
msr.lo = (siblings+1)<<16;
wrmsr_amd(LOGICAL_CPUS_NUM_MSR, msr);
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
msr.hi |= 1<<(33-32);
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
/* Is this a bad location? In particular can another node prefecth
/* Is this a bad location? In particular can another node prefetch
* data from this node before we have initialized it?
*/
if (id.coreid == 0) init_ecc_memory(id.nodeid); // only do it for core 0
#else
/* Is this a bad location? In particular can another node prefecth
* data from this node before we have initialized it?
*/
nodeid = lapicid() & 0xf;
init_ecc_memory(nodeid);
#endif
#if CONFIG_LOGICAL_CPUS==1
/* Start up my cpu siblings */
// if(id.coreid==0) amd_sibling_init(dev); // Don't need core1 is already be put in the CPU BUS in bus_cpu_scan
#endif
if (id.coreid == 0) {
init_ecc_memory(id.nodeid); // only do it for core 0
}
/* Deal with sibling cpus */
amd_sibling_init(cpu, id);
}
static struct device_operations cpu_dev_ops = {
@ -451,7 +414,7 @@ static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0xf51 }, /* SH7-B3 */
{ X86_VENDOR_AMD, 0xf58 }, /* SH7-C0 */
{ X86_VENDOR_AMD, 0xf48 },
#if 1
{ X86_VENDOR_AMD, 0xf5A }, /* SH7-CG */
{ X86_VENDOR_AMD, 0xf4A },
{ X86_VENDOR_AMD, 0xf7A },
@ -483,7 +446,6 @@ static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0x20fc2 },
{ X86_VENDOR_AMD, 0x20f12 }, /* JH-E6 */
{ X86_VENDOR_AMD, 0x20f32 },
#endif
{ 0, 0 },
};

13
src/cpu/x86/mtrr/earlymtrr.c
View File

@ -117,4 +117,17 @@ static void early_mtrr_init(void)
enable_cache();
}
static int early_mtrr_init_detected(void)
{
msr_t msr;
/* See if MTRR's are enabled.
* a #RESET disables them while an #INIT
* preserves their state. This works
* on both Intel and AMD cpus, at least
* according to the documentation.
*/
msr = rdmsr(MTRRdefType_MSR);
return msr.lo & 0x00000800;
}
#endif /* EARLYMTRR_C */