device/dram/ddr2: Add common ddr2 spd decoder
Decode DDR2 SPD similar to DDR3 SPD decoder to ease readability, reduce code complexity and reduce size of maintainable code. Rename dimm_is_registered to spd_dimm_is_registered_ddr3 to avoid compilation errors. Change-Id: I741f0e61ab23e3999ae9e31f57228ba034c2509e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18273 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins)
This commit is contained in:
Patrick Rudolph
committed by
Martin Roth
Martin Roth
parent
7e4d12c5b1
commit
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218
src/include/device/dram/ddr2.h
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218
src/include/device/dram/ddr2.h
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* JEDEC Standard No. 21-C
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* Annex J: Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3)
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*/
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#ifndef DEVICE_DRAM_DDR2L_H
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#define DEVICE_DRAM_DDR2L_H
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/**
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* @file ddr2.h
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*
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* \brief Utilities for decoding DDR2 SPDs
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*/
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#include <stdint.h>
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#include <spd.h>
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/**
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* \brief Convenience definitions for TCK values
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*
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* Different values for tCK, representing standard DDR2 frequencies.
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* These values are in 1/256 ns units.
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* @{
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*/
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#define TCK_800MHZ 320
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#define TCK_700MHZ 365
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#define TCK_666MHZ 384
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#define TCK_533MHZ 480
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#define TCK_400MHZ 640
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#define TCK_333MHZ 768
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#define TCK_266MHZ 960
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#define TCK_200MHZ 1280
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/** @} */
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/**
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* \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP
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*
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* Use this macro instead of printk(); for verbose RAM initialization messages.
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* When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically
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* disabled.
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* @{
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*/
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#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
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#define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__)
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#else
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#define printram(x, ...)
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#endif
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/** @} */
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/*
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* Module type (byte 20, bits 5:0) of SPD
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* This definition is specific to DDR2. DDR3 SPDs have a different structure.
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*/
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enum spd_dimm_type {
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SPD_DIMM_TYPE_UNDEFINED = 0x00,
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SPD_DIMM_TYPE_RDIMM = 0x01,
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SPD_DIMM_TYPE_UDIMM = 0x02,
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SPD_DIMM_TYPE_SO_DIMM = 0x04,
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SPD_DIMM_TYPE_72B_SO_CDIMM = 0x06,
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SPD_DIMM_TYPE_72B_SO_RDIMM = 0x07,
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SPD_DIMM_TYPE_MICRO_DIMM = 0x08,
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SPD_DIMM_TYPE_MINI_DIMM = 0x10,
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SPD_DIMM_TYPE_MINI_UDIMM = 0x20,
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/* Masks to bits 5:0 to give the dimm type */
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SPD_DIMM_TYPE_MASK = 0x3f,
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};
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/**
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* \brief DIMM flags
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*
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* Characteristic flags for the DIMM, as presented by the SPD
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*/
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union dimm_flags_st {
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/* The whole point of the union/struct construct is to allow us to clear
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* all the bits with one line: flags.raw = 0.
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* We do not care how these bits are ordered */
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struct {
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/* Module can work at 5.00V */
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unsigned operable_5_00V:1;
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/* Module can work at 3.33V */
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unsigned operable_3_33V:1;
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/* Module can work at 2.50V */
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unsigned operable_2_50V:1;
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/* Module can work at 1.80V - All DIMMS must be 1.8V operable */
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unsigned operable_1_80V:1;
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/* Module can work at 1.50V */
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unsigned operable_1_50V:1;
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/* Module can work at 1.35V */
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unsigned operable_1_35V:1;
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/* Module can work at 1.20V */
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unsigned operable_1_25V:1;
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/* Has an 8-bit bus extension, meaning the DIMM supports ECC */
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unsigned is_ecc:1;
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/* Supports weak driver */
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unsigned weak_driver:1;
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/* Supports terminating at 50 Ohm */
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unsigned terminate_50ohms:1;
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/* Partial Array Self Refresh */
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unsigned pasr:1;
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/* Supports burst length 8 */
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unsigned bl8:1;
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/* Supports burst length 4 */
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unsigned bl4:1;
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/* DIMM Package is stack */
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unsigned stacked:1;
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};
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unsigned int raw;
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};
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/**
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* \brief DIMM characteristics
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*
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* The characteristics of each DIMM, as presented by the SPD
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*/
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struct dimm_attr_st {
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enum spd_memory_type dram_type;
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enum spd_dimm_type dimm_type;
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/* BCD SPD revision */
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u8 rev;
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/* Supported CAS mask, bit 0 == CL0 .. bit7 == CL7 */
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u8 cas_supported;
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/* Maximum cloclk to data cycle times for various CAS.
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* Fields 0 and 1 are unused. */
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u32 cycle_time[8];
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/* Maximum data access times for various CAS.
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* Fields 0 and 1 are unused. */
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u32 access_time[8];
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/* Flags extracted from SPD */
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union dimm_flags_st flags;
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/* Number of banks */
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u8 banks;
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/* SDRAM width */
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u8 width;
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/* Module width */
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u8 mod_width;
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/* Number of ranks */
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u8 ranks;
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/* Number or row address bits */
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u8 row_bits;
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/* Number or column address bits */
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u8 col_bits;
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/* Number of PLLs on module */
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u8 plls;
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/* Size of module in MiB */
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u16 size_mb;
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/* Size of one rank in MiB */
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u16 ranksize_mb;
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/* Latencies are in units of 1/256 ns */
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u32 tCK;
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u32 tWR;
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u32 tRCD;
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u32 tRRD;
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u32 tRP;
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u32 tRAS;
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u32 tIS;
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u32 tIH;
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u32 tDS;
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u32 tDH;
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u32 tRC;
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u32 tRFC;
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u32 tWTR;
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u32 tRTP;
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u32 tDQSQ;
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u32 tQHS;
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/* Latencies are in units of 1/256 us */
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u32 tPLL;
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u32 tRR;
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/* Manufacturer ID */
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u32 manufacturer_id;
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/* ASCII part number - NULL terminated */
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u8 part_number[17];
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/* Year manufactured */
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u16 year;
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/* Week manufactured */
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u8 weeks;
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/* Unique serial number */
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u32 serial;
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};
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/** Result of the SPD decoding process */
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enum spd_status {
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SPD_STATUS_OK = 0,
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SPD_STATUS_INVALID,
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SPD_STATUS_CRC_ERROR,
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SPD_STATUS_INVALID_FIELD,
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};
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/** Maximum SPD size supported */
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#define SPD_SIZE_MAX_DDR2 128
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int spd_dimm_is_registered_ddr2(enum spd_dimm_type type);
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u8 spd_ddr2_calc_checksum(u8 *spd, int len);
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u32 spd_decode_spd_size_ddr2(u8 byte0);
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u32 spd_decode_eeprom_size_ddr2(u8 byte1);
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int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2]);
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void dram_print_spd_ddr2(const struct dimm_attr_st *dimm);
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#endif /* DEVICE_DRAM_DDR2L_H */
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@@ -201,7 +201,7 @@ typedef u8 spd_raw_data[256];
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u16 spd_ddr3_calc_crc(u8 *spd, int len);
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u16 spd_ddr3_calc_unique_crc(u8 *spd, int len);
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int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd_data);
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int dimm_is_registered(enum spd_dimm_type type);
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int spd_dimm_is_registered_ddr3(enum spd_dimm_type type);
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void dram_print_spd_ddr3(const dimm_attr * dimm);
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int spd_xmp_decode_ddr3(dimm_attr * dimm,
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spd_raw_data spd,
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