sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Jetway NF81-T56N-LF [2/2]: actually implement mainboard support.

Browse Source 
Step 2: change the Persimmon code to adapt it to the new board's hardware.

The NF81-T56N-LF is a IPC form factor embedded board:
- AMD Fusion G-T56N (1.65 GHz dual core) APU
  - 2x SO-DIMM sockets for DDR3 800-1066 SDRAM (Fixed at 1.5V)
  - VGA and LVDS (via Analogix ANX3110)
- AMD A55E (Hudson-E1) southbridge
  - 6x USB 2.0/1.1 ports
  - 5x SATA3 6Gb/s, 1x mSATA socket
  - 6-Channel HD Audio (via VIA VT1705)
  - PCI and ISA (via ITE IT8888)??
  - NEC uPD78F0532 microcontroller on I2C ("SEMA")??
- 2x RJ45 GbE (via Realtek RTL8111E x2)
- Fintek F71869AD Super I/O
  - PS/2 KB/MS port
  - RS232 header (via Unisonic UTC 75232 RS232 driver/receiver)
  - GPIO header
  - CIR header
- 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)

Note: MX25L1606E is 16Mbit, 8bits in a byte, so 2MB. Jetway *lies*
claiming the SPI flash is 16MB. They also use red pen over the chip
so you wont see this deceit.

Change-Id: I03ccc58bc782e800aeef0d19679ce060277b0c04
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/4801
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Edward O'Callaghan
2014-01-25 21:46:10 +11:00
committed by Alexandru Gagniuc
parent 4726a87c9a
commit 6e56de3d20
6 changed files with 69 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/jetway/Kconfig
View File

@@ -11,6 +11,8 @@ config BOARD_JETWAY_J7F4K1G5D
bool "J7F4K1G5D" bool "J7F4K1G5D"
config BOARD_JETWAY_PA78VM5 config BOARD_JETWAY_PA78VM5
bool "PA78VM5 (Fam10)" bool "PA78VM5 (Fam10)"
config BOARD_JETWAY_NF81_T56N_LF
bool "NF81_T56N_LF"
endchoice endchoice
@@ -18,6 +20,7 @@ source "src/mainboard/jetway/j7f2/Kconfig"
source "src/mainboard/jetway/j7f4k1g2e/Kconfig" source "src/mainboard/jetway/j7f4k1g2e/Kconfig"
source "src/mainboard/jetway/j7f4k1g5d/Kconfig" source "src/mainboard/jetway/j7f4k1g5d/Kconfig"
source "src/mainboard/jetway/pa78vm5/Kconfig" source "src/mainboard/jetway/pa78vm5/Kconfig"
source "src/mainboard/jetway/nf81-t56n-lf/Kconfig"
config MAINBOARD_VENDOR config MAINBOARD_VENDOR
string string

18
src/mainboard/jetway/nf81-t56n-lf/Kconfig
View File

@@ -2,6 +2,7 @@
# This file is part of the coreboot project. # This file is part of the coreboot project.
# #
# Copyright (C) 2011 Advanced Micro Devices, Inc. # Copyright (C) 2011 Advanced Micro Devices, Inc.
# Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>.
# #
# This program is free software; you can redistribute it and/or modify # This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by # it under the terms of the GNU General Public License as published by
@@ -17,7 +18,7 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
# #
if BOARD_AMD_PERSIMMON if BOARD_JETWAY_NF81_T56N_LF
config BOARD_SPECIFIC_OPTIONS # dummy config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y def_bool y
@@ -25,22 +26,23 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select CPU_AMD_AGESA_FAMILY14 select CPU_AMD_AGESA_FAMILY14
select NORTHBRIDGE_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14
select SOUTHBRIDGE_AMD_CIMX_SB800 select SOUTHBRIDGE_AMD_CIMX_SB800
select SUPERIO_FINTEK_F81865F select SUPERIO_FINTEK_F71869AD
select HAVE_OPTION_TABLE select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE select HAVE_MP_TABLE
select HAVE_ACPI_RESUME # FIXME: Disable S3 for now. Enable by default once stabilised.
# select HAVE_ACPI_RESUME
select SB_HT_CHAIN_UNITID_OFFSET_ONLY select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT select SERIAL_CPU_INIT
select AMDMCT select AMDMCT
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096 select BOARD_ROMSIZE_KB_2048
select GFXUMA select GFXUMA
config MAINBOARD_DIR config MAINBOARD_DIR
string string
default amd/persimmon default jetway/nf81-t56n-lf
config APIC_ID_OFFSET config APIC_ID_OFFSET
hex hex
@@ -48,7 +50,7 @@ config APIC_ID_OFFSET
config MAINBOARD_PART_NUMBER config MAINBOARD_PART_NUMBER
string string
default "Persimmon" default "NF81-T56N-LF"
config HW_MEM_HOLE_SIZEK config HW_MEM_HOLE_SIZEK
hex hex
@@ -101,7 +103,7 @@ config VGA_BIOS
config VGA_BIOS_ID config VGA_BIOS_ID
string string
default "1002,9802" default "1002,9806" # FUSION_G_T56N
config SB800_AHCI_ROM config SB800_AHCI_ROM
bool bool
@@ -111,4 +113,4 @@ config DRIVERS_PS2_KEYBOARD
bool bool
default n default n
endif # BOARD_AMD_PERSIMMON endif # BOARD_JETWAY_NF81_T56N_LF

5
src/mainboard/jetway/nf81-t56n-lf/board_info.txt
View File

@@ -1,5 +1,6 @@
Board name: DBFT1-00-EVAL-KT (Persimmon) Board URL: http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=822&proname=NF81-T56N-LF
Category: eval Category: Mini-ITX
ROM package: SOIC8
ROM protocol: SPI ROM protocol: SPI
ROM socketed: n ROM socketed: n
Flashrom support: y Flashrom support: y

66
src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
View File

@@ -2,6 +2,7 @@
# This file is part of the coreboot project. # This file is part of the coreboot project.
# #
# Copyright (C) 2011 Advanced Micro Devices, Inc. # Copyright (C) 2011 Advanced Micro Devices, Inc.
# Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>.
# #
# This program is free software; you can redistribute it and/or modify # This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by # it under the terms of the GNU General Public License as published by
@@ -29,7 +30,8 @@ chip northbridge/amd/agesa/family14/root_complex
chip northbridge/amd/agesa/family14 # PCI side of HT root complex chip northbridge/amd/agesa/family14 # PCI side of HT root complex
device pci 0.0 on end # Root Complex device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
device pci 4.0 on end # PCIE P2P bridge on-board NIC # device pci 1.1 on end # Internal Audio P2P bridge 0x1314
device pci 4.0 off end
device pci 5.0 off end # PCIE P2P bridge device pci 5.0 off end # PCIE P2P bridge
device pci 6.0 on end # PCIE P2P bridge PCIe slot device pci 6.0 on end # PCIE P2P bridge PCIe slot
device pci 7.0 off end # PCIE P2P bridge device pci 7.0 off end # PCIE P2P bridge
@@ -50,47 +52,64 @@ chip northbridge/amd/agesa/family14/root_complex
device i2c 51 on end device i2c 51 on end
end end
end # SM end # SM
device pci 14.1 on end # IDE 0x439c device pci 14.1 off end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383 device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d device pci 14.3 on # LPC 0x439d
chip superio/fintek/f81865f chip superio/fintek/f71869ad
device pnp 4e.0 off # Floppy # XXX: 4e is the default index port and .xy is the
# LDN indexing the pnp_info array found in the superio.c
# NB: Jetway board changes the default (0x4e) index port to (0x2e) by pin 124,
# see page 18 from Fintek F71869 V1.1 datasheet.
device pnp 2e.00 off # Floppy
io 0x60 = 0x3f0 io 0x60 = 0x3f0
irq 0x70 = 6 irq 0x70 = 6
drq 0x74 = 2 drq 0x74 = 2
end end
device pnp 4e.3 off end # Parallel Port device pnp 2e.01 on # COM1
device pnp 4e.4 off end # Hardware Monitor
device pnp 4e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
end
device pnp 4e.6 off end # GPIO
device pnp 4e.a off end # PME
device pnp 4e.10 on # COM1
io 0x60 = 0x3f8 io 0x60 = 0x3f8
irq 0x70 = 4 irq 0x70 = 4
end end
device pnp 4e.11 on # COM2 # COM2 not physically wired on board.
device pnp 2e.02 off # COM2
io 0x60 = 0x2f8 io 0x60 = 0x2f8
irq 0x70 = 3 irq 0x70 = 3
end end
end # f81865f device pnp 2e.03 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
drq 0x74 = 3
end
device pnp 2e.04 on # Hardware Monitor
io 0x60 = 0x295
irq 0x70 = 0
end
device pnp 2e.05 on # KBC
io 0x60 = 0x060
irq 0x70 = 1 # Keyboard IRQ
irq 0x72 = 12 # Mouse IRQ
end
device pnp 2e.06 off end # GPIO
# TODO: Verify BSEL register content with vendor BIOS using
# $ sudo isadump 0x4e 0x4f 0x7
# which select logical device (LDN) 7. Then read that we have in 0x27, bit1
device pnp 2e.07 on end # BSEL
device pnp 2e.0a off end # PME
end # f71869ad
end #LPC end #LPC
device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 off end # OHCI FS/LS USB device pci 14.5 on end # OHCI FS/LS USB (0x4399)
device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
device pci 15.0 off end # PCIe PortA device pci 15.0 on end # PCIe PortA (0x43a0) GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168)
device pci 15.1 off end # PCIe PortB device pci 15.1 off end # PCIe PortB
device pci 15.2 off end # PCIe PortC device pci 15.2 off end # PCIe PortC
device pci 15.3 off end # PCIe PortD device pci 15.3 off end # PCIe PortD
device pci 16.0 off end # OHCI USB 10-13 device pci 16.0 on end # OHCI USB 10-13 (0x4397)
device pci 16.2 off end # EHCI USB 10-13 device pci 16.2 on end # EHCI USB 10-13 (0x4396)
register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
#set up SB800 Fan control registers and IMC fan controls # Set up SB800 Fan control registers and IMC fan controls
# TODO: verify SB handles the HW monitor and not the super io (PME)
register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common
register "fan0_enabled" = "1" register "fan0_enabled" = "1"
register "fan1_enabled" = "1" register "fan1_enabled" = "1"
@@ -150,6 +169,11 @@ chip northbridge/amd/agesa/family14/root_complex
device pci 18.6 on end device pci 18.6 on end
device pci 18.7 on end device pci 18.7 on end
#
# TODO: Verify the proper SocketId/MemChannelId/DimmId addresses of the SPD
# with i2cdump tool.
# Notes: 0xa0=0x50*2, 0xa2=0x51*2.. 0x50-0x54 are usually RAM modules on the SMBus.
#
register "spdAddrLookup" = " register "spdAddrLookup" = "
{ {
{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses

3
src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h
View File

@@ -2,6 +2,7 @@
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright (C) 2011 Advanced Micro Devices, Inc. * Copyright (C) 2011 Advanced Micro Devices, Inc.
* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@@ -211,6 +212,7 @@
*/ */
#define GEC_CONFIG 0 #define GEC_CONFIG 0
/* FIXME: Verify this for sound to work! */
static const CODECENTRY persimmon_codec_alc269[] = static const CODECENTRY persimmon_codec_alc269[] =
{ {
/* NID, PinConfig */ /* NID, PinConfig */
@@ -228,6 +230,7 @@ static const CODECENTRY persimmon_codec_alc269[] =
{0xff, 0xffffffff} /* end of table */ {0xff, 0xffffffff} /* end of table */
}; };
/* FIXME: Verify this for sound to work! */
static const CODECTBLLIST codec_tablelist[] = static const CODECTBLLIST codec_tablelist[] =
{ {
{0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]}, {0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]},

8
src/mainboard/jetway/nf81-t56n-lf/romstage.c
View File

@@ -2,6 +2,7 @@
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright (C) 2011 Advanced Micro Devices, Inc. * Copyright (C) 2011 Advanced Micro Devices, Inc.
* Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@@ -31,7 +32,7 @@
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include "agesawrapper.h" #include "agesawrapper.h"
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#include "superio/fintek/f81865f/f81865f_early_serial.c" #include "superio/fintek/f71869ad/f71869ad.h"
#include "cpu/x86/lapic.h" #include "cpu/x86/lapic.h"
#include "drivers/pc80/i8254.c" #include "drivers/pc80/i8254.c"
#include "drivers/pc80/i8259.c" #include "drivers/pc80/i8259.c"
@@ -45,7 +46,8 @@
void disable_cache_as_ram(void); /* cache_as_ram.inc */ void disable_cache_as_ram(void); /* cache_as_ram.inc */
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) /* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */
#define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
@@ -70,7 +72,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sb_Poweron_Init(); sb_Poweron_Init();
post_code(0x31); post_code(0x31);
f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); f71869ad_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();
} }