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mb/ocp/deltalake: Fill ECC type in romstage

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Fill the ECC type in `struct memory_info` in romstage, and in SoC code.
The SMBIOS override is unnecessary, and this is not mainboard-specific.

Change-Id: I8370b3ee7d75914b895946b53923598adf87b522
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50179
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
2021-01-31 15:15:11 +01:00
committed by Patrick Georgi
parent 6724ba4f04
commit 6e82ebff73
4 changed files with 21 additions and 32 deletions
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7
src/arch/x86/smbios.c
View File

@@ -443,11 +443,6 @@ static int get_socket_type(void)
return 0x02; /* Unknown */
}
unsigned int __weak smbios_memory_error_correction_type(struct memory_info *meminfo)
{
return meminfo->ecc_type;
}
unsigned int __weak smbios_processor_external_clock(void)
{
return 0; /* Unknown */
@@ -1023,7 +1018,7 @@ static int smbios_write_type16(unsigned long *current, int *handle)
t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD;
t->use = MEMORY_ARRAY_USE_SYSTEM;
t->memory_error_correction = smbios_memory_error_correction_type(meminfo);
t->memory_error_correction = meminfo->ecc_type;
/* no error information handle available */
t->memory_error_information_handle = 0xFFFE;

1
src/include/smbios.h
View File

@@ -61,7 +61,6 @@ void smbios_type0_bios_version(uintptr_t address);
void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision);
unsigned int smbios_memory_error_correction_type(struct memory_info *meminfo);
unsigned int smbios_processor_external_clock(void);
unsigned int smbios_processor_characteristics(void);
struct cpuid_result;

25
src/mainboard/ocp/deltalake/ramstage.c
View File

@@ -23,31 +23,6 @@
extern struct fru_info_str fru_strings;
static char slot_id_str[SLOT_ID_LEN];
/* Override SMBIOS type 16 error correction type. */
unsigned int smbios_memory_error_correction_type(struct memory_info *meminfo)
{
const struct SystemMemoryMapHob *hob;
hob = get_system_memory_map();
assert(hob != NULL);
switch (hob->RasModesEnabled) {
case CH_INDEPENDENT:
return MEMORY_ARRAY_ECC_SINGLE_BIT;
case FULL_MIRROR_1LM:
case PARTIAL_MIRROR_1LM:
case FULL_MIRROR_2LM:
case PARTIAL_MIRROR_2LM:
return MEMORY_ARRAY_ECC_MULTI_BIT;
case RK_SPARE:
return MEMORY_ARRAY_ECC_SINGLE_BIT;
case CH_LOCKSTEP:
return MEMORY_ARRAY_ECC_SINGLE_BIT;
default:
return MEMORY_ARRAY_ECC_MULTI_BIT;
}
}
/*
* Update SMBIOS type 0 ec version.
* In deltalake, BMC version is used to represent ec version.

20
src/soc/intel/xeon_sp/cpx/romstage.c
View File

@@ -37,6 +37,25 @@ static const struct SystemMemoryMapHob *get_system_memory_map(void)
return *memmap_addr;
}
static uint8_t get_error_correction_type(const uint8_t RasModesEnabled)
{
switch (RasModesEnabled) {
case CH_INDEPENDENT:
return MEMORY_ARRAY_ECC_SINGLE_BIT;
case FULL_MIRROR_1LM:
case PARTIAL_MIRROR_1LM:
case FULL_MIRROR_2LM:
case PARTIAL_MIRROR_2LM:
return MEMORY_ARRAY_ECC_MULTI_BIT;
case RK_SPARE:
return MEMORY_ARRAY_ECC_SINGLE_BIT;
case CH_LOCKSTEP:
return MEMORY_ARRAY_ECC_SINGLE_BIT;
default:
return MEMORY_ARRAY_ECC_MULTI_BIT;
}
}
/* Save the DIMM information for SMBIOS table 17 */
void save_dimm_info(void)
{
@@ -63,6 +82,7 @@ void save_dimm_info(void)
/* According to Dear Customer Letter it's 1.12 TB per processor. */
mem_info->max_capacity_mib = 1.12 * MiB * CONFIG_MAX_SOCKET;
mem_info->number_of_devices = CONFIG_DIMM_MAX;
mem_info->ecc_type = get_error_correction_type(hob->RasModesEnabled);
dimm_max = ARRAY_SIZE(mem_info->dimm);
vdd_voltage = get_ddr_voltage(hob->DdrVoltage);
/* For now only implement for one socket and hard-coded for DDR4 */