soc/common/smbus: Add support for reading spd data via smbus for DDR5

DDR5 uses a Serial Presence Detect EEPROM with hub function
(SPD5 hub device) to store the spd data.
This CL adds support to read the spd5 hub device via smbus.

BUG=b:180458099
TEST=Boot adlrvp DDR5 board to kernel

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe

src/include/spd_bin.h

@@ -35,6 +35,18 @@
 #define DDR4_SPD_PART_OFF	329
 #define DDR4_SPD_PART_LEN	20
 #define DDR4_SPD_SN_OFF		325
+#define MAX_SPD_PAGE_SIZE_SPD5	128
+#define MAX_SPD_SIZE		(SPD_PAGE_LEN * SPD_SN_LEN)
+#define SPD_HUB_MEMREG(addr)	((u8)(0x80 | (addr)))
+#define SPD5_MR11		0x0B
+#define SPD5_MR0		0x00
+#define SPD5_MEMREG_REG(addr)	((u8)((~0x80) & (addr)))
+#define SPD5_MR0_SPD5_HUB_DEV	0x51
+
+struct spd_offset_table {
+	u16 start;		/* Offset 0 */
+	u16 end;		/* Offset 2 */
+};
 
 struct spd_block {
 	u8 addr_map[CONFIG_DIMM_MAX]; /* 7 bit I2C addresses */

src/soc/intel/common/block/smbus/smbuslib.c

@@ -6,6 +6,17 @@
 #include <device/smbus_host.h>
 #include "smbuslib.h"
 
+static const struct spd_offset_table spd_ddr5_table[] = {
+{   0,               1 }, /* General Configuration section */
+{   2,               2 }, /* General Configuration section */
+{   3,              47 }, /* General Configuration section */
+{ 126,             127 }, /* General Configuration section */
+{ 192,             213 }, /* Module-Specific section */
+{ 230,             235 }, /* Module-Specific section */
+{ 512,             520 }, /* Module Supplier's data */
+{ 521,             550 }, /* Module Supplier's data */
+};
+
 static void update_spd_len(struct spd_block *blk)
 {
 	u8 i, j = 0;
@@ -37,6 +48,62 @@ static void smbus_read_spd(u8 *spd, u8 addr)
 	}
 }
 
+static void switch_page(u8 spd_addr, u8 new_page)
+{
+	u32 offset;
+	/*
+	*  By default,an SPD5 hub accepts 1 byte addressing pointing
+	*  to the first 128 bytes of memory. MR11[2:0] selects the page
+	*  pointer to address the entire 1024 bytes of non-volatile memory.
+	*/
+	offset = SPD5_MEMREG_REG(SPD5_MR11);
+	smbus_write_byte(spd_addr, offset, new_page);
+}
+
+/*
+ * Read the SPD data over the SMBus, at the specified SPD address,
+ * starting at the specified starting offset and read the given amount of data.
+ */
+static void smbus_read_spd5(u8 *spd, u8 spd_addr, const u16 start, u8 size, u8 *const page)
+{
+	u16 index;
+	u32 max_page_size = MAX_SPD_PAGE_SIZE_SPD5;
+
+	if ((start + size) >= MAX_SPD_SIZE) {
+		printk(BIOS_ERR, "Maximum SPD size reached\n");
+		return;
+	}
+	for (int i = 0; i < size; i++) {
+		index = start + i;
+		u8 next_page = index / max_page_size;
+		if (next_page != *page) {
+			switch_page(spd_addr, next_page);
+			*page = next_page;
+		}
+		unsigned int byte_addr = SPD_HUB_MEMREG(index % max_page_size);
+		spd[index] = smbus_read_byte(spd_addr, byte_addr);
+	}
+}
+
+/* Read SPD5 MR0 and check if SPD Byte 0 matches the SPD5 HUB MR0 identifier.*/
+static int is_spd5_hub(u8 spd_addr)
+{
+	u8 spd_hub_byte;
+
+	spd_hub_byte = smbus_read_byte(spd_addr, SPD5_MEMREG_REG(SPD5_MR0));
+	return spd_hub_byte == SPD5_MR0_SPD5_HUB_DEV;
+}
+
+/*
+ * Reset the SPD page back to page 0 on an SPD5 Hub device at the
+ * input SPD SMbus address.
+ */
+static void reset_page_spd5(u8 spd_addr)
+{
+	/* Set SPD5 MR11[2:0] = 0 (Page 0) */
+	smbus_write_byte(spd_addr, SPD5_MEMREG_REG(SPD5_MR11), 0);
+}
+
 /* return -1 if SMBus errors otherwise return 0 */
 static int get_spd(u8 *spd, u8 addr)
 {
@@ -47,22 +114,42 @@ static int get_spd(u8 *spd, u8 addr)
 		return -1;
 	}
 
-	if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd) < 0) {
+	if (is_spd5_hub(addr)) {
-		printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n");
+		const struct spd_offset_table *tbl;
-		smbus_read_spd(spd, addr);
+		u32 byte;
-	}
+		u32 stop;
+		u8 page;
+		page = (u8) (~0);
+		stop = ARRAY_SIZE(spd_ddr5_table);
 
-	/* Check if module is DDR4, DDR4 spd is 512 byte. */
+		for (byte = 0; byte < stop; byte++) {
-	if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 && CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) {
+			tbl = &spd_ddr5_table[byte];
-		/* Switch to page 1 */
+			smbus_read_spd5(spd, addr,  tbl->start,
-		smbus_write_byte(SPD_PAGE_1, 0, 0);
+					tbl->end - tbl->start + 1, &page);
-
+		}
-		if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd + SPD_PAGE_LEN) < 0) {
+
-			printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n");
+		/* Reset the page for the next loop iteration */
-			smbus_read_spd(spd + SPD_PAGE_LEN, addr);
+		reset_page_spd5(addr);
+	} else {
+
+		if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd) < 0) {
+			printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n");
+			smbus_read_spd(spd, addr);
+		}
+
+		/* Check if module is DDR4, DDR4 spd is 512 byte. */
+		if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 &&
+					CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) {
+			/* Switch to page 1 */
+			smbus_write_byte(SPD_PAGE_1, 0, 0);
+
+			if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd + SPD_PAGE_LEN) < 0) {
+				printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n");
+				smbus_read_spd(spd + SPD_PAGE_LEN, addr);
+			}
+			/* Restore to page 0 */
+			smbus_write_byte(SPD_PAGE_0, 0, 0);
 		}
-		/* Restore to page 0 */
-		smbus_write_byte(SPD_PAGE_0, 0, 0);
 	}
 	return 0;
 }