soc/{amd,intel}: Use postcar_frame_add_romcache()

Change-Id: Iee816628ac3c33633f5f45798562a4ce49493a65
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/amd/stoneyridge/romstage.c

@@ -128,8 +128,7 @@ asmlinkage void car_stage_entry(void)
 		MTRR_TYPE_WRBACK);
 
 	/* Cache the memory-mapped boot media. */
-	postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
-					MTRR_TYPE_WRPROT);
+	postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
 
 	/*
 	 * Cache the TSEG region at the top of ram. This region is

src/soc/intel/apollolake/romstage.c

@@ -233,9 +233,7 @@ asmlinkage void car_stage_entry(void)
 		MTRR_TYPE_WRBACK);
 
 	/* Cache the memory-mapped boot media. */
-	if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED))
-		postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
-					MTRR_TYPE_WRPROT);
+	postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
 
 	/*
 	* Cache the TSEG region at the top of ram. This region is

src/soc/intel/cannonlake/romstage/romstage.c

@@ -142,8 +142,7 @@ asmlinkage void car_stage_entry(void)
 	postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
 
 	/* Cache the ROM as WP just below 4GiB. */
-	postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
-			       MTRR_TYPE_WRPROT);
+	postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
 
 	run_postcar_phase(&pcf);
 }

src/soc/intel/denverton_ns/romstage.c

@@ -172,9 +172,8 @@ asmlinkage void car_stage_entry(void)
 			       MTRR_TYPE_WRBACK);
 
 	/* Cache the memory-mapped boot media. */
-	if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED))
-		postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
-				       MTRR_TYPE_WRPROT);
+	postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
+
 #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
 	/*
 	 * Cache the TSEG region at the top of ram. This region is

src/soc/intel/quark/romstage/fsp2_0.c

@@ -80,8 +80,7 @@ asmlinkage void *car_stage_c_entry(void)
 	postcar_frame_add_mtrr(&pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK);
 
 	/* Cache SPI flash - Write protect not supported */
-	postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
-			       MTRR_TYPE_WRTHROUGH);
+	postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRTHROUGH);
 
 	run_postcar_phase(&pcf);
 	return NULL;

src/soc/intel/skylake/romstage/romstage_fsp20.c

@@ -186,8 +186,7 @@ asmlinkage void car_stage_entry(void)
 	}
 
 	/* Cache the ROM as WP just below 4GiB. */
-	postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
-			       MTRR_TYPE_WRPROT);
+	postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
 
 	run_postcar_phase(&pcf);
 }