riscv: get SBI calls to work

SBI calls, as it turned out, were never right.
They did not set the stack correctly on traps.
They were not correctly setting the MIP instead of the SIP
(although this was not really well documented).
On Harvey, we were trying to avoid using them,
and due to a bug in SPIKE, our avoidance worked.
Once SPIKE was fixed, our avoidance broke.

This set of changes is tested and working with Harvey
which, for the first time, is making SBI calls.

It's not pretty and we're going to want to rework
trap_util.S in coming days.

Change-Id: Ibef530adcc58d33e2c44ff758e0b7d2acbdc5e99
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/18097
Tested-by: build bot (Jenkins)

src/arch/riscv/bootblock.S

@@ -16,6 +16,7 @@
  */
 
 #include <arch/encoding.h>
+#include <mcall.h>
 
 .section ".text._start", "ax", %progbits
 
@@ -30,8 +31,14 @@ _start:
 	# and the stack must be page-aligned.
 	la sp, _estack
 
+	# poison the stack
+	la t1, _stack
+	li t0, 0xdeadbeef
+	sd t0, 0(t1)
+
 	# make room for HLS and initialize it
-	addi sp, sp, -64 // MENTRY_FRAME_SIZE
+	addi sp, sp, -HLS_SIZE
+
 	// Once again, the docs and toolchain disagree.
 	// Rather than get fancy I'll just lock this down
 	// until it all stabilizes.
@@ -39,11 +46,6 @@ _start:
 	csrr a0, 0xf14
 	call hls_init
 
-	# poison the stack
-	la t1, _stack
-	li t0, 0xdeadbeef
-	sd t0, 0(t1)
-
 	la t0, trap_entry
 	csrw mtvec, t0