Fix all warnings in the tree

(does not fix the cmos.layout race yet)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/cpu/amd/car/cache_as_ram.inc

@@ -37,16 +37,16 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
 /*
- XMM map:
-    xmm1: cpu family
-    xmm2: fam10 comparison value
-    xmm3: backup ebx
-*/
+ * XMM map:
+ *   xmm1: cpu family
+ *   xmm2: fam10 comparison value
+ *   xmm3: backup ebx
+ */
 
 	/* Save the BIST result */
 	movl	%eax, %ebp
 
-	/*for normal part %ebx already contain cpu_init_detected from fallback call */
+	/* for normal part %ebx already contain cpu_init_detected from fallback call */
 
 cache_as_ram_setup:
 	post_code(0xa0)
@@ -113,7 +113,8 @@ cache_as_ram_setup:
 CAR_FAM10_out:
 
 	/* Errata 193: Disable clean copybacks to L3 cache to allow cached ROM.
-	   Re-enable it in after RAM is initialized and before CAR is disabled */
+	 * Re-enable it in after RAM is initialized and before CAR is disabled
+	 */
 	movl	$0xc001102a, %ecx
 	rdmsr
 	bts	$15, %eax

src/cpu/amd/dualcore/dualcore_id.c

@@ -47,7 +47,7 @@ static inline unsigned get_core_num(void)
 	return (cpuid_ecx(0x80000008) & 0xff);
 }
 
-static inline struct node_core_id get_node_core_id_x(void)
+struct node_core_id get_node_core_id_x(void)
 {
 
 	return get_node_core_id(read_nb_cfg_54()); // for pre_e0() nb_cfg_54 always be 0

src/cpu/amd/model_10xxx/init_cpus.c

@@ -417,7 +417,7 @@ static u32 is_core0_started(u32 nodeid)
 	return htic;
 }
 
-static void wait_all_core0_started(void)
+void wait_all_core0_started(void)
 {
 	/* When core0 is started, it will distingush_cpu_resets
 	 * So wait for that to finish */

src/cpu/amd/model_fxx/init_cpus.c

@@ -326,7 +326,7 @@ static u32 is_core0_started(u32 nodeid)
 	return htic;
 }
 
-static void wait_all_core0_started(void)
+void wait_all_core0_started(void)
 {
 	/* When core0 is started, it will distingush_cpu_resets
 	 * So wait for that to finish */

src/cpu/amd/quadcore/quadcore_id.c

@@ -74,7 +74,7 @@ static u32 get_core_num(void)
 }
 #endif
 
-static struct node_core_id get_node_core_id_x(void)
+struct node_core_id get_node_core_id_x(void)
 {
 	return get_node_core_id(read_nb_cfg_54());
 }