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usbdebug: Remove EHCI_DEBUG_OFFSET

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Read this variable from PCI configuration capabilities list instead.

Change-Id: I0cfe981833873397c32cd3aa2af307f35f01784b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5176
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Kyösti Mälkki
2014-02-09 19:21:30 +02:00
parent 6e56de3d20
commit 6f6a249a75
21 changed files with 30 additions and 78 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
src/drivers/usb/ehci_debug.c
View File

@ -569,6 +569,8 @@ static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_
int port_map_tried; int port_map_tried;
int playtimes = 3; int playtimes = 3;
dprintk(BIOS_INFO, "ehci_bar: 0x%x debug_offset 0x%x\n", ehci_bar, offset);
ehci_caps = (struct ehci_caps *)ehci_bar; ehci_caps = (struct ehci_caps *)ehci_bar;
ehci_regs = (struct ehci_regs *)(ehci_bar + ehci_regs = (struct ehci_regs *)(ehci_bar +
HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase))); HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase)));
@ -589,7 +591,6 @@ try_next_port:
debug_port = HCS_DEBUG_PORT(hcs_params); debug_port = HCS_DEBUG_PORT(hcs_params);
n_ports = HCS_N_PORTS(hcs_params); n_ports = HCS_N_PORTS(hcs_params);
dprintk(BIOS_INFO, "ehci_bar: 0x%x\n", ehci_bar);
dprintk(BIOS_INFO, "debug_port: %d\n", debug_port); dprintk(BIOS_INFO, "debug_port: %d\n", debug_port);
dprintk(BIOS_INFO, "n_ports: %d\n", n_ports); dprintk(BIOS_INFO, "n_ports: %d\n", n_ports);
@ -926,11 +927,13 @@ struct dbgp_pipe *dbgp_console_input(void)
int usbdebug_init(void) int usbdebug_init(void)
{ {
struct ehci_debug_info *dbg_info = dbgp_ehci_info(); struct ehci_debug_info *dbg_info = dbgp_ehci_info();
unsigned int ehci_base, dbg_offset;
#if !defined(__PRE_RAM__) && !defined(__SMM__) #if !defined(__PRE_RAM__) && !defined(__SMM__)
if (!get_usbdebug_from_cbmem(dbg_info)) if (!get_usbdebug_from_cbmem(dbg_info))
return 0; return 0;
#endif #endif
ehci_debug_hw_enable(); if (ehci_debug_hw_enable(&ehci_base, &dbg_offset))
return usbdebug_init_(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info); return -1;
return usbdebug_init_(ehci_base, dbg_offset, dbg_info);
} }

6
src/drivers/usb/ehci_debug.h
View File

@ -24,10 +24,12 @@
void usbdebug_re_enable(unsigned ehci_base); void usbdebug_re_enable(unsigned ehci_base);
void usbdebug_disable(void); void usbdebug_disable(void);
void ehci_debug_hw_enable(void); /* Returns 0 on success and sets MMIO base and dbg_offset if EHCI debug
* capability was found and enabled. Returns non-zero on error.
*/
int ehci_debug_hw_enable(unsigned *base, unsigned *dbg_offset);
void ehci_debug_select_port(unsigned int port); void ehci_debug_select_port(unsigned int port);
#define DBGP_EP_VALID (1<<0) #define DBGP_EP_VALID (1<<0)
#define DBGP_EP_ENABLED (1<<1) #define DBGP_EP_ENABLED (1<<1)
#define DBGP_EP_BUSY (1<<2) #define DBGP_EP_BUSY (1<<2)

22
src/drivers/usb/pci_ehci.c
View File

@ -34,12 +34,30 @@ static struct device_operations *ehci_drv_ops;
static struct device_operations ehci_dbg_ops; static struct device_operations ehci_dbg_ops;
#endif #endif
void ehci_debug_hw_enable(void) int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset)
{ {
#if defined(__PRE_RAM__) || !CONFIG_USBDEBUG_IN_ROMSTAGE
pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
pci_ehci_dbg_enable(dbg_dev, CONFIG_EHCI_BAR); pci_ehci_dbg_enable(dbg_dev, CONFIG_EHCI_BAR);
#ifdef __SIMPLE_DEVICE__
pci_devfn_t dev = dbg_dev;
#else
device_t dev = dev_find_slot(PCI_DEV2SEGBUS(dbg_dev), PCI_DEV2DEVFN(dbg_dev));
#endif #endif
u8 pos = pci_find_capability(dev, PCI_CAP_ID_EHCI_DEBUG);
if (!pos)
return -1;
u32 cap = pci_read_config32(dev, pos);
/* FIXME: We should remove static EHCI_BAR_INDEX. */
u8 dbg_bar = 0x10 + 4 * ((cap >> 29) - 1);
if (dbg_bar != EHCI_BAR_INDEX)
return -1;
*base = CONFIG_EHCI_BAR;
*dbg_offset = (cap>>16) & 0x1ffc;
return 0;
} }
void ehci_debug_select_port(unsigned int port) void ehci_debug_select_port(unsigned int port)

4
src/southbridge/amd/agesa/hudson/Kconfig
View File

@ -43,10 +43,6 @@ config EHCI_BAR
hex hex
default 0xfef00000 default 0xfef00000
config EHCI_DEBUG_OFFSET
hex
default 0xe0
config HUDSON_XHCI_ENABLE config HUDSON_XHCI_ENABLE
bool "Enable Hudson XHCI Controller" bool "Enable Hudson XHCI Controller"
default y default y

4
src/southbridge/amd/cimx/sb700/Kconfig
View File

@ -54,10 +54,6 @@ config EHCI_BAR
hex hex
default 0xfef00000 default 0xfef00000
config EHCI_DEBUG_OFFSET
hex
default 0xe0
config BOOTBLOCK_SOUTHBRIDGE_INIT config BOOTBLOCK_SOUTHBRIDGE_INIT
string string
default "southbridge/amd/cimx/sb700/bootblock.c" default "southbridge/amd/cimx/sb700/bootblock.c"

4
src/southbridge/amd/cimx/sb800/Kconfig
View File

@ -209,10 +209,6 @@ config EHCI_BAR
hex hex
default 0xfef00000 default 0xfef00000
config EHCI_DEBUG_OFFSET
hex
default 0xe0
choice choice
prompt "Fan Control" prompt "Fan Control"
default SB800_NO_FAN_CONTROL default SB800_NO_FAN_CONTROL

4
src/southbridge/amd/sb600/Kconfig
View File

@ -32,10 +32,6 @@ config EHCI_BAR
hex hex
default 0xfef00000 default 0xfef00000
config EHCI_DEBUG_OFFSET
hex
default 0xe0
choice choice
prompt "SATA Mode" prompt "SATA Mode"
default SATA_MODE_IDE default SATA_MODE_IDE

4
src/southbridge/amd/sb700/Kconfig
View File

@ -45,8 +45,4 @@ config EHCI_BAR
hex hex
default 0xfef00000 default 0xfef00000
config EHCI_DEBUG_OFFSET
hex
default 0xe0
endif # SOUTHBRIDGE_AMD_SB700 endif # SOUTHBRIDGE_AMD_SB700

4
src/southbridge/amd/sb800/Kconfig
View File

@ -37,8 +37,4 @@ config EHCI_BAR
hex hex
default 0xfef00000 default 0xfef00000
config EHCI_DEBUG_OFFSET
hex
default 0xe0
endif # SOUTHBRIDGE_AMD_SB800 endif # SOUTHBRIDGE_AMD_SB800

4
src/southbridge/intel/bd82x6x/Kconfig
View File

@ -41,10 +41,6 @@ config EHCI_BAR
hex hex
default 0xfef00000 default 0xfef00000
config EHCI_DEBUG_OFFSET
hex
default 0xa0
config DRAM_RESET_GATE_GPIO config DRAM_RESET_GATE_GPIO
int int
default 60 default 60

4
src/southbridge/intel/fsp_bd82x6x/Kconfig
View File

@ -37,10 +37,6 @@ config EHCI_BAR
hex hex
default 0xfef00000 default 0xfef00000
config EHCI_DEBUG_OFFSET
hex
default 0xa0
config BOOTBLOCK_SOUTHBRIDGE_INIT config BOOTBLOCK_SOUTHBRIDGE_INIT
string string
default "southbridge/intel/fsp_bd82x6x/bootblock.c" default "southbridge/intel/fsp_bd82x6x/bootblock.c"

4
src/southbridge/intel/i82801dx/Kconfig
View File

@ -33,8 +33,4 @@ config EHCI_BAR
hex hex
default 0xfef00000 default 0xfef00000
config EHCI_DEBUG_OFFSET
hex
default 0x80
endif endif

4
src/southbridge/intel/i82801ex/Kconfig
View File

@ -11,8 +11,4 @@ config EHCI_BAR
hex hex
default 0xfef00000 default 0xfef00000
config EHCI_DEBUG_OFFSET
hex
default 0xa0
endif endif

4
src/southbridge/intel/i82801gx/Kconfig
View File

@ -32,10 +32,6 @@ config EHCI_BAR
hex hex
default 0xfef00000 default 0xfef00000
config EHCI_DEBUG_OFFSET
hex
default 0xa0
config BOOTBLOCK_SOUTHBRIDGE_INIT config BOOTBLOCK_SOUTHBRIDGE_INIT
string string
default "southbridge/intel/i82801gx/bootblock.c" default "southbridge/intel/i82801gx/bootblock.c"

4
src/southbridge/intel/i82801ix/Kconfig
View File

@ -33,10 +33,6 @@ config EHCI_BAR
hex hex
default 0xfef00000 default 0xfef00000
config EHCI_DEBUG_OFFSET
hex
default 0xa0
config BOOTBLOCK_SOUTHBRIDGE_INIT config BOOTBLOCK_SOUTHBRIDGE_INIT
string string
default "southbridge/intel/i82801ix/bootblock.c" default "southbridge/intel/i82801ix/bootblock.c"

4
src/southbridge/intel/ibexpeak/Kconfig
View File

@ -39,10 +39,6 @@ config EHCI_BAR
hex hex
default 0xfef00000 default 0xfef00000
config EHCI_DEBUG_OFFSET
hex
default 0xa0
config DRAM_RESET_GATE_GPIO config DRAM_RESET_GATE_GPIO
int int
default 60 default 60

4
src/southbridge/intel/lynxpoint/Kconfig
View File

@ -44,10 +44,6 @@ config EHCI_BAR
hex hex
default 0xe8000000 default 0xe8000000
config EHCI_DEBUG_OFFSET
hex
default 0xa0
config BOOTBLOCK_SOUTHBRIDGE_INIT config BOOTBLOCK_SOUTHBRIDGE_INIT
string string
default "southbridge/intel/lynxpoint/bootblock.c" default "southbridge/intel/lynxpoint/bootblock.c"

4
src/southbridge/intel/sch/Kconfig
View File

@ -30,10 +30,6 @@ config EHCI_BAR
hex hex
default 0xfef00000 default 0xfef00000
config EHCI_DEBUG_OFFSET
hex
default 0xa0
config HAVE_CMC config HAVE_CMC
bool "Add a CMC state machine binary" bool "Add a CMC state machine binary"
help help

4
src/southbridge/nvidia/ck804/Kconfig
View File

@ -14,10 +14,6 @@ config EHCI_BAR
hex hex
default 0xfef00000 default 0xfef00000
config EHCI_DEBUG_OFFSET
hex
default 0x98
config CK804_USE_NIC config CK804_USE_NIC
bool bool
default n default n

4
src/southbridge/nvidia/mcp55/Kconfig
View File

@ -14,10 +14,6 @@ config EHCI_BAR
hex hex
default 0xfef00000 default 0xfef00000
config EHCI_DEBUG_OFFSET
hex
default 0x98
config MCP55_USE_NIC config MCP55_USE_NIC
bool bool
default n default n

3
src/southbridge/sis/sis966/Kconfig
View File

@ -12,6 +12,3 @@ config EHCI_BAR
hex hex
default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966 default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966
config EHCI_DEBUG_OFFSET
hex
default 0x98 if SOUTHBRIDGE_SIS_SIS966