soc/intel/ehl: Replace dt HeciEnabled by HECI1 disable config

The only option to make HECI1 function disable on Elkhart Lake SoC
platform is using SBI under SMM mode.

List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.

Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I76c625e6221fdef1343599e7dbc7739caa91bf98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>

src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb

@@ -12,9 +12,6 @@ chip soc/intel/elkhartlake
 	register "pmc_gpe0_dw1" = "GPP_F"
 	register "pmc_gpe0_dw2" = "GPP_E"
 
-	# Enable heci1 communication
-	register "HeciEnabled" = "1"
-
 	# FSP configuration
 	register "SaGv" = "SaGv_Enabled"
 	register "SmbusEnable" = "1"

src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb

@@ -12,9 +12,6 @@ chip soc/intel/elkhartlake
 	register "pmc_gpe0_dw1" = "GPP_F"
 	register "pmc_gpe0_dw2" = "GPP_E"
 
-	# Enable heci1 communication
-	register "HeciEnabled" = "1"
-
 	# FSP configuration
 	register "SaGv" = "SaGv_Disabled"
 	register "SmbusEnable" = "1"

src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb

@@ -12,9 +12,6 @@ chip soc/intel/elkhartlake
 	register "pmc_gpe0_dw1" = "GPP_F"
 	register "pmc_gpe0_dw2" = "GPP_E"
 
-	# Enable heci1 communication
-	register "HeciEnabled" = "1"
-
 	# FSP configuration
 	register "SaGv" = "SaGv_Disabled"
 	register "SmbusEnable" = "1"

src/soc/intel/elkhartlake/chip.h

@@ -226,10 +226,6 @@ struct soc_intel_elkhartlake_config {
 
 	uint8_t Device4Enable;
 
-	/* HeciEnabled decides the state of Heci1 at end of boot
-	 * Setting to 0 (default) disables Heci1 and hides the device from OS */
-	uint8_t HeciEnabled;
-
 	/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
 	uint8_t eist_enable;
 

src/soc/intel/elkhartlake/smihandler.c

@@ -16,11 +16,7 @@
  */
 void smihandler_soc_at_finalize(void)
 {
-	const struct soc_intel_elkhartlake_config *config;
+	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
-
-	config = config_of_soc();
-
-	if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM))
 		heci_disable();
 }