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soc/intel/tigerlake: Allow fine grained control of S0iX states

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Expose devicetree parameter to enable/disable each individual substate.

See https://review.coreboot.org/c/coreboot/+/43741 for context.

TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x
BUG=b:154333137

Change-Id: I8a0cf820e20961486813067c6945fe07bc4899f7
Signed-off-by: jbk@chromium.org
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44355
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jes Klinke
2020-08-10 13:30:40 -07:00
committed by Patrick Georgi
parent 1df3b70c6a
commit 6fd87ffe2e
2 changed files with 25 additions and 0 deletions
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8
src/soc/intel/tigerlake/fsp_params.c
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@@ -204,6 +204,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(params->SataPortsDevSlp));
}
/* S0iX: Selectively enable individual sub-states,
* by default all are enabled.
*
* LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0,
* LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4
*/
params->LpmStateEnableMask = LPM_S0iX_ALL & ~config->LpmStateDisableMask;
/*
* Power Optimizer for DMI and SATA.
* DmiPwrOptimizeDisable and SataPwrOptimizeDisable is default to 0.