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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Greg Watson
19
src/cpu/ppc/ppc7xx/Config.lb
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19
src/cpu/ppc/ppc7xx/Config.lb
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##
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## CPU initialization
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##
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uses _RAMBASE
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uses USE_DCACHE_RAM
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uses DCACHE_RAM_BASE
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uses DCACHE_RAM_SIZE
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##
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## PPC7XX always uses cache ram for initial setup
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##
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default USE_DCACHE_RAM=1
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## Set dcache ram above linuxbios image
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default DCACHE_RAM_BASE=_RAMBASE+0x100000
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## Dcache size is 16Kb
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default DCACHE_RAM_SIZE=16384
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initinclude "FAMILY_INIT" cpu/ppc/ppc7xx/ppc7xx.inc
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179
src/cpu/ppc/ppc7xx/ppc7xx.inc
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179
src/cpu/ppc/ppc7xx/ppc7xx.inc
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/* Copyright 2000 AG Electronics Ltd. */
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/* This code is distributed without warranty under the GPL v2 (see COPYING) */
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/*
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* The aim of this code is to bring the machine from power-on to the point
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* where we can jump to the the main LinuxBIOS entry point hardwaremain()
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* which is written in C.
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*
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* At power-on, we have no RAM, a memory-mapped I/O space, and we are executing
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* out of ROM, generally at 0xfff00100.
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*
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* Before we jump to harwaremain() we want to do the following:
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*
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* - enable L1 I/D caches, otherwise performance will be slow
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* - set up DBATs for the following regions:
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* - RAM (generally 0x00000000 -> 0x7fffffff)
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* - ROM (_ROMBASE -> _ROMBASE + ROM_SIZE)
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* - I/O (generally 0xfc000000 -> 0xfdffffff)
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* - the main purpose for setting up the DBATs is so the I/O region
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* can be marked cache inhibited/write through
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* - set up IBATs for RAM and ROM
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*
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*/
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#define BSP_IOREGION1 0x80000000
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#define BSP_IOMASK1 BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
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#define BSP_IOREGION2 0xFD000000
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#define BSP_IOMASK2 BAT_BL_64M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
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isync
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/*
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* Disable dcache and MMU, so we're in a known state
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*/
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li r0, 0
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sync
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mtspr HID0, r0
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sync
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mtmsr r0
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isync
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/*
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* Invalidate D & I BATS
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*/
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mtibatu 0, r0
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mtibatu 1, r0
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mtibatu 2, r0
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mtibatu 3, r0
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isync
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mtdbatu 0, r0
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mtdbatu 1, r0
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mtdbatu 2, r0
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mtdbatu 3, r0
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isync
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/*
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* Clear segment registers (LinuxBIOS doesn't use these)
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*/
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mtsr 0, r0
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isync
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mtsr 1, r0
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isync
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mtsr 2, r0
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isync
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mtsr 3, r0
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isync
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mtsr 4, r0
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isync
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mtsr 5, r0
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isync
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mtsr 6, r0
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isync
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mtsr 7, r0
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isync
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mtsr 8, r0
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isync
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mtsr 9, r0
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isync
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mtsr 10, r0
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isync
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mtsr 11, r0
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isync
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mtsr 12, r0
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isync
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mtsr 13, r0
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isync
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mtsr 14, r0
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isync
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mtsr 15, r0
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isync
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/*
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* Set up DBATs
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*
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* DBAT0 covers RAM (0 -> 0x0FFFFFFF) (256Mb)
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* DBAT1 covers PCI memory and ROM (0xFD000000 -> 0xFFFFFFFF) (64Mb)
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* DBAT2 covers PCI memory (0x80000000 -> 0x8FFFFFFF) (256Mb)
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* DBAT3 is not used
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*/
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lis r2, 0@h
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ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
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ori r2, r2, BAT_READ_WRITE | BAT_GUARDED
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mtdbatu 0, r3
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mtdbatl 0, r2
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isync
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lis r2, BSP_IOREGION2@h
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ori r3, r2, BAT_BL_64M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
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ori r2, r2, BAT_CACHE_INHIBITED | BAT_GUARDED | BAT_READ_WRITE
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mtdbatu 1, r3
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mtdbatl 1, r2
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isync
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lis r2, BSP_IOREGION1@h
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ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
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ori r2, r2, BAT_CACHE_INHIBITED | BAT_GUARDED | BAT_READ_WRITE
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mtdbatu 2, r3
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mtdbatl 2, r2
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isync
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/*
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* IBATS
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*
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* IBAT0 covers RAM (0 -> 256Mb)
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* IBAT1 covers ROM (_ROMBASE -> _ROMBASE+ROM_SIZE)
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*/
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lis r2, 0@h
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ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
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ori r2, r2, BAT_READ_WRITE
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mtibatu 0, r3
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mtibatl 0, r2
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isync
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lis r2, _ROMBASE@h
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#if ROM_SIZE > 1048576
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ori r3, r2, BAT_BL_16M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
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#else
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ori r3, r2, BAT_BL_1M | BAT_VALID_SUPERVISOR | BAT_VALID_USER
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#endif
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ori r2, r2, BAT_READ_ONLY
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mtibatu 1, r3
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mtibatl 1, r2
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isync
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/*
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* Enable MMU
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*/
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mfmsr r2
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ori r2, r2, MSR_DR | MSR_IR
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mtmsr r2
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isync
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sync
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/*
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* Enable and invalidate the L1 icache
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*/
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mfspr r2, HID0
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ori r2, r2, HID0_ICE | HID0_ICFI
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isync
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mtspr HID0, r2
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/*
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* Enable and invalidate the L1 dcache
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*/
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mfspr r2, HID0
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ori r2, r2, HID0_DCE | HID0_DCFI
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sync
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mtspr HID0, r2
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/*
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* Initialize data cache blocks
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* (assumes cache block size of 32 bytes)
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*/
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lis r1, DCACHE_RAM_BASE@h
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ori r1, r1, DCACHE_RAM_BASE@l
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li r3, (DCACHE_RAM_SIZE / 32)
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mtctr r3
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0: dcbz r0, r1
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addi r1, r1, 32
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bdnz 0b
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