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vendorcode/amd/agesa/family16: Drop unused platform

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This platform use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.

Change-Id: Ie2ef5424c3ebe75ff98361639a0f9980101c1141
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69126
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Arthur Heymans
2022-11-02 00:13:06 +01:00
parent 49af4f7f91
commit 7036ded25d
729 changed files with 0 additions and 229109 deletions
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1
src/vendorcode/amd/agesa/Makefile.inc
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@ -1,4 +1,3 @@
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += f16kb
ifeq ($(CONFIG_CPU_AMD_AGESA),y)

3924
src/vendorcode/amd/agesa/f16kb/AGESA.h
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File diff suppressed because it is too large Load Diff

478
src/vendorcode/amd/agesa/f16kb/AMD.h
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@ -1,478 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Agesa structures and definitions
*
* Contains AMD AGESA core interface
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Include
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _AMD_H_
#define _AMD_H_
#define AGESA_REVISION "Arch2008"
#define AGESA_ID "AGESA"
#define Int16FromChar(a,b) ((a) << 0 | (b) << 8)
#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
// AGESA Types and Definitions
//
//
#define LAST_ENTRY 0xFFFFFFFFul
#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
#define IOCF8 0xCF8
#define IOCFC 0xCFC
/// The return status for all AGESA public services.
///
/// Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
/// will have log entries with more detail.
///
typedef enum {
AGESA_SUCCESS = 0, ///< The service completed normally. Info may be logged.
AGESA_UNSUPPORTED, ///< The dispatcher or create struct had an unimplemented function requested.
///< Not logged.
AGESA_BOUNDS_CHK, ///< A dynamic parameter was out of range and the service was not provided.
///< Example, memory address not installed, heap buffer handle not found.
///< Not Logged.
// AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
AGESA_ALERT, ///< An observed condition, but no loss of function.
///< See log. Example, HT CRC.
AGESA_WARNING, ///< Possible or minor loss of function. See Log.
AGESA_ERROR, ///< Significant loss of function, boot may be possible. See Log.
AGESA_CRITICAL, ///< Continue boot only to notify user. See Log.
AGESA_FATAL, ///< Halt booting. See Log, however Fatal errors pertaining to heap problems
///< may not be able to reliably produce log events.
AgesaStatusMax ///< Not a status, for limit checking.
} AGESA_STATUS;
/// For checking whether a status is at or above the mandatory log level.
#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
/**
* Callout method to the host environment.
*
* Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
*
* @param[in] Function The specific callout function being invoked.
* @param[in] FcnData Function specific data item.
* @param[in,out] ConfigPtr Reference to Callout params.
*/
typedef AGESA_STATUS (*CALLOUT_ENTRY) (
IN UINT32 Function,
IN UINTN FcnData,
IN OUT VOID *ConfigPtr
);
typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
///This allocation type is used by the AmdCreateStruct entry point
typedef enum {
PreMemHeap = 0, ///< Create heap in cache.
PostMemDram, ///< Create heap in memory.
ByHost ///< Create heap by Host.
} ALLOCATION_METHOD;
/// These width descriptors are used by the library function, and others, to specify the data size
typedef enum ACCESS_WIDTH {
AccessWidth8 = 1, ///< Access width is 8 bits.
AccessWidth16, ///< Access width is 16 bits.
AccessWidth32, ///< Access width is 32 bits.
AccessWidth64, ///< Access width is 64 bits.
AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.
AccessS3SaveWidth16, ///< Save 16 bits data.
AccessS3SaveWidth32, ///< Save 32 bits data.
AccessS3SaveWidth64, ///< Save 64 bits data.
} ACCESS_WIDTH;
/// AGESA struct name
typedef enum {
// AGESA BASIC FUNCTIONS
AMD_INIT_RECOVERY = 0x00020000, ///< AmdInitRecovery entry point handle
AMD_CREATE_STRUCT, ///< AmdCreateStruct handle
AMD_INIT_EARLY, ///< AmdInitEarly entry point handle
AMD_INIT_ENV, ///< AmdInitEnv entry point handle
AMD_INIT_LATE, ///< AmdInitLate entry point handle
AMD_INIT_MID, ///< AmdInitMid entry point handle
AMD_INIT_POST, ///< AmdInitPost entry point handle
AMD_INIT_RESET, ///< AmdInitReset entry point handle
AMD_INIT_RESUME, ///< AmdInitResume entry point handle
AMD_RELEASE_STRUCT, ///< AmdReleaseStruct handle
AMD_S3LATE_RESTORE, ///< AmdS3LateRestore entry point handle
AMD_S3_SAVE, ///< AmdS3Save entry point handle
AMD_GET_APIC_ID, ///< AmdGetApicId entry point handle
AMD_GET_PCI_ADDRESS, ///< AmdGetPciAddress entry point handle
AMD_IDENTIFY_CORE, ///< AmdIdentifyCore general service handle
AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle
AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle
AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle
AMD_IDENTIFY_DIMMS, ///< AmdIdentifyDimm general service handle
AMD_GET_2D_DATA_EYE, ///< AmdGet2DDataEye general service handle
AMD_S3FINAL_RESTORE, ///< AmdS3FinalRestore entry point handle
AMD_INIT_RTB ///< AmdInitRtb entry point handle
} AGESA_STRUCT_NAME;
/* ResetType constant values */
#define WARM_RESET_WHENEVER 1
#define COLD_RESET_WHENEVER 2
#define WARM_RESET_IMMEDIATELY 3
#define COLD_RESET_IMMEDIATELY 4
// AGESA Structures
/// The standard header for all AGESA services.
/// For internal AGESA naming conventions, see @ref amdconfigparamname .
typedef struct {
IN UINT32 ImageBasePtr; ///< The AGESA Image base address.
IN UINT32 Func; ///< The service desired
IN UINT32 AltImageBasePtr; ///< Alternate Image location
IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
IN UINT8 HeapStatus; ///< For heap status from boot time slide.
IN UINT64 HeapBasePtr; ///< Location of the heap
IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use.
} AMD_CONFIG_PARAMS;
/// Create Struct Interface.
typedef struct {
IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
IN AGESA_STRUCT_NAME AgesaFunctionName; ///< The service to init
IN ALLOCATION_METHOD AllocationMethod; ///< How to handle buffer allocation
IN OUT UINT32 NewStructSize; ///< The size of the allocated data, in for ByHost, else out only.
IN OUT VOID *NewStructPtr; ///< The struct for the service.
///< The struct to init for ByHost allocation,
///< the initialized struct on return.
} AMD_INTERFACE_PARAMS;
#define FUNC_0 0 // bit-placed for PCI address creation
#define FUNC_1 1
#define FUNC_2 2
#define FUNC_3 3
#define FUNC_4 4
#define FUNC_5 5
#define FUNC_6 6
#define FUNC_7 7
/// AGESA Binary module header structure
typedef struct {
IN UINT32 Signature; ///< Binary Signature
IN CHAR8 CreatorID[8]; ///< 8 characters ID
IN CHAR8 Version[12]; ///< 12 characters version
IN UINT32 ModuleInfoOffset; ///< Offset of module
IN UINT32 EntryPointAddress; ///< Entry address
IN UINT32 ImageBase; ///< Image base
IN UINT32 RelocTableOffset; ///< Relocate Table offset
IN UINT32 ImageSize; ///< Size
IN UINT16 Checksum; ///< Checksum
IN UINT8 ImageType; ///< Type
IN UINT8 V_Reserved; ///< Reserved
} AMD_IMAGE_HEADER;
/// AGESA Binary module header structure
typedef struct _AMD_MODULE_HEADER {
IN UINT32 ModuleHeaderSignature; ///< Module signature
IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID
IN CHAR8 ModuleVersion[12]; ///< 12 characters version
IN VOID *ModuleDispatcher; ///< A pointer point to dispatcher
IN struct _AMD_MODULE_HEADER *NextBlock; ///< Next module header link
} AMD_MODULE_HEADER;
// AMD_CODE_HEADER Signatures.
#define AGESA_CODE_SIGNATURE {'!', '!', '!', 'A', 'G', 'E', 'S', 'A'}
/// AGESA_CODE_SIGNATURE
typedef struct {
IN CHAR8 Signature[8]; ///< code header Signature
IN CHAR8 ComponentName[16]; ///< 16 character name of the code module
IN CHAR8 Version[12]; ///< 12 character version string
IN CHAR8 TerminatorNull; ///< null terminated string
IN CHAR8 VerReserved[7]; ///< reserved space
} AMD_CODE_HEADER;
/// Extended PCI address format
typedef struct {
IN OUT UINT32 Register:12; ///< Register offset
IN OUT UINT32 Function:3; ///< Function number
IN OUT UINT32 Device:5; ///< Device number
IN OUT UINT32 Bus:8; ///< Bus number
IN OUT UINT32 Segment:4; ///< Segment
} EXT_PCI_ADDR;
/// Union type for PCI address
typedef union _PCI_ADDR {
IN UINT32 AddressValue; ///< Formal address
IN EXT_PCI_ADDR Address; ///< Extended address
} PCI_ADDR;
// SBDFO - Segment Bus Device Function Offset
// 31:28 Segment (4-bits)
// 27:20 Bus (8-bits)
// 19:15 Device (5-bits)
// 14:12 Function(3-bits)
// 11:00 Offset (12-bits)
#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
(((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
#define ILLEGAL_SBDFO 0xFFFFFFFFul
/// CPUID data received registers format
typedef struct {
OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX
OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX
OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX
OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX
} CPUID_DATA;
/// HT frequency for external callbacks
typedef enum {
HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks
HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks
HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks
HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks
HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks
HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks
HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks
HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks
HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks
HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks
HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks
HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks
HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks
HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks
HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks
HT_FREQUENCY_3200M = 19, ///< HT speed 3200 for external callbacks
HT_FREQUENCY_MAX ///< Limit check.
} HT_FREQUENCIES;
// The minimum HT3 frequency
#define HT3_FREQUENCY_MIN HT_FREQUENCY_1200M
#ifndef BIT0
#define BIT0 0x0000000000000001ull
#endif
#ifndef BIT1
#define BIT1 0x0000000000000002ull
#endif
#ifndef BIT2
#define BIT2 0x0000000000000004ull
#endif
#ifndef BIT3
#define BIT3 0x0000000000000008ull
#endif
#ifndef BIT4
#define BIT4 0x0000000000000010ull
#endif
#ifndef BIT5
#define BIT5 0x0000000000000020ull
#endif
#ifndef BIT6
#define BIT6 0x0000000000000040ull
#endif
#ifndef BIT7
#define BIT7 0x0000000000000080ull
#endif
#ifndef BIT8
#define BIT8 0x0000000000000100ull
#endif
#ifndef BIT9
#define BIT9 0x0000000000000200ull
#endif
#ifndef BIT10
#define BIT10 0x0000000000000400ull
#endif
#ifndef BIT11
#define BIT11 0x0000000000000800ull
#endif
#ifndef BIT12
#define BIT12 0x0000000000001000ull
#endif
#ifndef BIT13
#define BIT13 0x0000000000002000ull
#endif
#ifndef BIT14
#define BIT14 0x0000000000004000ull
#endif
#ifndef BIT15
#define BIT15 0x0000000000008000ull
#endif
#ifndef BIT16
#define BIT16 0x0000000000010000ull
#endif
#ifndef BIT17
#define BIT17 0x0000000000020000ull
#endif
#ifndef BIT18
#define BIT18 0x0000000000040000ull
#endif
#ifndef BIT19
#define BIT19 0x0000000000080000ull
#endif
#ifndef BIT20
#define BIT20 0x0000000000100000ull
#endif
#ifndef BIT21
#define BIT21 0x0000000000200000ull
#endif
#ifndef BIT22
#define BIT22 0x0000000000400000ull
#endif
#ifndef BIT23
#define BIT23 0x0000000000800000ull
#endif
#ifndef BIT24
#define BIT24 0x0000000001000000ull
#endif
#ifndef BIT25
#define BIT25 0x0000000002000000ull
#endif
#ifndef BIT26
#define BIT26 0x0000000004000000ull
#endif
#ifndef BIT27
#define BIT27 0x0000000008000000ull
#endif
#ifndef BIT28
#define BIT28 0x0000000010000000ull
#endif
#ifndef BIT29
#define BIT29 0x0000000020000000ull
#endif
#ifndef BIT30
#define BIT30 0x0000000040000000ull
#endif
#ifndef BIT31
#define BIT31 0x0000000080000000ull
#endif
#ifndef BIT32
#define BIT32 0x0000000100000000ull
#endif
#ifndef BIT33
#define BIT33 0x0000000200000000ull
#endif
#ifndef BIT34
#define BIT34 0x0000000400000000ull
#endif
#ifndef BIT35
#define BIT35 0x0000000800000000ull
#endif
#ifndef BIT36
#define BIT36 0x0000001000000000ull
#endif
#ifndef BIT37
#define BIT37 0x0000002000000000ull
#endif
#ifndef BIT38
#define BIT38 0x0000004000000000ull
#endif
#ifndef BIT39
#define BIT39 0x0000008000000000ull
#endif
#ifndef BIT40
#define BIT40 0x0000010000000000ull
#endif
#ifndef BIT41
#define BIT41 0x0000020000000000ull
#endif
#ifndef BIT42
#define BIT42 0x0000040000000000ull
#endif
#ifndef BIT43
#define BIT43 0x0000080000000000ull
#endif
#ifndef BIT44
#define BIT44 0x0000100000000000ull
#endif
#ifndef BIT45
#define BIT45 0x0000200000000000ull
#endif
#ifndef BIT46
#define BIT46 0x0000400000000000ull
#endif
#ifndef BIT47
#define BIT47 0x0000800000000000ull
#endif
#ifndef BIT48
#define BIT48 0x0001000000000000ull
#endif
#ifndef BIT49
#define BIT49 0x0002000000000000ull
#endif
#ifndef BIT50
#define BIT50 0x0004000000000000ull
#endif
#ifndef BIT51
#define BIT51 0x0008000000000000ull
#endif
#ifndef BIT52
#define BIT52 0x0010000000000000ull
#endif
#ifndef BIT53
#define BIT53 0x0020000000000000ull
#endif
#ifndef BIT54
#define BIT54 0x0040000000000000ull
#endif
#ifndef BIT55
#define BIT55 0x0080000000000000ull
#endif
#ifndef BIT56
#define BIT56 0x0100000000000000ull
#endif
#ifndef BIT57
#define BIT57 0x0200000000000000ull
#endif
#ifndef BIT58
#define BIT58 0x0400000000000000ull
#endif
#ifndef BIT59
#define BIT59 0x0800000000000000ull
#endif
#ifndef BIT60
#define BIT60 0x1000000000000000ull
#endif
#ifndef BIT61
#define BIT61 0x2000000000000000ull
#endif
#ifndef BIT62
#define BIT62 0x4000000000000000ull
#endif
#ifndef BIT63
#define BIT63 0x8000000000000000ull
#endif
#endif // _AMD_H_

84
src/vendorcode/amd/agesa/f16kb/Config/OptionApmInstall.h
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@ -1,84 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Application Power Management (APM).
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_APM_INSTALL_H_
#define _OPTION_APM_INSTALL_H_
#include "cpuApm.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPU_APM_FEAT
#define F16_APM_SUPPORT
#if OPTION_CPU_APM == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
// Family 16H
#ifdef OPTION_FAMILY16H
#if OPTION_FAMILY16H == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureApm;
#undef OPTION_CPU_APM_FEAT
#define OPTION_CPU_APM_FEAT &CpuFeatureApm,
extern CONST APM_FAMILY_SERVICES ROMDATA F16ApmSupport;
#undef F16_APM_SUPPORT
#define F16_APM_SUPPORT {AMD_FAMILY_16, &F16ApmSupport},
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA ApmFamilyServiceArray[] =
{
F16_APM_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA ApmFamilyServiceTable =
{
(sizeof (ApmFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&ApmFamilyServiceArray[0]
};
#endif // _OPTION_APM_INSTALL_H_

101
src/vendorcode/amd/agesa/f16kb/Config/OptionC6Install.h
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@ -1,101 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: C6 C-state
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_C6_STATE_INSTALL_H_
#define _OPTION_C6_STATE_INSTALL_H_
#include "cpuC6State.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_C6_STATE_FEAT
#define F15_TN_C6_STATE_SUPPORT
#define F16_KB_C6_STATE_SUPPORT
#if OPTION_C6_STATE == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if (OPTION_FAMILY15H_TN == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
#undef OPTION_C6_STATE_FEAT
#define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
extern CONST C6_FAMILY_SERVICES ROMDATA F15TnC6Support;
#undef F15_TN_C6_STATE_SUPPORT
#define F15_TN_C6_STATE_SUPPORT {AMD_FAMILY_15_TN, &F15TnC6Support},
#endif
#endif
#endif
#ifdef OPTION_FAMILY16H
#if OPTION_FAMILY16H == TRUE
#if OPTION_FAMILY16H_KB == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
#undef OPTION_C6_STATE_FEAT
#define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
extern CONST C6_FAMILY_SERVICES ROMDATA F16KbC6Support;
#undef F16_KB_C6_STATE_SUPPORT
#define F16_KB_C6_STATE_SUPPORT {AMD_FAMILY_16_KB, &F16KbC6Support},
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA C6FamilyServiceArray[] =
{
F15_TN_C6_STATE_SUPPORT
F16_KB_C6_STATE_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA C6FamilyServiceTable =
{
(sizeof (C6FamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&C6FamilyServiceArray[0]
};
#endif // _OPTION_C6_STATE_INSTALL_H_

74
src/vendorcode/amd/agesa/f16kb/Config/OptionCditInstall.h
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@ -1,74 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: CDIT
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_CDIT_INSTALL_H_
#define _OPTION_CDIT_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
OPTION_CDIT_FEATURE GetAcpiCditStub;
#define USER_CDIT_OPTION &GetAcpiCditStub
#if AGESA_ENTRY_INIT_LATE == TRUE
#ifndef OPTION_CDIT
#error BLDOPT: Option not defined: "OPTION_CDIT"
#endif
#if OPTION_CDIT == TRUE
OPTION_CDIT_FEATURE GetAcpiCditMain;
#undef USER_CDIT_OPTION
#define USER_CDIT_OPTION &GetAcpiCditMain
#endif
#endif
/* Declare the instance of the CDIT option configuration structure */
CONST OPTION_CDIT_CONFIGURATION ROMDATA OptionCditConfiguration = {
CDIT_STRUCT_VERSION,
USER_CDIT_OPTION,
{CFG_ACPI_SET_OEM_ID},
{CFG_ACPI_SET_OEM_TABLE_ID}
};
#endif // _OPTION_CDIT_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Core Performance Boost
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_CPB_INSTALL_H_
#define _OPTION_CPB_INSTALL_H_
#include "cpuCpb.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPB_FEAT
#define F15_TN_CPB_SUPPORT
#define F16_KB_CPB_SUPPORT
#if OPTION_CPB == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
// Family 15h
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if (OPTION_FAMILY15H_TN == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
#undef OPTION_CPB_FEAT
#define OPTION_CPB_FEAT &CpuFeatureCpb,
extern CONST CPB_FAMILY_SERVICES ROMDATA F15TnCpbSupport;
#undef F15_TN_CPB_SUPPORT
#define F15_TN_CPB_SUPPORT {AMD_FAMILY_15_TN, &F15TnCpbSupport},
#endif
#endif
#endif
// Family 16h
#ifdef OPTION_FAMILY16H
#if OPTION_FAMILY16H == TRUE
#if OPTION_FAMILY16H_KB == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
#undef OPTION_CPB_FEAT
#define OPTION_CPB_FEAT &CpuFeatureCpb,
extern CONST CPB_FAMILY_SERVICES ROMDATA F16KbCpbSupport;
#undef F16_KB_CPB_SUPPORT
#define F16_KB_CPB_SUPPORT {AMD_FAMILY_16_KB, &F16KbCpbSupport},
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpbFamilyServiceArray[] =
{
F15_TN_CPB_SUPPORT
F16_KB_CPB_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpbFamilyServiceTable =
{
(sizeof (CpbFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&CpbFamilyServiceArray[0]
};
#endif // _OPTION_CPB_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: CPU Cache Flush On Halt
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
#define _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
#include "cpuPostInit.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
#define F15_TN_CPU_CFOH_SUPPORT
#define F16_KB_CPU_CFOH_SUPPORT
#if OPTION_CPU_CFOH == TRUE
#if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
#undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
#if OPTION_FAMILY15H_TN == TRUE
extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15TnCacheFlushOnHalt;
#undef F15_TN_CPU_CFOH_SUPPORT
#define F15_TN_CPU_CFOH_SUPPORT {AMD_FAMILY_15_TN, &F15TnCacheFlushOnHalt},
#endif
#endif
#endif
#ifdef OPTION_FAMILY16H
#if OPTION_FAMILY16H == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
#undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
#if OPTION_FAMILY16H_KB == TRUE
extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F16KbCacheFlushOnHalt;
#undef F16_KB_CPU_CFOH_SUPPORT
#define F16_KB_CPU_CFOH_SUPPORT {AMD_FAMILY_16_KB, &F16KbCacheFlushOnHalt},
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CacheFlushOnHaltFamilyServiceArray[] =
{
F16_KB_CPU_CFOH_SUPPORT
F15_TN_CPU_CFOH_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CacheFlushOnHaltFamilyServiceTable =
{
(sizeof (CacheFlushOnHaltFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&CacheFlushOnHaltFamilyServiceArray[0]
};
#endif // _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: CPU Core Leveling
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_CPU_CORELEVELING_INSTALL_H_
#define _OPTION_CPU_CORELEVELING_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPU_CORE_LEVELING_FEAT
#define F15_TN_CPU_CORELEVELING_SUPPORT
#define F16_KB_CPU_CORELEVELING_SUPPORT
#if OPTION_CPU_CORELEVELING == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE)
// Family 15h
#if OPTION_FAMILY15H == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
#undef OPTION_CPU_CORE_LEVELING_FEAT
#define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
#if (OPTION_FAMILY15H_TN == TRUE)
extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15TnCoreLeveling;
#undef F15_TN_CPU_CORELEVELING_SUPPORT
#define F15_TN_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15_TN, &F15TnCoreLeveling},
#endif
#endif
// Family 16h
#if OPTION_FAMILY16H == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
#undef OPTION_CPU_CORE_LEVELING_FEAT
#define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
#if (OPTION_FAMILY16H_KB == TRUE)
extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F16KbCoreLeveling;
#undef F16_KB_CPU_CORELEVELING_SUPPORT
#define F16_KB_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_16_KB, &F16KbCoreLeveling},
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CoreLevelingFamilyServiceArray[] =
{
F16_KB_CPU_CORELEVELING_SUPPORT
F15_TN_CPU_CORELEVELING_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CoreLevelingFamilyServiceTable =
{
(sizeof (CoreLevelingFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&CoreLevelingFamilyServiceArray[0]
};
#endif // _OPTION_CPU_CORELEVELING_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of all appropriate CPU family specific support.
*
* This file generates the defaults tables for all family specific
* combinations.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
/* Default all CPU Specific Service members to off. They
will be enabled as needed by cross referencing families
with entry points in the family / model install files. */
#define USES_REGISTER_TABLES FALSE
#define BASE_FAMILY_PCI FALSE
#define MODEL_SPECIFIC_PCI FALSE
#define BASE_FAMILY_MSR FALSE
#define MODEL_SPECIFIC_MSR FALSE
#define BASE_FAMILY_HT_PCI FALSE
#define MODEL_SPECIFIC_HT_PCI FALSE
#define BASE_FAMILY_WORKAROUNDS FALSE
/*
* Pull in family specific services based on entry point
*/
#if AGESA_ENTRY_INIT_RESET == TRUE
#endif
#if AGESA_ENTRY_INIT_EARLY == TRUE
#undef USES_REGISTER_TABLES
#define USES_REGISTER_TABLES TRUE
#undef BASE_FAMILY_PCI
#define BASE_FAMILY_PCI TRUE
#undef MODEL_SPECIFIC_PCI
#define MODEL_SPECIFIC_PCI TRUE
#undef BASE_FAMILY_MSR
#define BASE_FAMILY_MSR TRUE
#undef MODEL_SPECIFIC_MSR
#define MODEL_SPECIFIC_MSR TRUE
#undef BASE_FAMILY_HT_PCI
#define BASE_FAMILY_HT_PCI TRUE
#undef MODEL_SPECIFIC_HT_PCI
#define MODEL_SPECIFIC_HT_PCI TRUE
#undef BASE_FAMILY_WORKAROUNDS
#define BASE_FAMILY_WORKAROUNDS TRUE
#endif
#if AGESA_ENTRY_INIT_POST == TRUE
#endif
#if AGESA_ENTRY_INIT_ENV == TRUE
#endif
#if AGESA_ENTRY_INIT_MID == TRUE
#endif
#if AGESA_ENTRY_INIT_LATE == TRUE
#endif
#if AGESA_ENTRY_INIT_S3SAVE == TRUE
#endif
#if AGESA_ENTRY_INIT_RESUME == TRUE
#endif
#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
#endif
#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
#endif
/*
* Initialize PCI MMIO mask to 0
*/
#define FAMILY_MMIO_BASE_MASK (0ull)
/*
* Initialize all families to disabled
*/
#define OPT_F15_TABLE
#define OPT_F16_TABLE
#define OPT_F15_ID_TABLE
#define OPT_F16_ID_TABLE
/*
* Install family specific support
*/
#if (OPTION_FAMILY15H_TN == TRUE)
#include "OptionFamily15hInstall.h"
#endif
#if (OPTION_FAMILY16H_KB == TRUE)
#include "OptionFamily16hInstall.h"
#endif
/*
* Process PCI MMIO mask
*/
// If size is 0, but base is not, break the build.
#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0)
#error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
#endif
// If base is 0, but size is not, break the build.
#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0)
#error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
#endif
#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0)
// Both are non-zero, begin further processing.
// Heap runs from 4MB to 8MB. Disallow any addresses below 8MB.
#if (CFG_PCI_MMIO_BASE < 0x800000)
#error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
#endif
// Break the build if the address is too high for the enabled families.
#if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0)
#error BLDCFG: Invalid PCI MMIO base address for the installed CPU families
#endif
// If the size parameter is not valid, break the build.
#if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16)
#if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256)
#error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
#endif
#endif
#define PCI_MMIO_ALIGNMENT ((0x100000ul * CFG_PCI_MMIO_SIZE) - 1)
// If the base is not aligned according to size, break the build.
#if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0)
#error BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size
#endif
#undef PCI_MMIO_ALIGNMENT
#endif
/*
* Process sockets / modules
*/
#ifndef ADVCFG_PLATFORM_SOCKETS
#error BLDOPT Set Family supported sockets.
#endif
#ifndef ADVCFG_PLATFORM_MODULES
#error BLDOPT Set Family supported modules.
#endif
CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration =
{
ADVCFG_PLATFORM_SOCKETS,
ADVCFG_PLATFORM_MODULES
};
/*
* Instantiate global data needed for processor identification
*/
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpuSupportedFamiliesArray[] =
{
OPT_F15_TABLE
OPT_F16_TABLE
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpuSupportedFamiliesTable =
{
(sizeof (CpuSupportedFamiliesArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&CpuSupportedFamiliesArray[0]
};
CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] =
{
OPT_F15_ID_TABLE
OPT_F16_ID_TABLE
};
CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable =
{
(sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)),
CpuSupportedFamilyIdArray
};

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/* $NoKeywords:$ */
/**
* @file
*
* Install of multiple CPU features.
*
* Aggregates enabled CPU features into a list for the dispatcher to process.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_CPU_FEATURES_INSTALL_H_
#define _OPTION_CPU_FEATURES_INSTALL_H_
#include "OptionMsgBasedC1eInstall.h"
#include "OptionL3FeaturesInstall.h"
#include "OptionCpuCoreLevelingInstall.h"
#include "OptionIoCstateInstall.h"
#include "OptionC6Install.h"
#include "OptionCpbInstall.h"
#include "OptionApmInstall.h"
#include "OptionCpuCacheFlushOnHaltInstall.h"
#include "OptionPstateHpcModeInstall.h"
#include "OptionLowPwrPstateInstall.h"
#include "OptionTdpLimitingInstall.h"
#include "OptionPsiInstall.h"
#include "OptionHtcInstall.h"
#include "OptionPrefetchModeInstall.h"
#include "OptionPreserveMailboxInstall.h"
CONST CPU_FEATURE_DESCRIPTOR* ROMDATA CONST SupportedCpuFeatureList[] =
{
OPTION_MSG_BASED_C1E_FEAT
OPTION_L3_FEAT
OPTION_CPU_CORE_LEVELING_FEAT
OPTION_IO_CSTATE_FEAT
OPTION_C6_STATE_FEAT
OPTION_CPU_APM_FEAT
OPTION_CPB_FEAT
OPTION_TDP_LIMIT_FEAT
OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
OPTION_CPU_PSTATE_HPC_MODE_FEAT // this function should be run before low power pstate for prochot
OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT // this function should be run before creating ACPI objects and after Pstate initialization
OPTION_CPU_PSI_FEAT
OPTION_CPU_HTC_FEAT
OPTION_PREFETCH_MODE_FEAT
OPTION_PRESERVE_MAILBOX_FEAT
NULL
};
#endif // _OPTION_CPU_FEATURES_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: CRAT
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_CRAT_INSTALL_H_
#define _OPTION_CRAT_INSTALL_H_
OPTION_CRAT_FEATURE GetAcpiCratStub;
#define USER_CRAT_OPTION &GetAcpiCratStub
#define F15_CRAT_SUPPORT
#define F16_CRAT_SUPPORT
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#if AGESA_ENTRY_INIT_LATE == TRUE
#ifndef OPTION_CRAT
#error BLDOPT: Option not defined: "OPTION_CRAT"
#endif
#if OPTION_CRAT == TRUE
OPTION_CRAT_FEATURE GetAcpiCratMain;
#undef USER_CRAT_OPTION
#define USER_CRAT_OPTION &GetAcpiCratMain
/*
* Family service start
*/
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if ((OPTION_FAMILY15H_TN == TRUE)
extern CONST CRAT_FAMILY_SERVICES ROMDATA F15CratSupport;
#undef F15_CRAT_SUPPORT
#define F15_CRAT_SUPPORT {AMD_FAMILY_15, &F15CratSupport},
#endif
#endif
#endif
#ifdef OPTION_FAMILY16H
#if OPTION_FAMILY16H == TRUE
extern CONST CRAT_FAMILY_SERVICES ROMDATA F16CratSupport;
#undef F16_CRAT_SUPPORT
#define F16_CRAT_SUPPORT {AMD_FAMILY_16, &F16CratSupport},
#endif
#endif
/*
* Family service end
*/
#endif
#endif
/* Declare the instance of the CRAT option configuration structure */
CONST OPTION_CRAT_CONFIGURATION ROMDATA OptionCratConfiguration = {
CRAT_STRUCT_VERSION,
USER_CRAT_OPTION,
{CFG_ACPI_SET_OEM_ID},
{CFG_ACPI_SET_OEM_TABLE_ID}
};
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CratFamilyServiceArray[] =
{
F16_CRAT_SUPPORT
F15_CRAT_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CratFamilyServiceTable =
{
(sizeof (CratFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&CratFamilyServiceArray[0]
};
/// All entries that CRAT needs
CONST S_MAKE_CRAT_ENTRY ROMDATA MakeCratEntryTable[] =
{
{MakeHSAProcUnitEntry},
{MakeMemoryEntry},
{MakeCacheEntry},
{MakeTLBEntry},
/// @todo
//MakeFPUEntry,
//MakeIOEntry,
{NULL}
};
#endif // _OPTION_CRAT_INSTALL_H_

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@ -1,123 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: DMI
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_DMI_INSTALL_H_
#define _OPTION_DMI_INSTALL_H_
#include "cpuLateInit.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
OPTION_DMI_FEATURE GetDmiInfoStub;
OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub;
#define USER_DMI_OPTION GetDmiInfoStub
#define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
#define CPU_DMI_AP_GET_TYPE4_TYPE7
#define FAM15_TN_DMI_TABLE
#define FAM16_KB_DMI_TABLE
#ifndef OPTION_DMI
#error BLDOPT: Option not defined: "OPTION_DMI"
#endif
#if OPTION_DMI == TRUE
#if AGESA_ENTRY_INIT_LATE == TRUE
OPTION_DMI_FEATURE GetDmiInfoMain;
OPTION_DMI_RELEASE_BUFFER ReleaseDmiBuffer;
#undef USER_DMI_OPTION
#define USER_DMI_OPTION &GetDmiInfoMain
#undef USER_DMI_RELEASE_BUFFER
#define USER_DMI_RELEASE_BUFFER &ReleaseDmiBuffer
// This additional check keeps AP launch routines from being unnecessarily included
// in single socket systems.
#if OPTION_MULTISOCKET == TRUE
#undef CPU_DMI_AP_GET_TYPE4_TYPE7
#define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info},
#endif
// Family 15
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if OPTION_FAMILY15H_TN == TRUE
extern PROC_FAMILY_TABLE ProcFamily15TnDmiTable;
#undef FAM15_TN_DMI_TABLE
#define FAM15_TN_DMI_TABLE &ProcFamily15TnDmiTable,
#endif
#endif
#endif
// Family 16
#ifdef OPTION_FAMILY16H
#if OPTION_FAMILY16H == TRUE
#if OPTION_FAMILY16H_KB
extern PROC_FAMILY_TABLE ProcFamily16KbDmiTable;
#undef FAM16_KB_DMI_TABLE
#define FAM16_KB_DMI_TABLE &ProcFamily16KbDmiTable,
#endif
#endif
#endif
#endif
#endif
/* Declare the Family List. An array of pointers to tables that each describe a family */
CONST PROC_FAMILY_TABLE ROMDATA *ProcTables[] = {
FAM15_TN_DMI_TABLE
FAM16_KB_DMI_TABLE
NULL
};
/* Declare the instance of the DMI option configuration structure */
CONST OPTION_DMI_CONFIGURATION ROMDATA OptionDmiConfiguration = {
DMI_STRUCT_VERSION,
USER_DMI_OPTION,
USER_DMI_RELEASE_BUFFER,
((sizeof (ProcTables) / sizeof (PROC_FAMILY_TABLE *)) - 1), // Including 'NULL' in above ProcTables would
// cause one more entry is counted.
(VOID *((*)[])) &ProcTables // Compiler says array size must match struct decl
};
#endif // _OPTION_DMI_INSTALL_H_

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@ -1,332 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of family 16h support
*
* This file generates the defaults tables for family 16h processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 87264 $ @e \$Date: 2013-01-31 09:26:23 -0600 (Thu, 31 Jan 2013) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_FAMILY_16H_INSTALL_H_
#define _OPTION_FAMILY_16H_INSTALL_H_
#include "OptionFamily16hEarlySample.h"
#include "cpuFamilyTranslation.h"
/*
* Pull in family specific services based on entry point
*/
/*
* Common Family 16h routines
*/
/*
* Install family 16h model 00h - 0Fh support
*/
#ifdef OPTION_FAMILY16H_KB
#if OPTION_FAMILY16H_KB == TRUE
extern CONST REGISTER_TABLE ROMDATA F16KbPciRegisterTableBeforeApLaunch;
extern CONST REGISTER_TABLE ROMDATA F16KbPciRegisterTableAfterApLaunch;
extern CONST REGISTER_TABLE ROMDATA F16KbPciWorkaroundTable;
extern CONST REGISTER_TABLE ROMDATA F16KbMsrRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F16KbMsrWorkaroundTable;
extern CONST REGISTER_TABLE ROMDATA F16KbSharedMsrRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F16KbSharedMsrWorkaroundTable;
/**
* Compute unit and Compute unit primary determination table.
*
* The four fields from the compute unit status hardware register can be used to determine whether
* even number cores are primary or all cores are primary. It can be extended if it is
* decided to have other configs as well. The other logically possible value sets are BitMapMapping,
* but they are currently not supported by the processor.
*/
CONST COMPUTE_UNIT_MAP ROMDATA HtFam16KbComputeUnitMapping[] =
{
{1, 'x', 'x', 1, QuadCoresMapping}, ///< 1 Compute Unit with 4 Cores
{1, 'x', 1, 0, TripleCoresMapping}, ///< 1 Compute Unit with 3 Cores
{1, 1, 0, 0, EvenCoresMapping}, ///< 1 Compute Unit with 2 cores
{1, 0, 0, 0, AllCoresMapping}, ///< 1 Compute Unit with 1 Cores
{HT_LIST_TERMINAL, HT_LIST_TERMINAL, HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping} ///< End
};
#if USES_REGISTER_TABLES == TRUE
CONST REGISTER_TABLE ROMDATA * CONST F16KbRegisterTables[] =
{
#if MODEL_SPECIFIC_PCI == TRUE
&F16KbPciRegisterTableBeforeApLaunch,
&F16KbPciRegisterTableAfterApLaunch,
&F16KbPciWorkaroundTable,
#endif
#if MODEL_SPECIFIC_MSR == TRUE
&F16KbMsrRegisterTable,
&F16KbMsrWorkaroundTable,
&F16KbSharedMsrRegisterTable,
&F16KbSharedMsrWorkaroundTable,
#endif
// the end.
NULL
};
#endif
#if USES_REGISTER_TABLES == TRUE
CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F16KbTableEntryTypeDescriptors[] =
{
{MsrRegister, SetRegisterForMsrEntry},
{PciRegister, SetRegisterForPciEntry},
{FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
{ProfileFixup, SetRegisterForPerformanceProfileEntry},
{CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
// End
{TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
};
#endif
/**
* Early Init Tables
*
*/
extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesBeforeApLaunch;
extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAfterApLaunch;
extern F_PERFORM_EARLY_INIT_ON_CORE F16SetBrandIdRegistersAtEarly;
extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly;
extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly;
extern F_PERFORM_EARLY_INIT_ON_CORE F16KbLoadMicrocodePatchAtEarly;
CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F16KbEarlyInitBeforeApLaunchOnCoreTable[] =
{
{SetRegistersFromTablesBeforeApLaunch, PERFORM_EARLY_ANY_CONDITION},
{LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
#if OPTION_EARLY_SAMPLES == TRUE
{LoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION},
#endif
{NULL, 0}
};
CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F16KbEarlyInitAfterApLaunchOnCoreTable[] =
{
{SetRegistersFromTablesAfterApLaunch, PERFORM_EARLY_ANY_CONDITION},
{F16SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION},
#if OPTION_EARLY_SAMPLES == FALSE
{F16KbLoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION},
#endif
{NULL, 0}
};
#include "OptionCpuSpecificServicesInstallReset.h"
#define CpuSrvcTableName cpuF16KbServices
#define CpuSrvcDisablePstate F16DisablePstate
#define CpuSrvcTransitionPstate F16TransitionPstate
#define CpuSrvcGetProcIddMax F16KbGetProcIddMax
#define CpuSrvcGetTscRate F16GetTscRate
#define CpuSrvcGetCurrentNbFrequency F16KbGetCurrentNbFrequency
#define CpuSrvcGetMinMaxNbFrequency F16KbGetMinMaxNbFrequency
#define CpuSrvcGetNbPstateInfo F16KbGetNbPstateInfo
#define CpuSrvcIsNbCofInitNeeded F16GetNbCofVidUpdate
#define CpuSrvcGetNbIddMax F16KbGetNbIddMax
#define CpuSrvcLaunchApCore F16LaunchApCore
#define CpuSrvcGetNumberOfPhysicalCores F16KbGetNumberOfPhysicalCores
#define CpuSrvcGetApMailboxFromHardware F16KbGetApMailboxFromHardware
#define CpuSrvcGetApCoreNumber F16KbGetApCoreNumber
#define CpuSrvcCoreIdPositionInInitialApicId F16CpuAmdCoreIdPositionInInitialApicId
#define CpuSrvcSetWarmResetFlag F16SetAgesaWarmResetFlag
#define CpuSrvcGetWarmResetFlag F16GetAgesaWarmResetFlag
#define CpuSrvcGetMicroCodePatchesStruct GetF16KbMicroCodePatchesStruct
#define CpuSrvcGetMicrocodeEquivalenceTable GetF16KbMicrocodeEquivalenceTable
#define CpuSrvcGetCacheInfo GetF16CacheInfo
#define CpuSrvcGetSysPmTableStruct GetF16KbSysPmTable
#define CpuSrvcGetWheaInitData GetF16WheaInitData
#define CpuSrvcIsNbPstateEnabled F16KbIsNbPstateEnabled
#define CpuSrvcRegisterTableList (REGISTER_TABLE **) F16KbRegisterTables
#define CpuSrvcTableEntryTypeDescriptors (TABLE_ENTRY_TYPE_DESCRIPTOR *) F16KbTableEntryTypeDescriptors
#define CpuSrvcComputeUnitMap (COMPUTE_UNIT_MAP *) &HtFam16KbComputeUnitMapping
#define CpuSrvcInitCacheDisabled InitCacheEnabled
#define CpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable GetF16KbEarlyInitBeforeApLaunchOnCoreTable
#define CpuSrvcGetEarlyInitAfterApLaunchOnCoreTable GetF16KbEarlyInitAfterApLaunchOnCoreTable
#define CpuSrvcPatchLoaderIsSharedByCU FALSE
#include "OptionCpuSpecificServicesInstall.h"
INSTALL_CPU_SPECIFIC_SERVICES_TABLE (CpuSrvcTableName);
#define KB_SOCKETS 1
#define KB_MODULES 1
#define KB_RECOVERY_SOCKETS 1
#define KB_RECOVERY_MODULES 1
extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF16KbLogicalIdAndRev;
#define OPT_F16_KB_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF16KbLogicalIdAndRev,
#ifndef ADVCFG_PLATFORM_SOCKETS
#define ADVCFG_PLATFORM_SOCKETS KB_SOCKETS
#else
#if ADVCFG_PLATFORM_SOCKETS < KB_SOCKETS
#undef ADVCFG_PLATFORM_SOCKETS
#define ADVCFG_PLATFORM_SOCKETS KB_SOCKETS
#endif
#endif
#ifndef ADVCFG_PLATFORM_MODULES
#define ADVCFG_PLATFORM_MODULES KB_MODULES
#else
#if ADVCFG_PLATFORM_MODULES < KB_MODULES
#undef ADVCFG_PLATFORM_MODULES
#define ADVCFG_PLATFORM_MODULES KB_MODULES
#endif
#endif
#if (AGESA_ENTRY_INIT_EARLY == TRUE)
#define F16_KB_UCODE_7000
#define F16_KB_UCODE_7001
#if AGESA_ENTRY_INIT_EARLY == TRUE
#if OPTION_EARLY_SAMPLES == TRUE
extern CONST UINT8 ROMDATA CpuF16KbId7000MicrocodePatch[];
#undef F16_KB_UCODE_7000
#define F16_KB_UCODE_7000 CpuF16KbId7000MicrocodePatch,
#endif
extern CONST UINT8 ROMDATA CpuF16KbId7001MicrocodePatch[];
#undef F16_KB_UCODE_7001
#define F16_KB_UCODE_7001 CpuF16KbId7001MicrocodePatch,
#endif
CONST UINT8 ROMDATA * CONST CpuF16KbMicroCodePatchArray[] =
{
F16_KB_UCODE_7001
F16_KB_UCODE_7000
NULL
};
CONST UINT8 ROMDATA CpuF16KbNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF16KbMicroCodePatchArray) / sizeof (CpuF16KbMicroCodePatchArray[0])) - 1);
#endif
#define OPT_F16_KB_CPU {AMD_FAMILY_16_KB, &cpuF16KbServices},
#else // OPTION_FAMILY16H_KB == TRUE
#define OPT_F16_KB_CPU
#define OPT_F16_KB_ID
#endif // OPTION_FAMILY16H_KB == TRUE
#else // defined (OPTION_FAMILY16H_KB)
#define OPT_F16_KB_CPU
#define OPT_F16_KB_ID
#endif // defined (OPTION_FAMILY16H_KB)
/*
* Install unknown family 16h support
*/
#if USES_REGISTER_TABLES == TRUE
extern CONST REGISTER_TABLE ROMDATA F16PciUnknownRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F16MsrUnknownRegisterTable;
CONST REGISTER_TABLE ROMDATA * CONST F16UnknownRegisterTables[] =
{
&F16PciUnknownRegisterTable,
&F16MsrUnknownRegisterTable
// the end.
};
#endif
#if USES_REGISTER_TABLES == TRUE
CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F16UnknownTableEntryTypeDescriptors[] =
{
{MsrRegister, SetRegisterForMsrEntry},
{PciRegister, SetRegisterForPciEntry},
// End
{TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
};
#endif
#include "OptionCpuSpecificServicesInstallReset.h"
#define CpuSrvcTableName cpuF16UnknownServices
#define CpuSrvcDisablePstate F16DisablePstate
#define CpuSrvcTransitionPstate F16TransitionPstate
#define CpuSrvcGetTscRate F16GetTscRate
#define CpuSrvcLaunchApCore F16LaunchApCore
#define CpuSrvcCoreIdPositionInInitialApicId F16CpuAmdCoreIdPositionInInitialApicId
#define CpuSrvcSetWarmResetFlag F16SetAgesaWarmResetFlag
#define CpuSrvcGetWarmResetFlag F16GetAgesaWarmResetFlag
#define CpuSrvcGetMicroCodePatchesStruct GetEmptyArray
#define CpuSrvcGetMicrocodeEquivalenceTable GetEmptyArray
#define CpuSrvcGetWheaInitData GetF16WheaInitData
#define CpuSrvcIsNbPstateEnabled F16IsNbPstateEnabled
#define CpuSrvcRegisterTableList (REGISTER_TABLE **) F16UnknownRegisterTables
#define CpuSrvcTableEntryTypeDescriptors (TABLE_ENTRY_TYPE_DESCRIPTOR *) F16UnknownTableEntryTypeDescriptors
#define CpuSrvcInitCacheDisabled InitCacheEnabled
#define CpuSrvcPatchLoaderIsSharedByCU FALSE
#include "OptionCpuSpecificServicesInstall.h"
INSTALL_CPU_SPECIFIC_SERVICES_TABLE (CpuSrvcTableName);
// Family 16h maximum base address is 40 bits. Limit BLDCFG to 40 bits, if appropriate.
#if (FAMILY_MMIO_BASE_MASK < 0xFFFFFF0000000000ull)
#undef FAMILY_MMIO_BASE_MASK
#define FAMILY_MMIO_BASE_MASK (0xFFFFFF0000000000ull)
#endif
#undef OPT_F16_ID_TABLE
#define OPT_F16_ID_TABLE {0x16, {AMD_FAMILY_16, AMD_F16_UNKNOWN}, F16LogicalIdTable, (sizeof (F16LogicalIdTable) / sizeof (F16LogicalIdTable[0]))},
#define OPT_F16_UNKNOWN_CPU {AMD_FAMILY_16, &cpuF16UnknownServices},
#undef OPT_F16_TABLE
#define OPT_F16_TABLE OPT_F16_KB_CPU OPT_F16_UNKNOWN_CPU
CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F16LogicalIdTable[] =
{
OPT_F16_KB_ID
};
#endif // _OPTION_FAMILY_16H_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: GfxRecovery
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_GFX_RECOVERY_INSTALL_H_
#define _OPTION_GFX_RECOVERY_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#endif // _OPTION_GFX_RECOVERY_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: GNB
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 87849 $ @e \$Date: 2013-02-11 15:37:58 -0600 (Mon, 11 Feb 2013) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_GNB_INSTALL_H_
#define _OPTION_GNB_INSTALL_H_
#include "S3SaveState.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
//---------------------------------------------------------------------------------------------------
// Family installation
//---------------------------------------------------------------------------------------------------
#define GNB_TYPE_TN FALSE
#define GNB_TYPE_BK FALSE
#define GNB_TYPE_KV FALSE
#define GNB_TYPE_KB FALSE
#define GNB_TYPE_BK FALSE
#define GNB_TYPE_ML FALSE
#if (OPTION_FAMILY15H_TN == TRUE)
#undef GNB_TYPE_TN
#define GNB_TYPE_TN TRUE
#endif
#if (OPTION_FAMILY16H_KB == TRUE)
#undef GNB_TYPE_KB
#define GNB_TYPE_KB TRUE
#endif
#if (GNB_TYPE_KB == TRUE || GNB_TYPE_TN == TRUE)
//---------------------------------------------------------------------------------------------------
// Service installation
//---------------------------------------------------------------------------------------------------
#include "Gnb.h"
#include "GnbPcie.h"
#include "GnbGfx.h"
#define SERVICES_POINTER NULL
#if (GNB_TYPE_TN == TRUE)
#include "GnbInitTNInstall.h"
#endif
#if (GNB_TYPE_KB == TRUE)
#include "GnbInitKBInstall.h"
#endif
CONST GNB_SERVICE * CONST ServiceTable = SERVICES_POINTER;
//---------------------------------------------------------------------------------------------------
// BUILD options
//---------------------------------------------------------------------------------------------------
#ifndef CFG_IGFX_AS_PCIE_EP
#define CFG_IGFX_AS_PCIE_EP TRUE
#endif
#ifndef CFG_LCLK_DEEP_SLEEP_EN
#if (GNB_TYPE_TN == TRUE)
#define CFG_LCLK_DEEP_SLEEP_EN FALSE
#else
#define CFG_LCLK_DEEP_SLEEP_EN TRUE
#endif
#endif
#ifndef CFG_LCLK_DPM_EN
#define CFG_LCLK_DPM_EN TRUE
#endif
#ifndef CFG_GMC_POWER_GATING
#if ((GNB_TYPE_TN == TRUE) || (GNB_TYPE_KB == TRUE))
#define CFG_GMC_POWER_GATING GmcPowerGatingWithStutter
#else
#define CFG_GMC_POWER_GATING GmcPowerGatingDisabled
#endif
#endif
#ifndef CFG_SMU_SCLK_CLOCK_GATING_ENABLE
#if (GNB_TYPE_TN == TRUE)
#define CFG_SMU_SCLK_CLOCK_GATING_ENABLE TRUE
#else
#define CFG_SMU_SCLK_CLOCK_GATING_ENABLE FALSE
#endif
#endif
#ifndef CFG_PCIE_ASPM_BLACK_LIST_ENABLE
#define CFG_PCIE_ASPM_BLACK_LIST_ENABLE TRUE
#endif
#ifndef CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT
#define CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT FALSE
#endif
#ifndef CFG_GNB_LOAD_REAL_FUSE
#define CFG_GNB_LOAD_REAL_FUSE TRUE
#endif
#ifndef CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING
#define CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000)
#endif
#ifndef CFG_GNB_PCIE_LINK_L0_POOLING
#define CFG_GNB_PCIE_LINK_L0_POOLING (60 * 1000)
#endif
#ifndef CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME
#define CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000)
#endif
#ifndef CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME
#define CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000)
#endif
#ifdef BLDCFG_PCIE_TRAINING_ALGORITHM
#define CFG_GNB_PCIE_TRAINING_ALGORITHM BLDCFG_PCIE_TRAINING_ALGORITHM
#else
#define CFG_GNB_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed
#endif
#ifndef CFG_GNB_FORCE_CABLESAFE_OFF
#define CFG_GNB_FORCE_CABLESAFE_OFF FALSE
#endif
#ifndef CFG_ORB_CLOCK_GATING_ENABLE
#define CFG_ORB_CLOCK_GATING_ENABLE TRUE
#endif
#ifndef CFG_GNB_PCIE_POWERGATING_FLAGS
#define CFG_GNB_PCIE_POWERGATING_FLAGS 0x0
#endif
#ifndef CFG_IOC_SCLK_CLOCK_GATING_ENABLE
#if (GNB_TYPE_TN == TRUE)
#define CFG_IOC_SCLK_CLOCK_GATING_ENABLE TRUE
#else
#define CFG_IOC_SCLK_CLOCK_GATING_ENABLE FALSE
#endif
#endif
#ifndef CFG_IOMMU_L1_CLOCK_GATING_ENABLE
#if (GNB_TYPE_TN == TRUE)
#define CFG_IOMMU_L1_CLOCK_GATING_ENABLE TRUE
#else
#define CFG_IOMMU_L1_CLOCK_GATING_ENABLE FALSE
#endif
#endif
#ifndef CFG_IOMMU_L2_CLOCK_GATING_ENABLE
#if (GNB_TYPE_TN == TRUE)
#define CFG_IOMMU_L2_CLOCK_GATING_ENABLE TRUE
#else
#define CFG_IOMMU_L2_CLOCK_GATING_ENABLE FALSE
#endif
#endif
#ifndef CFG_GNB_ALTVDDNB_SUPPORT
#define CFG_GNB_ALTVDDNB_SUPPORT TRUE
#endif
#ifndef CFG_GNB_BAPM_SUPPORT
#if ((GNB_TYPE_TN == TRUE) || (GNB_TYPE_KB == TRUE))
#define CFG_GNB_BAPM_SUPPORT TRUE
#else
#define CFG_GNB_BAPM_SUPPORT FALSE
#endif
#endif
#ifndef CFG_GNB_LHTC_SUPPORT
#if (GNB_TYPE_KB == TRUE)
#define CFG_GNB_LHTC_SUPPORT TRUE
#else
#define CFG_GNB_LHTC_SUPPORT FALSE
#endif
#endif
#ifndef CFG_UNUSED_SIMD_POWERGATING_ENABLE
#define CFG_UNUSED_SIMD_POWERGATING_ENABLE TRUE
#endif
#ifndef CFG_UNUSED_RB_POWERGATING_ENABLE
#define CFG_UNUSED_RB_POWERGATING_ENABLE FALSE
#endif
#ifndef CFG_NBDPM_ENABLE
#if ((GNB_TYPE_KB == TRUE))
#define CFG_NBDPM_ENABLE FALSE
#else
#define CFG_NBDPM_ENABLE TRUE
#endif
#endif
#ifndef CFG_MAX_PAYLOAD_ENABLE
#define CFG_MAX_PAYLOAD_ENABLE TRUE
#endif
#ifndef CFG_ORB_DYN_WAKE_ENABLE
#if (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
#define CFG_ORB_DYN_WAKE_ENABLE TRUE
#else
#define CFG_ORB_DYN_WAKE_ENABLE TRUE
#endif
#endif
#ifndef CFG_LOADLINE_ENABLE
#define CFG_LOADLINE_ENABLE TRUE
#endif
#ifndef CFG_PCIE_PHY_ISOLATION_SUPPORT
#if (GNB_TYPE_KB == TRUE)
#define CFG_PCIE_PHY_ISOLATION_SUPPORT TRUE
#else
#define CFG_PCIE_PHY_ISOLATION_SUPPORT FALSE
#endif
#endif
#ifndef CFG_SVI_REVISION
#if (GNB_TYPE_KB == TRUE || GNB_TYPE_TN == TRUE)
#define CFG_SVI_REVISION 2
#else
#define CFG_SVI_REVISION 1
#endif
#endif
#ifndef CFG_SCS_SUPPORT
#if ((GNB_TYPE_KB == TRUE))
#define CFG_SCS_SUPPORT TRUE
#else
#define CFG_SCS_SUPPORT FALSE
#endif
#endif
#ifndef CFG_SAMU_PATCH_ENABLED
#define CFG_SAMU_PATCH_ENABLED TRUE
#endif
#ifndef CFG_GNB_TDC_SUPPORT
#define CFG_GNB_TDC_SUPPORT TRUE
#endif
#ifndef CFG_NATIVE_GEN1_PLL_ENABLE
#define CFG_NATIVE_GEN1_PLL_ENABLE TRUE
#endif
#ifndef CFG_UMA_STEERING
#define CFG_UMA_STEERING 0
#endif
CONST GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions = {
CFG_IGFX_AS_PCIE_EP,
CFG_LCLK_DEEP_SLEEP_EN,
CFG_LCLK_DPM_EN,
CFG_GMC_POWER_GATING,
CFG_SMU_SCLK_CLOCK_GATING_ENABLE,
CFG_PCIE_ASPM_BLACK_LIST_ENABLE,
CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT,
CFG_GNB_LOAD_REAL_FUSE,
CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING,
CFG_GNB_PCIE_LINK_L0_POOLING,
CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME,
CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME,
CFG_GNB_PCIE_TRAINING_ALGORITHM,
CFG_GNB_FORCE_CABLESAFE_OFF,
CFG_ORB_CLOCK_GATING_ENABLE,
CFG_GNB_PCIE_POWERGATING_FLAGS,
TRUE,
CFG_IOC_SCLK_CLOCK_GATING_ENABLE,
CFG_IOMMU_L1_CLOCK_GATING_ENABLE,
CFG_IOMMU_L2_CLOCK_GATING_ENABLE,
CFG_GNB_ALTVDDNB_SUPPORT,
CFG_GNB_BAPM_SUPPORT,
CFG_UNUSED_SIMD_POWERGATING_ENABLE,
CFG_UNUSED_RB_POWERGATING_ENABLE,
CFG_NBDPM_ENABLE,
TRUE,
CFG_MAX_PAYLOAD_ENABLE,
CFG_ORB_DYN_WAKE_ENABLE,
CFG_LOADLINE_ENABLE,
CFG_PCIE_PHY_ISOLATION_SUPPORT,
CFG_GNB_LHTC_SUPPORT,
CFG_SVI_REVISION,
CFG_SCS_SUPPORT,
CFG_SAMU_PATCH_ENABLED,
{CFG_ACPI_SET_OEM_ID},
{CFG_ACPI_SET_OEM_TABLE_ID},
CFG_GNB_TDC_SUPPORT,
TRUE,
CFG_NATIVE_GEN1_PLL_ENABLE,
CFG_UMA_STEERING
};
//---------------------------------------------------------------------------------------------------
// SMU Firmware
//---------------------------------------------------------------------------------------------------
//---------------------------------------------------------------------------------------------------
// Module entries
//---------------------------------------------------------------------------------------------------
#if (AGESA_ENTRY_INIT_EARLY == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_EARLY_INIT
#define OPTION_NB_EARLY_INIT TRUE
#endif
#if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
OPTION_GNB_FEATURE GnbEarlyInterfaceTN;
#define OPTION_GNBEARLYINTERFACETN_ENTRY {AMD_FAMILY_TN, GnbEarlyInterfaceTN, TpGnbEarlyInterface},
#else
#define OPTION_GNBEARLYINTERFACETN_ENTRY
#endif
#if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
OPTION_GNB_FEATURE GnbEarlyInterfaceKB;
#define OPTION_GNBEARLYINTERFACEKB_ENTRY {AMD_FAMILY_KB, GnbEarlyInterfaceKB, TpGnbEarlyInterface},
#else
#define OPTION_GNBEARLYINTERFACEKB_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_CONFIG_MAP
#define OPTION_PCIE_CONFIG_MAP TRUE
#endif
#if (OPTION_PCIE_CONFIG_MAP == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
OPTION_GNB_FEATURE PcieConfigurationMap;
#define OPTION_PCIECONFIGURATIONMAP_ENTRY {AMD_FAMILY_TN | AMD_FAMILY_KB, PcieConfigurationMap, TpGnbPcieConfigurationMap},
#else
#define OPTION_PCIECONFIGURATIONMAP_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_EARLY_INIT
#define OPTION_PCIE_EARLY_INIT TRUE
#endif
#if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
OPTION_GNB_FEATURE PcieEarlyInterfaceTN;
#define OPTION_PCIEEARLYINTERFACETN_ENTRY {AMD_FAMILY_TN, PcieEarlyInterfaceTN, TpGnbPcieEarlyInterface},
#else
#define OPTION_PCIEEARLYINTERFACETN_ENTRY
#endif
#if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
OPTION_GNB_FEATURE PcieEarlyInterfaceKB;
#define OPTION_PCIEEARLYINTERFACEKB_ENTRY {AMD_FAMILY_KB, PcieEarlyInterfaceKB, TpGnbPcieEarlyInterface},
#else
#define OPTION_PCIEEARLYINTERFACEKB_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
CONST OPTION_GNB_CONFIGURATION GnbEarlyFeatureTable[] = {
OPTION_GNBEARLYINTERFACETN_ENTRY
OPTION_GNBEARLYINTERFACEKB_ENTRY
OPTION_PCIECONFIGURATIONMAP_ENTRY
OPTION_PCIEEARLYINTERFACETN_ENTRY
OPTION_PCIEEARLYINTERFACEKB_ENTRY
{0, NULL, EndGnbTestPoints}
};
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_CONFIG_INIT
#define OPTION_PCIE_CONFIG_INIT TRUE
#endif
#if (OPTION_PCIE_CONFIG_INIT == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
OPTION_GNB_FEATURE PcieConfigurationInit;
#define OPTION_PCIECONFIGURATIONINIT_ENTRY {AMD_FAMILY_TN | AMD_FAMILY_KB, PcieConfigurationInit, TpGnbEarlierPcieConfigurationInit},
#else
#define OPTION_PCIECONFIGURATIONINIT_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_EARLIER_INIT
#define OPTION_NB_EARLIER_INIT TRUE
#endif
#if (OPTION_NB_EARLIER_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
OPTION_GNB_FEATURE GnbEarlierInterfaceTN;
#define OPTION_GNBEARLIERINTERFACETN_ENTRY {AMD_FAMILY_TN, GnbEarlierInterfaceTN, TpGnbEarlierInterface},
#else
#define OPTION_GNBEARLIERINTERFACETN_ENTRY
#endif
#if (OPTION_NB_EARLIER_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
OPTION_GNB_FEATURE GnbEarlierInterfaceKB;
#define OPTION_GNBEARLIERINTERFACEKB_ENTRY {AMD_FAMILY_KB, GnbEarlierInterfaceKB, TpGnbEarlierInterface},
#else
#define OPTION_GNBEARLIERINTERFACEKB_ENTRY
#endif
#if (OPTION_NB_EARLIER_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
OPTION_GNB_FEATURE OptionGnbInstall581;
#define OPTION_GNBSCSINTERFACEKB_ENTRY {AMD_FAMILY_KB, OptionGnbInstall581, TpGnbEarlierInterface},
#else
#define OPTION_GNBSCSINTERFACEKB_ENTRY
#endif
CONST OPTION_GNB_CONFIGURATION GnbEarlierFeatureTable[] = {
OPTION_PCIECONFIGURATIONINIT_ENTRY
OPTION_GNBEARLIERINTERFACETN_ENTRY
OPTION_GNBEARLIERINTERFACEKB_ENTRY
OPTION_GNBSCSINTERFACEKB_ENTRY
{0, NULL, EndGnbTestPoints}
};
#endif
#if (AGESA_ENTRY_INIT_POST == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_CONFIG_POST_INIT
#define OPTION_GFX_CONFIG_POST_INIT TRUE
#endif
#if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
OPTION_GNB_FEATURE GfxConfigPostInterface;
#define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY {AMD_FAMILY_TN | AMD_FAMILY_KB, GfxConfigPostInterface, TpGnbGfxConfigPostInterface},
#else
#define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_POST_INIT
#define OPTION_GFX_POST_INIT TRUE
#endif
#if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
OPTION_GNB_FEATURE GfxPostInterfaceTN;
#define OPTION_GFXPOSTINTERFACETN_ENTRY {AMD_FAMILY_TN, GfxPostInterfaceTN, TpGnbGfxPostInterface},
#else
#define OPTION_GFXPOSTINTERFACETN_ENTRY
#endif
#if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
OPTION_GNB_FEATURE GfxPostInterfaceKB;
#define OPTION_GFXPOSTINTERFACEKB_ENTRY {AMD_FAMILY_KB, GfxPostInterfaceKB, TpGnbGfxPostInterface},
#else
#define OPTION_GFXPOSTINTERFACEKB_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_POST_INIT
#define OPTION_NB_POST_INIT TRUE
#endif
#if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
OPTION_GNB_FEATURE GnbPostInterfaceTN;
#define OPTION_GNBPOSTINTERFACETN_ENTRY {AMD_FAMILY_TN, GnbPostInterfaceTN, TpGnbPostInterface},
#else
#define OPTION_GNBPOSTINTERFACETN_ENTRY
#endif
#if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
OPTION_GNB_FEATURE GnbPostInterfaceKB;
#define OPTION_GNBPOSTINTERFACEKB_ENTRY {AMD_FAMILY_KB, GnbPostInterfaceKB, TpGnbPostInterface},
#else
#define OPTION_GNBPOSTINTERFACEKB_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_POST_EARLY_INIT
#define OPTION_PCIE_POST_EARLY_INIT TRUE
#endif
#if (OPTION_PCIE_POST_EARLY_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
OPTION_GNB_FEATURE PciePostEarlyInterfaceTN;
#define OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY {AMD_FAMILY_TN, PciePostEarlyInterfaceTN, TpGnbPciePostEarlyInterface},
#else
#define OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY
#endif
#if (OPTION_PCIE_POST_EARLY_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
OPTION_GNB_FEATURE PciePostEarlyInterfaceKB;
#define OPTION_PCIEPOSTEARLYINTERFACEKB_ENTRY {AMD_FAMILY_KB, PciePostEarlyInterfaceKB, TpGnbPciePostEarlyInterface},
#else
#define OPTION_PCIEPOSTEARLYINTERFACEKB_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_POST_INIT
#define OPTION_PCIE_POST_INIT TRUE
#endif
#if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
OPTION_GNB_FEATURE PciePostInterfaceTN;
#define OPTION_PCIEPOSTINTERFACETN_ENTRY {AMD_FAMILY_TN, PciePostInterfaceTN, TpGnbPciePostInterface},
#else
#define OPTION_PCIEPOSTINTERFACETN_ENTRY
#endif
#if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
OPTION_GNB_FEATURE PciePostInterfaceKB;
#define OPTION_PCIEPOSTINTERFACEKB_ENTRY {AMD_FAMILY_KB, PciePostInterfaceKB, TpGnbPciePostInterface},
#else
#define OPTION_PCIEPOSTINTERFACEKB_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
CONST OPTION_GNB_CONFIGURATION GnbPostFeatureTable[] = {
OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY
OPTION_PCIEPOSTEARLYINTERFACEKB_ENTRY
OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
OPTION_GFXPOSTINTERFACETN_ENTRY
OPTION_GFXPOSTINTERFACEKB_ENTRY
{0, NULL, EndGnbTestPoints}
};
CONST OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[] = {
OPTION_GNBPOSTINTERFACETN_ENTRY
OPTION_GNBPOSTINTERFACEKB_ENTRY
OPTION_PCIEPOSTINTERFACETN_ENTRY
OPTION_PCIEPOSTINTERFACEKB_ENTRY
{0, NULL, EndGnbTestPoints}
};
#endif
#if (AGESA_ENTRY_INIT_ENV == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_ENV_INIT
#define OPTION_NB_ENV_INIT TRUE
#endif
#if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
OPTION_GNB_FEATURE GnbEnvInterfaceTN;
#define OPTION_GNBENVINTERFACETN_ENTRY {AMD_FAMILY_TN, GnbEnvInterfaceTN, TpGnbEnvInterface},
#else
#define OPTION_GNBENVINTERFACETN_ENTRY
#endif
#if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
OPTION_GNB_FEATURE GnbEnvInterfaceKB;
#define OPTION_GNBENVINTERFACEKB_ENTRY {AMD_FAMILY_KB, GnbEnvInterfaceKB, TpGnbEnvInterface},
#else
#define OPTION_GNBENVINTERFACEKB_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_CONFIG_ENV_INIT
#define OPTION_GFX_CONFIG_ENV_INIT TRUE
#endif
#if (OPTION_GFX_CONFIG_ENV_INIT == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
OPTION_GNB_FEATURE GfxConfigEnvInterface;
#define OPTION_GFXCONFIGENVINTERFACE_ENTRY {AMD_FAMILY_TN | AMD_FAMILY_KB, GfxConfigEnvInterface, TpGnbGfxConfigEnvInterface},
#else
#define OPTION_GFXCONFIGENVINTERFACE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_ENV_INIT
#define OPTION_GFX_ENV_INIT TRUE
#endif
#if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
OPTION_GNB_FEATURE GfxEnvInterfaceTN;
#define OPTION_GFXENVINTERFACETN_ENTRY {AMD_FAMILY_TN, GfxEnvInterfaceTN, TpGnbGfxEnvInterface},
#else
#define OPTION_GFXENVINTERFACETN_ENTRY
#endif
#if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
OPTION_GNB_FEATURE GfxEnvInterfaceKB;
#define OPTION_GFXENVINTERFACEKB_ENTRY {AMD_FAMILY_KB, GfxEnvInterfaceKB, TpGnbGfxEnvInterface},
#else
#define OPTION_GFXENVINTERFACEKB_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_ENV_INIT
#define OPTION_PCIE_ENV_INIT TRUE
#endif
#if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
OPTION_GNB_FEATURE PcieEnvInterfaceTN;
#define OPTION_PCIEENVINTERFACETN_ENTRY {AMD_FAMILY_TN, PcieEnvInterfaceTN, TpGnbPcieEnvInterface},
#else
#define OPTION_PCIEENVINTERFACETN_ENTRY
#endif
#if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
OPTION_GNB_FEATURE PcieEnvInterfaceKB;
#define OPTION_PCIEENVINTERFACEKB_ENTRY {AMD_FAMILY_KB, PcieEnvInterfaceKB, TpGnbPcieEnvInterface},
#else
#define OPTION_PCIEENVINTERFACEKB_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
CONST OPTION_GNB_CONFIGURATION GnbEnvFeatureTable[] = {
OPTION_GNBENVINTERFACETN_ENTRY
OPTION_GNBENVINTERFACEKB_ENTRY
OPTION_PCIEENVINTERFACETN_ENTRY
OPTION_PCIEENVINTERFACEKB_ENTRY
OPTION_GFXCONFIGENVINTERFACE_ENTRY
OPTION_GFXENVINTERFACETN_ENTRY
OPTION_GFXENVINTERFACEKB_ENTRY
{0, NULL, EndGnbTestPoints}
};
#endif
#if (AGESA_ENTRY_INIT_MID == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_MID_INIT
#define OPTION_GFX_MID_INIT TRUE
#endif
#if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
OPTION_GNB_FEATURE GfxMidInterfaceTN;
#define OPTION_GFXMIDINTERFACETN_ENTRY {AMD_FAMILY_TN, GfxMidInterfaceTN, TpGnbGfxMidInterface},
#else
#define OPTION_GFXMIDINTERFACETN_ENTRY
#endif
#if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
OPTION_GNB_FEATURE GfxMidInterfaceKB;
#define OPTION_GFXMIDINTERFACEKB_ENTRY {AMD_FAMILY_KB, GfxMidInterfaceKB, TpGnbGfxMidInterface},
#else
#define OPTION_GFXMIDINTERFACEKB_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_INTEGRATED_TABLE_INIT
#define OPTION_GFX_INTEGRATED_TABLE_INIT TRUE
#endif
#if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
OPTION_GNB_FEATURE GfxIntInfoTableInterfaceTN;
#define OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY {AMD_FAMILY_TN, GfxIntInfoTableInterfaceTN},
#else
#define OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY
#endif
#if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
OPTION_GNB_FEATURE GfxIntInfoTableInterfaceKB;
#define OPTION_GFXINTINFOTABLEINTERFACEKB_ENTRY {AMD_FAMILY_KB, GfxIntInfoTableInterfaceKB},
#else
#define OPTION_GFXINTINFOTABLEINTERFACEKB_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIe_MID_INIT
#define OPTION_PCIe_MID_INIT TRUE
#endif
#if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
OPTION_GNB_FEATURE PcieMidInterfaceTN;
#define OPTION_PCIEMIDINTERFACETN_ENTRY {AMD_FAMILY_TN, PcieMidInterfaceTN, TpPcieMidInterface},
#else
#define OPTION_PCIEMIDINTERFACETN_ENTRY
#endif
#if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
OPTION_GNB_FEATURE PcieMidInterfaceKB;
#define OPTION_PCIEMIDINTERFACEKB_ENTRY {AMD_FAMILY_KB, PcieMidInterfaceKB, TpPcieMidInterface},
#else
#define OPTION_PCIEMIDINTERFACEKB_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_MID_INIT
#define OPTION_NB_MID_INIT TRUE
#endif
#if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
OPTION_GNB_FEATURE GnbMidInterfaceTN;
#define OPTION_GNBMIDINTERFACETN_ENTRY {AMD_FAMILY_TN, GnbMidInterfaceTN, TpGnbMidInterface},
#else
#define OPTION_GNBMIDINTERFACETN_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_CONFIG_POST_INIT
#define OPTION_GFX_CONFIG_POST_INIT TRUE
#endif
#if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
OPTION_GNB_FEATURE GfxConfigMidInterface;
#define OPTION_GFXCONFIGMIDINTERFACE_ENTRY {AMD_FAMILY_TN | AMD_FAMILY_KB, GfxConfigMidInterface, TpGnbGfxConfigMidInterface},
#else
#define OPTION_GFXCONFIGMIDINTERFACE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
OPTION_GNB_FEATURE GnbMidInterfaceKB;
#define OPTION_GNBMIDINTERFACEKB_ENTRY {AMD_FAMILY_KB, GnbMidInterfaceKB, TpGnbMidInterface},
#else
#define OPTION_GNBMIDINTERFACEKB_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_MAXPAYLOAD_INTERFACE
#define OPTION_PCIE_MAXPAYLOAD_INTERFACE TRUE
#endif
#if (OPTION_PCIE_MAXPAYLOAD_INTERFACE == TRUE) && (GNB_TYPE_KB == TRUE)
OPTION_GNB_FEATURE PcieMaxPayloadInterface;
#define OPTION_PCIEMAXPAYLOADINTERFACE_ENTRY {AMD_FAMILY_TN | AMD_FAMILY_KB, PcieMaxPayloadInterface, TpGnbPcieMaxPayloadInterface},
#else
#define OPTION_PCIEMAXPAYLOADINTERFACE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_CLK_PM_INTERFACE
#define OPTION_PCIE_CLK_PM_INTERFACE FALSE
#if (GNB_TYPE_TN == TRUE && (OPTION_FS1_SOCKET_SUPPORT == TRUE || OPTION_FP1_SOCKET_SUPPORT == TRUE))
#undef OPTION_PCIE_CLK_PM_INTERFACE
#define OPTION_PCIE_CLK_PM_INTERFACE TRUE
#endif
#if (GNB_TYPE_KB == TRUE)
#undef OPTION_PCIE_CLK_PM_INTERFACE
#define OPTION_PCIE_CLK_PM_INTERFACE TRUE
#endif
#endif
#if (OPTION_PCIE_CLK_PM_INTERFACE == TRUE) && (GNB_TYPE_KB == TRUE)
OPTION_GNB_FEATURE PcieClkPmInterface;
#define OPTION_PCIECLKPMINTERFACE_ENTRY {AMD_FAMILY_TN | AMD_FAMILY_KB, PcieClkPmInterface, TpGnbPcieClkPmInterface},
#else
#define OPTION_PCIECLKPMINTERFACE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_ASPM_INTERFACE
#define OPTION_PCIE_ASPM_INTERFACE TRUE
#endif
#if (OPTION_PCIE_ASPM_INTERFACE == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
OPTION_GNB_FEATURE PcieAspmInterface;
#define OPTION_PCIEASPMINTERFACE_ENTRY {AMD_FAMILY_TN | AMD_FAMILY_KB, PcieAspmInterface, TpGnbPcieAspmInterface},
#else
#define OPTION_PCIEASPMINTERFACE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GNB_IOAPIC_INTERFACE
#define OPTION_GNB_IOAPIC_INTERFACE TRUE
#endif
#if (OPTION_GNB_IOAPIC_INTERFACE == TRUE) && (GNB_TYPE_KB == TRUE)
OPTION_GNB_FEATURE GnbNbIoapicInterface;
#define OPTION_GNBNBIOAPICINTERFACE_ENTRY {AMD_FAMILY_KB, GnbNbIoapicInterface, TpGnbNbIoapicInterface},
#else
#define OPTION_GNBNBIOAPICINTERFACE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
CONST OPTION_GNB_CONFIGURATION GnbMidFeatureTable[] = {
OPTION_GFXCONFIGMIDINTERFACE_ENTRY
OPTION_GFXMIDINTERFACETN_ENTRY
OPTION_GFXMIDINTERFACEKB_ENTRY
OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY
OPTION_GFXINTINFOTABLEINTERFACEKB_ENTRY
OPTION_PCIEMIDINTERFACETN_ENTRY
OPTION_PCIEMIDINTERFACEKB_ENTRY
OPTION_GNBMIDINTERFACETN_ENTRY
OPTION_GNBMIDINTERFACEKB_ENTRY
OPTION_PCIEMAXPAYLOADINTERFACE_ENTRY
OPTION_PCIECLKPMINTERFACE_ENTRY
OPTION_PCIEASPMINTERFACE_ENTRY
OPTION_GNBNBIOAPICINTERFACE_ENTRY
{0, NULL, EndGnbTestPoints}
};
#endif
#if (AGESA_ENTRY_INIT_LATE == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_ALIB
#define OPTION_ALIB FALSE
#endif
#if (OPTION_ALIB == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
#define ALIB_CALL_TABLE
#define ALIB_CALL_TABLEV2
#if (GNB_TYPE_TN == TRUE)
#if ((OPTION_FM2_SOCKET_SUPPORT == TRUE) || (OPTION_FM2r2_SOCKET_SUPPORT == TRUE))
extern F_ALIB_UPDATE PcieAlibUpdatePcieMmioInfo;
extern F_ALIB_GET PcieAlibGetBaseTableTNFM2;
F_ALIB_GET *AlibGetBaseTable = PcieAlibGetBaseTableTNFM2;
#undef ALIB_CALL_TABLE
#define ALIB_CALL_TABLE PcieAlibUpdatePcieMmioInfo,
#else
extern F_ALIB_UPDATE PcieAlibUpdatePcieMmioInfo;
extern F_ALIB_GET PcieAlibGetBaseTableTNFS1;
F_ALIB_GET *AlibGetBaseTable = PcieAlibGetBaseTableTNFS1;
extern F_ALIB_UPDATE PcieAlibUpdateVoltageInfo;
extern F_ALIB_UPDATE PcieAlibUpdatePcieInfo;
#undef ALIB_CALL_TABLE
#define ALIB_CALL_TABLE PcieAlibUpdatePcieMmioInfo, \
PcieAlibUpdateVoltageInfo, \
PcieAlibUpdatePcieInfo,
#endif
#endif
#if (GNB_TYPE_KB == TRUE)
extern F_ALIB_GET PcieAlibGetBaseTableKB;
F_ALIB_GET * CONST AlibGetBaseTableV2 = PcieAlibGetBaseTableKB;
extern F_ALIB_UPDATE PcieAlibUpdateVoltageData;
extern F_ALIB_UPDATE PcieAlibUpdatePcieData;
#undef ALIB_CALL_TABLEV2
#define ALIB_CALL_TABLEV2 PcieAlibUpdateVoltageData, \
PcieAlibUpdatePcieData,
#endif
F_ALIB_UPDATE* CONST AlibDispatchTable [] = {
ALIB_CALL_TABLE
NULL
};
F_ALIB_UPDATE* CONST AlibDispatchTableV2 [] = {
ALIB_CALL_TABLEV2
NULL
};
#if (GNB_TYPE_TN == TRUE)
OPTION_GNB_FEATURE PcieAlibFeature;
#define OPTION_PCIEALIBFEATURE_ENTRY {AMD_FAMILY_TN, PcieAlibFeature, TpGnbPcieAlibFeature},
#endif
#if ((GNB_TYPE_KB == TRUE))
OPTION_GNB_FEATURE PcieAlibV2Feature;
#define OPTION_PCIEALIBV2FEATURE_ENTRY {AMD_FAMILY_KB, PcieAlibV2Feature, TpGnbPcieAlibFeature},
#endif
#else
F_ALIB_GET * CONST AlibGetBaseTable = NULL;
F_ALIB_GET * CONST AlibGetBaseTableV2 = NULL;
F_ALIB_UPDATE* CONST AlibDispatchTable [] = {
NULL
};
F_ALIB_UPDATE* CONST AlibDispatchTableV2 [] = {
NULL
};
#define OPTION_PCIEALIBFEATURE_ENTRY
#define OPTION_PCIEALIBV2FEATURE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_IOMMU_ACPI_IVRS
#if (CFG_IOMMU_SUPPORT == TRUE)
#define OPTION_IOMMU_ACPI_IVRS TRUE
#else
#define OPTION_IOMMU_ACPI_IVRS FALSE
#endif
#endif
#if (OPTION_IOMMU_ACPI_IVRS == TRUE) && (GNB_TYPE_TN == TRUE)
OPTION_GNB_FEATURE GnbIommuIvrsTable;
#define OPTIONIOMMUACPIIVRSLATE_ENTRY {AMD_FAMILY_TN, GnbIommuIvrsTable},
#else
#define OPTIONIOMMUACPIIVRSLATE_ENTRY
#endif
#if (CFG_IOMMU_SUPPORT == TRUE) && (GNB_TYPE_TN == TRUE)
OPTION_GNB_FEATURE GnbIommuScratchMemoryRangeInterface;
#define OPTIONIOMMUSCRATCHMEMORYLATE_ENTRY {AMD_FAMILY_TN, GnbIommuScratchMemoryRangeInterface, TpGnbIommuIvrsTable},
#else
#define OPTIONIOMMUSCRATCHMEMORYLATE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
CONST OPTION_GNB_CONFIGURATION GnbLateFeatureTable[] = {
#if (GNB_TYPE_TN == TRUE)
OPTION_PCIEALIBFEATURE_ENTRY
#endif
#if ((GNB_TYPE_KB == TRUE))
OPTION_PCIEALIBV2FEATURE_ENTRY
#endif
OPTIONIOMMUSCRATCHMEMORYLATE_ENTRY
OPTIONIOMMUACPIIVRSLATE_ENTRY
{0, NULL, EndGnbTestPoints}
};
#endif
#if (AGESA_ENTRY_INIT_S3SAVE == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_INIT_SVIEW
#define OPTION_GFX_INIT_SVIEW FALSE
#endif
#if (OPTION_GFX_INIT_SVIEW == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
OPTION_GNB_FEATURE GfxInitSview;
#define OPTION_GFXINITSVIEW_ENTRY {AMD_FAMILY_TN | AMD_FAMILY_KB, GfxInitSview},
#else
#define OPTION_GFXINITSVIEW_ENTRY
#endif
CONST OPTION_GNB_CONFIGURATION GnbS3SaveFeatureTable[] = {
OPTION_GFXINITSVIEW_ENTRY
{0, NULL, EndGnbTestPoints}
};
#endif
#if (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
#define GNBS3RESTOREV4
#define GNBS3RESTOREV7
#if (GNB_TYPE_TN == TRUE)
S3_DISPATCH_FUNCTION GnbSmuServiceRequestV4S3Script;
#undef GNBS3RESTOREV4
#define GNBS3RESTOREV4 {GnbSmuServiceRequestV4S3Script_ID, GnbSmuServiceRequestV4S3Script},
#endif
#if (GNB_TYPE_KB == TRUE)
S3_DISPATCH_FUNCTION GnbSmuServiceRequestV7S3Script;
#undef GNBS3RESTOREV7
#define GNBS3RESTOREV7 {GnbSmuServiceRequestV7S3Script_ID, GnbSmuServiceRequestV7S3Script},
#endif
S3_DISPATCH_FUNCTION GnbLibStallS3Script;
#define PCIELATERESTORETN
#define PCIELATERESTOREKB
#define GFXSCLKRESTORETN
#if (GNB_TYPE_TN == TRUE)
S3_DISPATCH_FUNCTION PcieLateRestoreInitTNS3Script;
S3_DISPATCH_FUNCTION GfxRequestSclkTNS3Script;
#undef PCIELATERESTORETN
#define PCIELATERESTORETN {PcieLateRestoreTNS3Script_ID, PcieLateRestoreInitTNS3Script},
#undef GFXSCLKRESTORETN
#define GFXSCLKRESTORETN {GfxRequestSclkTNS3Script_ID, GfxRequestSclkTNS3Script },
#endif
#if (GNB_TYPE_KB == TRUE)
S3_DISPATCH_FUNCTION PcieLateRestoreInitKBS3Script;
#undef PCIELATERESTOREKB
#define PCIELATERESTOREKB {PcieLateRestoreKBS3Script_ID, PcieLateRestoreInitKBS3Script},
#endif
#define GNB_S3_DISPATCH_FUNCTION_TABLE \
GNBS3RESTOREV4 \
GNBS3RESTOREV7 \
PCIELATERESTORETN \
GFXSCLKRESTORETN \
PCIELATERESTOREKB \
{GnbLibStallS3Script_ID, GnbLibStallS3Script},
#endif
#endif
#endif // _OPTION_GNB_INSTALL_H_

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src/vendorcode/amd/agesa/f16kb/Config/OptionHtInstall.h
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@ -1,244 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Ht
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84154 $ @e \$Date: 2012-12-12 17:02:37 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_HT_INSTALL_H_
#define _OPTION_HT_INSTALL_H_
#include "Topology.h"
#include "htFeat.h"
#include "htInterface.h"
#include "htNb.h"
#include "htTopologies.h"
/*
* Advanced Option only, hardware socket naming is the preferred method.
*/
#ifdef BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP
#define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP)
#else
#define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (NULL)
#endif
/*
* OPTION_IS_RECOVERY_HT is true if Basic API is being used.
*/
#ifndef OPTION_IS_RECOVERY_HT
#define OPTION_IS_RECOVERY_HT TRUE
#endif
/*
* Macros will generate the correct item reference based on options
*/
#if AGESA_ENTRY_INIT_EARLY == TRUE
// Select the interface and features
#if ((OPTION_FAMILY15H_TN == TRUE) || (OPTION_FAMILY16H_KB == TRUE))
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
#define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNone
#define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceMapsOnly
#endif
// Select Northbridge components
#if OPTION_FAMILY15H == TRUE
#if OPTION_FAMILY15H_TN == TRUE
#define INTERNAL_HT_OPTION_FAM15TN_NB &HtFam15Mod1xNb,
#else
#define INTERNAL_HT_OPTION_FAM15TN_NB
#endif
#else
#define INTERNAL_HT_OPTION_FAM15TN_NB
#endif
#if OPTION_FAMILY16H == TRUE
#if OPTION_FAMILY16H_KB == TRUE
#define INTERNAL_HT_OPTION_FAM16KB_NB &HtFam16Nb,
#else
#define INTERNAL_HT_OPTION_FAM16KB_NB
#endif
#else
#define INTERNAL_HT_OPTION_FAM16KB_NB
#endif
#define INTERNAL_ONLY_NB_LIST_ITEM INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS,
#ifndef INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS
#undef INTERNAL_ONLY_NB_LIST_ITEM
#define INTERNAL_ONLY_NB_LIST_ITEM
#endif
/* Install the correct set of northbridge implementations. Each item provides its own comma, the last item
* is ok to have a comma because the final item (NULL) is added below.
*/
#define INTERNAL_HT_OPTION_SUPPORTED_NBS \
INTERNAL_ONLY_NB_LIST_ITEM \
INTERNAL_HT_OPTION_FAM15TN_NB \
INTERNAL_HT_OPTION_FAM16KB_NB
#else
// Not Init Early
#define INTERNAL_HT_OPTION_FEATURES NULL
#define INTERNAL_HT_OPTION_INTERFACE NULL
#define INTERNAL_HT_OPTION_SUPPORTED_NBS NULL
#define HT_OPTIONS_PLATFORM NULL
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
#endif
#ifdef AGESA_ENTRY_INIT_EARLY
#if AGESA_ENTRY_INIT_EARLY == TRUE
extern HT_FEATURES HtFeaturesDefault;
extern HT_FEATURES HtFeaturesCoherentOnly;
extern HT_FEATURES HtFeaturesNone;
extern HT_INTERFACE HtInterfaceDefault;
extern HT_INTERFACE HtInterfaceCoherentOnly;
extern HT_INTERFACE HtInterfaceMapsOnly;
extern HT_INTERFACE HtInterfaceNone;
extern NORTHBRIDGE HtFam15Mod4xNb;
extern NORTHBRIDGE HtFam15Mod1xNb;
extern NORTHBRIDGE HtFam16Nb;
CONST VOID * CONST ROMDATA HtInstalledFamilyNorthbridgeList[] = {
INTERNAL_HT_OPTION_SUPPORTED_NBS
NULL
};
STATIC CONST AMD_HT_INTERFACE ROMDATA HtOptionsPlatform =
{
CFG_STARTING_BUSNUM, CFG_MAXIMUM_BUSNUM, CFG_ALLOCATED_BUSNUM,
(MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
(DEVICE_CAP_OVERRIDE *)CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST,
(CPU_TO_CPU_PCB_LIMITS *)CFG_HTFABRIC_LIMITS_LIST,
(IO_PCB_LIMITS *)CFG_HTCHAIN_LIMITS_LIST,
(OVERRIDE_BUS_NUMBERS *)CFG_BUS_NUMBERS_LIST,
(IGNORE_LINK *)CFG_IGNORE_LINK_LIST,
(SKIP_REGANG *)CFG_LINK_SKIP_REGANG_LIST,
(UINT8 **)CFG_ADDITIONAL_TOPOLOGIES_LIST,
(SYSTEM_PHYSICAL_SOCKET_MAP *)CFG_SYSTEM_PHYSICAL_SOCKET_MAP
};
#ifndef HT_OPTIONS_PLATFORM
#define HT_OPTIONS_PLATFORM &HtOptionsPlatform
#endif
/**
* A list of all the supported topologies.
*
*/
#ifndef INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
CONST UINT8 *CONST ROMDATA AmdTopolist[] =
{
amdHtTopologySingleNode,
amdHtTopologyDualNode,
amdHtTopologyThreeLine,
amdHtTopologyTriangle,
amdHtTopologyFourLine,
amdHtTopologyFourStar,
amdHtTopologyFourDegenerate,
amdHtTopologyFourSquare,
amdHtTopologyFourKite,
amdHtTopologyFourFully,
amdHtTopologyFiveFully,
amdHtTopologyFiveTwistedLadder,
amdHtTopologySixFully,
amdHtTopologySixDoubloonLower,
amdHtTopologySixDoubloonUpper,
amdHtTopologySixTwistedLadder,
amdHtTopologySevenFully,
amdHtTopologySevenTwistedLadder,
amdHtTopologyEightFully,
amdHtTopologyEightDoubloon,
amdHtTopologyEightTwistedLadder,
amdHtTopologyEightStraightLadder,
amdHtTopologySixTwinTriangles,
amdHtTopologyEightTwinFullyFourWays,
NULL
};
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES AmdTopolist
#endif
/**
* Declare the instance of the Ht option configuration structure
*/
CONST OPTION_HT_CONFIGURATION ROMDATA OptionHtConfiguration = {
OPTION_IS_RECOVERY_HT,
CFG_SET_HTCRC_SYNC_FLOOD,
CFG_USE_UNIT_ID_CLUMPING,
HT_OPTIONS_PLATFORM,
INTERNAL_HT_OPTION_INTERFACE,
INTERNAL_HT_OPTION_FEATURES,
&HtInstalledFamilyNorthbridgeList,
INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
};
#endif
#endif
#ifndef OPTION_HT_INIIT_RESET_ENTRY
#define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
#define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY AmdHtResetConstructor
#if ((OPTION_FAMILY15H_TN == TRUE) || (OPTION_FAMILY16H == TRUE))
#undef OPTION_HT_INIIT_RESET_ENTRY
#undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
#define OPTION_HT_INIIT_RESET_ENTRY NULL
#define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY NULL
#endif
#endif
#ifdef AGESA_ENTRY_INIT_RESET
#if AGESA_ENTRY_INIT_RESET == TRUE
CONST AMD_HT_RESET_INTERFACE ROMDATA HtOptionResetDefaults = {
(MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
0 // Unused by options
};
CONST OPTION_HT_INIT_RESET ROMDATA HtOptionInitReset = {
OPTION_HT_INIIT_RESET_ENTRY,
OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
};
#endif
#endif
#endif // _OPTION_HT_INSTALL_H_

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src/vendorcode/amd/agesa/f16kb/Config/OptionHtcInstall.h
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@ -1,102 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Hardware Thermal Control (HTC).
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_HTC_INSTALL_H_
#define _OPTION_HTC_INSTALL_H_
#include "cpuHtc.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPU_HTC_FEAT
#define F15_TN_HTC_SUPPORT
#define F16_KB_HTC_SUPPORT
#if OPTION_CPU_HTC == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
// Family 15h
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if OPTION_FAMILY15H_TN == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHtc;
#undef OPTION_CPU_HTC_FEAT
#define OPTION_CPU_HTC_FEAT &CpuFeatureHtc,
extern CONST HTC_FAMILY_SERVICES ROMDATA F15TnHtcSupport;
#undef F15_TN_HTC_SUPPORT
#define F15_TN_HTC_SUPPORT {AMD_FAMILY_15_TN, &F15TnHtcSupport},
#endif
#endif
#endif
// Family 16h
#ifdef OPTION_FAMILY16H
#if OPTION_FAMILY16H == TRUE
#if OPTION_FAMILY16H_KB == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHtc;
#undef OPTION_CPU_HTC_FEAT
#define OPTION_CPU_HTC_FEAT &CpuFeatureHtc,
extern CONST HTC_FAMILY_SERVICES ROMDATA F16KbHtcSupport;
#undef F16_KB_HTC_SUPPORT
#define F16_KB_HTC_SUPPORT {AMD_FAMILY_16_KB, &F16KbHtcSupport},
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HtcFamilyServiceArray[] =
{
F15_TN_HTC_SUPPORT
F16_KB_HTC_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HtcFamilyServiceTable =
{
(sizeof (HtcFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&HtcFamilyServiceArray[0]
};
#endif // _OPTION_HTC_INSTALL_H_

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src/vendorcode/amd/agesa/f16kb/Config/OptionIdsInstall.h
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@ -1,499 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* IDS Option Install File
*
* This file generates the defaults tables for family 10h model 5 processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_IDS_INSTALL_H_
#define _OPTION_IDS_INSTALL_H_
#include "Ids.h"
#include "IdsHt.h"
#include "IdsLib.h"
#include "IdsDebugPrint.h"
#ifdef __IDS_EXTENDED__
#include OPTION_IDS_EXT_INSTALL_FILE
#endif
#define IDS_LATE_RUN_AP_TASK
#define M_HTIDS_PORT_OVERRIDE_HOOK (PF_HtIdsGetPortOverride)CommonVoid
#if (IDSOPT_IDS_ENABLED == TRUE)
#if (IDSOPT_CONTROL_ENABLED == TRUE)
// Check for all families which include HT Features.To add new family support replace FALSE
#if (FALSE) && (AGESA_ENTRY_INIT_POST == TRUE)
#undef M_HTIDS_PORT_OVERRIDE_HOOK
#define M_HTIDS_PORT_OVERRIDE_HOOK HtIdsGetPortOverride
#endif
#endif
#endif // OPTION_IDS_LEVEL
CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVERRIDE_HOOK;
#if (IDSOPT_IDS_ENABLED == TRUE)
#if (AGESA_ENTRY_INIT_LATE == TRUE)
#undef IDS_LATE_RUN_AP_TASK
#define IDS_LATE_RUN_AP_TASK {IDS_LATE_RUN_AP_TASK_ID, (IMAGE_ENTRY)AmdIdsRunApTaskLate},
#endif
#endif // OPTION_IDS_LEVEL
#if (IDSOPT_TRACING_ENABLED == TRUE)
#if (AGESA_ENTRY_INIT_POST == TRUE)
#include <mu.h>
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
{ (UINTN) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"},
{ (UINTN) MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"},
{ (UINTN) MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"}
};
#else
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
{ (UINTN) CommonReturnFalse, "DefRet()"},
{ (UINTN) CommonReturnFalse, "DefRet()"},
{ (UINTN) CommonReturnFalse, "DefRet()"}
};
#endif
#else
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
{ (UINTN) CommonReturnFalse, "DefRet()"},
{ (UINTN) CommonReturnFalse, "DefRet()"},
{ (UINTN) CommonReturnFalse, "DefRet()"}
};
#endif
#define NV_TO_CMOS(Len, NV_ID) {Len, NV_ID},
#define OPTION_IDS_NV_TO_CMOS_END NV_TO_CMOS (IDS_NV_TO_CMOS_LEN_END, IDS_NV_TO_CMOS_ID_END)
#if (IDSOPT_IDS_ENABLED == TRUE)
#if ((IDSOPT_CONTROL_ENABLED == TRUE) && \
((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || \
(AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || \
(AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)))
#if (IDSOPT_CONTROL_NV_TO_CMOS == TRUE)
#define OPTION_IDS_NV_TO_CMOS_COMMON
//Family 15h TN
#ifdef OPTION_FAMILY15H_TN
#if OPTION_FAMILY15H_TN == TRUE
#define OPTION_IDS_NV_TO_CMOS_F15_TN\
{IDS_NV_TO_CMOS_LEN_BYTE, AGESA_IDS_NV_UCODE},
#endif
#endif
#ifndef OPTION_IDS_NV_TO_CMOS_F15_TN
#define OPTION_IDS_NV_TO_CMOS_F15_TN
#endif
//Family 16h KB
#ifdef OPTION_FAMILY16H_KB
#if OPTION_FAMILY16H_KB == TRUE
#define OPTION_IDS_NV_TO_CMOS_F16_KB\
{IDS_NV_TO_CMOS_LEN_BYTE, AGESA_IDS_NV_UCODE},
#endif
#endif
#ifndef OPTION_IDS_NV_TO_CMOS_F16_KB
#define OPTION_IDS_NV_TO_CMOS_F16_KB
#endif
#ifndef OPTION_IDS_NV_TO_CMOS_EXTEND
#define OPTION_IDS_NV_TO_CMOS_EXTEND
#endif
IDS_NV_TO_CMOS gIdsNVToCmos[] = {
OPTION_IDS_NV_TO_CMOS_COMMON
OPTION_IDS_NV_TO_CMOS_F15_TN
OPTION_IDS_NV_TO_CMOS_F16_KB
OPTION_IDS_NV_TO_CMOS_EXTEND
OPTION_IDS_NV_TO_CMOS_END
};
#else
IDS_NV_TO_CMOS gIdsNVToCmos[] = {
OPTION_IDS_NV_TO_CMOS_END
};
#endif
#else
IDS_NV_TO_CMOS gIdsNVToCmos[] = {
OPTION_IDS_NV_TO_CMOS_END
};
#endif
#else
IDS_NV_TO_CMOS gIdsNVToCmos[] = {
OPTION_IDS_NV_TO_CMOS_END
};
#endif
///Ids Feat Options
#if ((IDSOPT_IDS_ENABLED == TRUE) && \
((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || \
(AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || \
(AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)))
#if (IDSOPT_CONTROL_ENABLED == TRUE)
#ifndef OPTION_IDS_EXTEND_FEATS
#define OPTION_IDS_EXTEND_FEATS
#endif
#define OPTION_IDS_FEAT_ECCCTRL
#define OPTION_IDS_FEAT_GNB_PLATFORMCFG\
OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN \
OPTION_IDS_FEAT_GNB_PLATFORMCFGF16KB
#define OPTION_IDS_FEAT_CPB_CTRL
#define OPTION_IDS_FEAT_HTC_CTRL\
OPTION_IDS_FEAT_HTC_CTRL_F15_TN \
OPTION_IDS_FEAT_HTC_CTRL_F16_KB
#define OPTION_IDS_FEAT_MEMORY_MAPPING\
OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN \
OPTION_IDS_FEAT_MEMORY_MAPPING_F16_KB
#define OPTION_IDS_FEAT_HT_ASSIST
/*----------------------------------------------------------------------------
* Family 15 TN feat blocks
*
*----------------------------------------------------------------------------
*/
#define OPTION_IDS_FEAT_HTC_CTRL_F15_TN
#define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN
#ifdef OPTION_FAMILY15H_TN
#if OPTION_FAMILY15H_TN == TRUE
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15Tn;
#undef OPTION_IDS_FEAT_HTC_CTRL_F15_TN
#define OPTION_IDS_FEAT_HTC_CTRL_F15_TN\
&IdsFeatHtcControlBlockF15Tn,
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15Tn;
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15Tn;
#undef OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN
#define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN\
&IdsFeatMemoryMappingPostBeforeBlockF15Tn,\
&IdsFeatMemoryMappingChIntlvBlockF15Tn,
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF15Tn;
#undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN &IdsFeatGnbPlatformCfgBlockF15Tn,
#endif
#endif
/*----------------------------------------------------------------------------
* Family 16 KB feat blocks
*
*----------------------------------------------------------------------------
*/
#define OPTION_IDS_FEAT_HTC_CTRL_F16_KB
#define OPTION_IDS_FEAT_MEMORY_MAPPING_F16_KB
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF16KB
#ifdef OPTION_FAMILY16H_KB
#if OPTION_FAMILY16H_KB == TRUE
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF16Kb;
#undef OPTION_IDS_FEAT_HTC_CTRL_F16_KB
#define OPTION_IDS_FEAT_HTC_CTRL_F16_KB\
&IdsFeatHtcControlBlockF16Kb,
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF16Kb;
#undef OPTION_IDS_FEAT_MEMORY_MAPPING_F16_KB
#define OPTION_IDS_FEAT_MEMORY_MAPPING_F16_KB\
&IdsFeatMemoryMappingPostBeforeBlockF16Kb,
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF16Kb;
#undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF16KB
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF16KB &IdsFeatGnbPlatformCfgBlockF16Kb,
#endif
#endif
#define OPTION_IDS_FEAT_NV_TO_CMOS
#if IDSOPT_CONTROL_NV_TO_CMOS == TRUE
#undef OPTION_IDS_FEAT_NV_TO_CMOS
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatNvToCmosSaveBlock;
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatNvToCmosRestoreBlock;
#define OPTION_IDS_FEAT_NV_TO_CMOS\
&IdsFeatNvToCmosSaveBlock, \
&IdsFeatNvToCmosRestoreBlock,
#endif
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatUcodeBlock =
{
IDS_FEAT_UCODE_UPDATE,
IDS_ALL_CORES,
IDS_UCODE,
IDS_FAMILY_ALL,
IdsSubUCode
};
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatPowerPolicyBlock =
{
IDS_FEAT_POWER_POLICY,
IDS_ALL_CORES,
IDS_PLATFORMCFG_OVERRIDE,
IDS_FAMILY_ALL,
IdsSubPowerPolicyOverride
};
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatTargetPstateBlock =
{
IDS_FEAT_TARGET_PSTATE,
IDS_BSP_ONLY,
IDS_INIT_LATE_AFTER,
IDS_FAMILY_ALL,
IdsSubTargetPstate
};
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatPostPstateBlock =
{
IDS_FEAT_POSTPSTATE,
IDS_ALL_CORES,
IDS_CPU_Early_Override,
IDS_FAMILY_ALL,
IdsSubPostPState
};
//Dram controller Features
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctAllMemClkBlock =
{
IDS_FEAT_DCT_ALLMEMCLK,
IDS_BSP_ONLY,
IDS_ALL_MEMORY_CLOCK,
IDS_FAMILY_ALL,
IdsSubAllMemClkEn
};
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctGangModeBlock =
{
IDS_FEAT_DCT_GANGMODE,
IDS_BSP_ONLY,
IDS_GANGING_MODE,
IDS_FAMILY_ALL,
IdsSubGangingMode
};
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownCtrlBlock =
{
IDS_FEAT_DCT_POWERDOWN,
IDS_BSP_ONLY,
IDS_INIT_POST_BEFORE,
IDS_FAMILY_ALL,
IdsSubPowerDownCtrl
};
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownModeBlock =
{
IDS_FEAT_DCT_POWERDOWN,
IDS_BSP_ONLY,
IDS_POWERDOWN_MODE,
IDS_FAMILY_ALL,
IdsSubPowerDownMode
};
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHdtOutBlock =
{
IDS_FEAT_HDTOUT,
IDS_BSP_ONLY,
IDS_INIT_EARLY_BEFORE,
IDS_FAMILY_ALL,
IdsSubHdtOut
};
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtSettingBlock =
{
IDS_FEAT_HT_SETTING,
IDS_BSP_ONLY,
IDS_HT_CONTROL,
IDS_FAMILY_ALL,
IdsSubHtLinkControl
};
CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsControlFeats[] =
{
&IdsFeatUcodeBlock,
&IdsFeatPowerPolicyBlock,
&IdsFeatTargetPstateBlock,
&IdsFeatPostPstateBlock,
OPTION_IDS_FEAT_NV_TO_CMOS
OPTION_IDS_FEAT_ECCCTRL
&IdsFeatDctAllMemClkBlock,
&IdsFeatDctGangModeBlock,
&IdsFeatDctPowerDownCtrlBlock,
&IdsFeatDctPowerDownModeBlock,
&IdsFeatDctPowerDownModeBlock,
OPTION_IDS_FEAT_HT_ASSIST
&IdsFeatHdtOutBlock,
&IdsFeatHtSettingBlock,
OPTION_IDS_FEAT_GNB_PLATFORMCFG
OPTION_IDS_FEAT_CPB_CTRL
OPTION_IDS_FEAT_HTC_CTRL
OPTION_IDS_FEAT_MEMORY_MAPPING
OPTION_IDS_EXTEND_FEATS
NULL
};
#else
CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsControlFeats[] =
{
NULL
};
#endif//IDSOPT_CONTROL_ENABLED
#define OPTION_IDS_FAM_REGACC_F15TN
#ifdef OPTION_FAMILY15H_TN
#if OPTION_FAMILY15H_TN == TRUE
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatRegGmmxF15Tn;
#undef OPTION_IDS_FAM_REGACC_F15TN
#define OPTION_IDS_FAM_REGACC_F15TN \
&IdsFeatRegGmmxF15Tn,
#endif
#endif
#define OPTION_IDS_FAM_REGACC_F16KB
#ifdef OPTION_FAMILY16H_KB
#if OPTION_FAMILY16H_KB == TRUE
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatRegGmmxF16Kb;
#undef OPTION_IDS_FAM_REGACC_F16KB
#define OPTION_IDS_FAM_REGACC_F16KB \
&IdsFeatRegGmmxF16Kb,
#endif
#endif
CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsRegAccessTbl[] =
{
OPTION_IDS_FAM_REGACC_F15TN
OPTION_IDS_FAM_REGACC_F16KB
NULL
};
/*----------------------------------------------------------------------------
* IDS TRACING SERVICES
*
*----------------------------------------------------------------------------
*/
#if IDSOPT_TRACING_ENABLED == TRUE
#define IDS_TRACING_CONSOLE_HDTOUT
#define IDS_TRACING_CONSOLE_SERIALPORT
#define IDS_TRACING_CONSOLE_REDIRECT_IO
#define IDS_TRACING_CONSOLE_RAM
#ifdef IDSOPT_TRACING_CONSOLE_HDTOUT
#if IDSOPT_TRACING_CONSOLE_HDTOUT == TRUE
#undef IDS_TRACING_CONSOLE_HDTOUT
extern CONST IDS_DEBUG_PRINT ROMDATA IdsDebugPrintHdtoutInstance;
#define IDS_TRACING_CONSOLE_HDTOUT &IdsDebugPrintHdtoutInstance,
#endif
#endif
#ifdef IDSOPT_TRACING_CONSOLE_SERIALPORT
#if IDSOPT_TRACING_CONSOLE_SERIALPORT == TRUE
#undef IDS_TRACING_CONSOLE_SERIALPORT
extern CONST IDS_DEBUG_PRINT ROMDATA IdsDebugPrintSerialInstance;
#define IDS_TRACING_CONSOLE_SERIALPORT &IdsDebugPrintSerialInstance,
#endif
#endif
#ifdef IDSOPT_TRACING_CONSOLE_REDIRECT_IO
#if IDSOPT_TRACING_CONSOLE_REDIRECT_IO == TRUE
#undef IDS_TRACING_CONSOLE_REDIRECT_IO
extern CONST IDS_DEBUG_PRINT ROMDATA IdsDebugPrintRedirectIoInstance;
#define IDS_TRACING_CONSOLE_REDIRECT_IO &IdsDebugPrintRedirectIoInstance,
#endif
#endif
#ifdef IDSOPT_TRACING_CONSOLE_RAM
#if IDSOPT_TRACING_CONSOLE_RAM == TRUE
#undef IDS_TRACING_CONSOLE_RAM
extern CONST IDS_DEBUG_PRINT ROMDATA IdsDebugPrintRamInstance;
#define IDS_TRACING_CONSOLE_RAM &IdsDebugPrintRamInstance,
#endif
#endif
CONST IDS_DEBUG_PRINT* ROMDATA IdsDebugPrint[] =
{
IDS_TRACING_CONSOLE_SERIALPORT
IDS_TRACING_CONSOLE_HDTOUT
IDS_TRACING_CONSOLE_REDIRECT_IO
IDS_TRACING_CONSOLE_RAM
NULL
};
#else
CONST IDS_DEBUG_PRINT* ROMDATA IdsDebugPrint[] =
{
NULL
};
#endif
#else
CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsControlFeats[] =
{
NULL
};
CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsRegAccessTbl[] =
{
NULL
};
CONST IDS_DEBUG_PRINT* ROMDATA IdsDebugPrint[] =
{
NULL
};
#endif// IDSOPT_IDS_ENABLED
#endif

103
src/vendorcode/amd/agesa/f16kb/Config/OptionIoCstateInstall.h
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@ -1,103 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: IO C-state
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_IO_CSTATE_INSTALL_H_
#define _OPTION_IO_CSTATE_INSTALL_H_
#include "cpuIoCstate.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_IO_CSTATE_FEAT
#define F15_TN_IO_CSTATE_SUPPORT
#define F16_KB_IO_CSTATE_SUPPORT
#if OPTION_IO_CSTATE == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if OPTION_FAMILY15H_TN == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
#undef OPTION_IO_CSTATE_FEAT
#define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15TnIoCstateSupport;
#undef F15_TN_IO_CSTATE_SUPPORT
#define F15_TN_IO_CSTATE_SUPPORT {AMD_FAMILY_15_TN, &F15TnIoCstateSupport},
#endif
#endif
#endif
#ifdef OPTION_FAMILY16H
#if OPTION_FAMILY16H == TRUE
#if OPTION_FAMILY16H_KB == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
#undef OPTION_IO_CSTATE_FEAT
#define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F16KbIoCstateSupport;
#undef F16_KB_IO_CSTATE_SUPPORT
#define F16_KB_IO_CSTATE_SUPPORT {AMD_FAMILY_16_KB, &F16KbIoCstateSupport},
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA IoCstateFamilyServiceArray[] =
{
F15_TN_IO_CSTATE_SUPPORT
F16_KB_IO_CSTATE_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA IoCstateFamilyServiceTable =
{
(sizeof (IoCstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&IoCstateFamilyServiceArray[0]
};
#endif // _OPTION_IO_CSTATE_INSTALL_H_

77
src/vendorcode/amd/agesa/f16kb/Config/OptionL3FeaturesInstall.h
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@ -1,77 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: L3 Dependent Features
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_L3_FEATURES_INSTALL_H_
#define _OPTION_L3_FEATURES_INSTALL_H_
#include "cpuL3Features.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_L3_FEAT
#define L3_FEAT_AP_DISABLE_CACHE
#define L3_FEAT_AP_ENABLE_CACHE
#if (OPTION_HT_ASSIST == TRUE || OPTION_ATM_MODE == TRUE || OPTION_NBR_CACHE == TRUE)
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
#undef L3_FEAT_AP_DISABLE_CACHE
#define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches},
#undef L3_FEAT_AP_ENABLE_CACHE
#define L3_FEAT_AP_ENABLE_CACHE {AP_LATE_TASK_ENABLE_CACHE, (IMAGE_ENTRY) EnableAllCaches},
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA L3FeatureFamilyServiceArray[] =
{
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA L3FeatureFamilyServiceTable =
{
(sizeof (L3FeatureFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&L3FeatureFamilyServiceArray[0]
};
#endif // _OPTION_L3_FEATURES_INSTALL_H_

55
src/vendorcode/amd/agesa/f16kb/Config/OptionLowPwrPstateInstall.h
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@ -1,55 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Low Power Pstate for PROCHOT_L Throttling.
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_LOW_PWR_PSTATE_INSTALL_H_
#define _OPTION_LOW_PWR_PSTATE_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT
#define F15_OR_LOW_PWR_PSTATE_SUPPORT
#endif // _OPTION_LOW_PWR_PSTATE_INSTALL_H_

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src/vendorcode/amd/agesa/f16kb/Config/OptionMemoryInstall.h
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93
src/vendorcode/amd/agesa/f16kb/Config/OptionMmioMapInstall.h
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@ -1,93 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: MMIO map manager
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_MMIO_MAP_INSTALL_H_
#define _OPTION_MMIO_MAP_INSTALL_H_
#include "mmioMapManager.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define F15_MMIO_MAP_SUPPORT
#define F16_MMIO_MAP_SUPPORT
#if ((AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
// Family 15h
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
extern CONST MMIO_MAP_FAMILY_SERVICES ROMDATA F15MmioMapSupport;
#undef F15_MMIO_MAP_SUPPORT
#define F15_MMIO_MAP_SUPPORT {AMD_FAMILY_15, &F15MmioMapSupport},
#endif
#endif
// Family 16h
#ifdef OPTION_FAMILY16H
#if OPTION_FAMILY16H == TRUE
extern CONST MMIO_MAP_FAMILY_SERVICES ROMDATA F16MmioMapSupport;
#undef F16_MMIO_MAP_SUPPORT
#define F16_MMIO_MAP_SUPPORT {AMD_FAMILY_16, &F16MmioMapSupport},
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MmioMapFamilyServiceArray[] =
{
F15_MMIO_MAP_SUPPORT
F16_MMIO_MAP_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MmioMapFamilyServiceTable =
{
(sizeof (MmioMapFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&MmioMapFamilyServiceArray[0]
};
#endif // _OPTION_MMIO_MAP_INSTALL_H_

70
src/vendorcode/amd/agesa/f16kb/Config/OptionMsgBasedC1eInstall.h
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@ -1,70 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Message-Based C1e
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_MSG_BASED_C1E_INSTALL_H_
#define _OPTION_MSG_BASED_C1E_INSTALL_H_
#include "cpuMsgBasedC1e.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_MSG_BASED_C1E_FEAT
#define F15_BK_MSG_BASED_C1E_SUPPORT
#if OPTION_MSG_BASED_C1E == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MsgBasedC1eFamilyServiceArray[] =
{
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MsgBasedC1eFamilyServiceTable =
{
(sizeof (MsgBasedC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&MsgBasedC1eFamilyServiceArray[0]
};
#endif
#endif
#endif // _OPTION_MSG_BASED_C1E_INSTALL_H_

104
src/vendorcode/amd/agesa/f16kb/Config/OptionMultiSocketInstall.h
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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Multiple Socket Support
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_MULTISOCKET_INSTALL_H_
#define _OPTION_MULTISOCKET_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#ifndef OPTION_MULTISOCKET
#error BLDOPT: Option not defined: "OPTION_MULTISOCKET"
#endif
#if OPTION_MULTISOCKET == TRUE
OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrMulti;
#define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrMulti
OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sMulti;
#define CORE0_PM_TASK RunCodeOnAllSystemCore0sMulti
OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofMulti;
#define GET_SYS_NB_COF GetSystemNbCofMulti
OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti;
#define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti
OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsMulti;
#define GET_EARLY_PM_ERRORS GetEarlyPmErrorsMulti
OPTION_MULTISOCKET_PM_NB_MIN_COF GetMinNbCofMulti;
#define GET_MIN_NB_COF GetMinNbCofMulti
OPTION_MULTISOCKET_GET_PCI_ADDRESS GetCurrPciAddrMulti;
#define GET_PCI_ADDRESS GetCurrPciAddrMulti
OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciMulti;
#define MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciMulti
#else
OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrSingle;
#define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrSingle
OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sSingle;
#define CORE0_PM_TASK RunCodeOnAllSystemCore0sSingle
OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofSingle;
#define GET_SYS_NB_COF GetSystemNbCofSingle
OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle;
#define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle
OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsSingle;
#define GET_EARLY_PM_ERRORS GetEarlyPmErrorsSingle
OPTION_MULTISOCKET_PM_NB_MIN_COF GetMinNbCofSingle;
#define GET_MIN_NB_COF GetMinNbCofSingle
OPTION_MULTISOCKET_GET_PCI_ADDRESS GetCurrPciAddrSingle;
#define GET_PCI_ADDRESS GetCurrPciAddrSingle
OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciSingle;
#define MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciSingle
#endif
/* Declare the instance of the multisocket option configuration structure */
CONST OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration = {
MULTISOCKET_STRUCT_VERSION,
GET_NUM_PM_STEPS,
CORE0_PM_TASK,
GET_SYS_NB_COF,
GET_SYS_NB_COF_UPDATE,
GET_EARLY_PM_ERRORS,
GET_MIN_NB_COF,
GET_PCI_ADDRESS,
MODIFY_CURR_SOCKET_PCI
};
#endif // _OPTION_MULTISOCKET_INSTALL_H_

105
src/vendorcode/amd/agesa/f16kb/Config/OptionPrefetchModeInstall.h
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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Prefetch Mode
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_PREFETCH_MODE_INSTALL_H_
#define _OPTION_PREFETCH_MODE_INSTALL_H_
#include "cpuPrefetchMode.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_PREFETCH_MODE_FEAT
#define CPU_PREFETCH_MODE_AP_TASK
#define F15_PREFETCH_MODE_SUPPORT
#define F16_PREFETCH_MODE_SUPPORT
#if OPTION_PREFETCH_MODE == TRUE
#if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
#undef CPU_PREFETCH_MODE_AP_TASK
#define CPU_PREFETCH_MODE_AP_TASK {AP_LATE_TASK_CPU_PREFETCH_MODE, (IMAGE_ENTRY) CpuPrefetchModeApTask},
// Family 15h
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePrefetchMode;
#undef OPTION_PREFETCH_MODE_FEAT
#define OPTION_PREFETCH_MODE_FEAT &CpuFeaturePrefetchMode,
extern CONST PREFETCH_MODE_FAMILY_SERVICES ROMDATA F15PrefetchModeSupport;
#undef F15_PREFETCH_MODE_SUPPORT
#define F15_PREFETCH_MODE_SUPPORT {AMD_FAMILY_15, &F15PrefetchModeSupport},
#endif
#endif
///@todo
// Family 16h
//#ifdef OPTION_FAMILY16H
// #if OPTION_FAMILY16H == TRUE
// extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePrefetchMode;
// #undef OPTION_PREFETCH_MODE_FEAT
// #define OPTION_PREFETCH_MODE_FEAT &CpuFeaturePrefetchMode,
// extern CONST PREFETCH_MODE_FAMILY_SERVICES ROMDATA F16PrefetchModeSupport;
// #undef F16_PREFETCH_MODE_SUPPORT
// #define F16_PREFETCH_MODE_SUPPORT {AMD_FAMILY_16, &F16PrefetchModeSupport},
// #endif
//#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PrefetchModeFamilyServiceArray[] =
{
F15_PREFETCH_MODE_SUPPORT
F16_PREFETCH_MODE_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PrefetchModeFamilyServiceTable =
{
(sizeof (PrefetchModeFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&PrefetchModeFamilyServiceArray[0]
};
#endif // _OPTION_PREFETCH_MODE_INSTALL_H_

57
src/vendorcode/amd/agesa/f16kb/Config/OptionPreserveMailboxInstall.h
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@ -1,57 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Preserve Mailbox
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_PRESERVE_MAILBOX_INSTALL_H_
#define _OPTION_PRESERVE_MAILBOX_INSTALL_H_
#include "PreserveMailbox.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_PRESERVE_MAILBOX_FEAT
#define F15_PRESERVE_MAILBOX_SUPPORT
#endif // _OPTION_PRESERVE_MAILBOX_INSTALL_H_

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src/vendorcode/amd/agesa/f16kb/Config/OptionPsiInstall.h
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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Power Status Indicator (PSI).
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_PSI_INSTALL_H_
#define _OPTION_PSI_INSTALL_H_
#include "cpuPsi.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPU_PSI_FEAT
#define F15_TN_PSI_SUPPORT
#define F16_KB_PSI_SUPPORT
#if OPTION_CPU_PSI == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
// Family 15h
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if OPTION_FAMILY15H_TN == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePsi;
#undef OPTION_CPU_PSI_FEAT
#define OPTION_CPU_PSI_FEAT &CpuFeaturePsi,
extern CONST PSI_FAMILY_SERVICES ROMDATA F15TnPsiSupport;
#undef F15_TN_PSI_SUPPORT
#define F15_TN_PSI_SUPPORT {AMD_FAMILY_15_TN, &F15TnPsiSupport},
#endif
#endif
#endif
// Family 16h
#ifdef OPTION_FAMILY16H
#if OPTION_FAMILY16H == TRUE
#if OPTION_FAMILY16H_KB == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePsi;
#undef OPTION_CPU_PSI_FEAT
#define OPTION_CPU_PSI_FEAT &CpuFeaturePsi,
extern CONST PSI_FAMILY_SERVICES ROMDATA F16KbPsiSupport;
#undef F16_KB_PSI_SUPPORT
#define F16_KB_PSI_SUPPORT {AMD_FAMILY_16_KB, &F16KbPsiSupport},
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PsiFamilyServiceArray[] =
{
F15_TN_PSI_SUPPORT
F16_KB_PSI_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PsiFamilyServiceTable =
{
(sizeof (PsiFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&PsiFamilyServiceArray[0]
};
#endif // _OPTION_PSI_INSTALL_H_

57
src/vendorcode/amd/agesa/f16kb/Config/OptionPstateHpcModeInstall.h
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@ -1,57 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Pstate HPC mode.
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_PSTATE_HPC_MODE_INSTALL_H_
#define _OPTION_PSTATE_HPC_MODE_INSTALL_H_
#include "cpuPstateHpcMode.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPU_PSTATE_HPC_MODE_FEAT
#define F15_PSTATE_HPC_MODE_SUPPORT
#endif // _OPTION_PSTATE_HPC_MODE_INSTALL_H_

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src/vendorcode/amd/agesa/f16kb/Config/OptionPstateInstall.h
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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: PState
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_PSTATE_INSTALL_H_
#define _OPTION_PSTATE_INSTALL_H_
#include "cpuPstateTables.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define F15_TN_PSTATE_SERVICE_SUPPORT
#define F16_KB_PSTATE_SERVICE_SUPPORT
#if ((AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
//
//Define Pstate CPU Family service
//
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#ifdef OPTION_FAMILY15H_TN
#if OPTION_FAMILY15H_TN == TRUE
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15TnPstateServices;
#undef F15_TN_PSTATE_SERVICE_SUPPORT
#define F15_TN_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15_TN, &F15TnPstateServices},
#endif
#endif
#endif
#endif
#ifdef OPTION_FAMILY16H
#if OPTION_FAMILY16H == TRUE
#ifdef OPTION_FAMILY16H_KB
#if OPTION_FAMILY16H_KB == TRUE
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F16KbPstateServices;
#undef F16_KB_PSTATE_SERVICE_SUPPORT
#define F16_KB_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_16_KB, &F16KbPstateServices},
#endif
#endif
#endif
#endif
//
//Define ACPI Pstate objects.
//
#ifndef OPTION_ACPI_PSTATES
#error BLDOPT: Option not defined: "OPTION_ACPI_PSTATES"
#endif
#if (OPTION_ACPI_PSTATES == TRUE)
OPTION_SSDT_FEATURE GenerateSsdt;
#define USER_SSDT_MAIN GenerateSsdt
#ifndef OPTION_MULTISOCKET
#error BLDOPT: Option not defined: "OPTION_MULTISOCKET"
#endif
OPTION_ACPI_FEATURE CreatePStateAcpiTables;
OPTION_PSTATE_GATHER PStateGatherMain;
#if ((OPTION_MULTISOCKET == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE))
OPTION_PSTATE_LEVELING PStateLevelingMain;
#define USER_PSTATE_OPTION_LEVEL PStateLevelingMain
#else
OPTION_PSTATE_LEVELING PStateLevelingStub;
#define USER_PSTATE_OPTION_LEVEL PStateLevelingStub
#endif
#if AGESA_ENTRY_INIT_LATE == TRUE
#define USER_PSTATE_OPTION_MAIN CreatePStateAcpiTables
#else
OPTION_ACPI_FEATURE CreateAcpiTablesStub;
#define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub
#endif
#if AGESA_ENTRY_INIT_POST == TRUE
#define USER_PSTATE_OPTION_GATHER PStateGatherMain
#else
OPTION_PSTATE_GATHER PStateGatherStub;
#define USER_PSTATE_OPTION_GATHER PStateGatherStub
#endif
#if CFG_ACPI_PSTATES_PPC == TRUE
#define USER_PSTATE_CFG_PPC TRUE
#else
#define USER_PSTATE_CFG_PPC FALSE
#endif
#if CFG_ACPI_PSTATES_PCT == TRUE
#define USER_PSTATE_CFG_PCT TRUE
#else
#define USER_PSTATE_CFG_PCT FALSE
#endif
#if CFG_ACPI_PSTATES_PSD == TRUE
#define USER_PSTATE_CFG_PSD TRUE
#else
#define USER_PSTATE_CFG_PSD FALSE
#endif
#if CFG_ACPI_PSTATES_PSS == TRUE
#define USER_PSTATE_CFG_PSS TRUE
#else
#define USER_PSTATE_CFG_PSS FALSE
#endif
#if CFG_ACPI_PSTATES_XPSS == TRUE
#define USER_PSTATE_CFG_XPSS TRUE
#else
#define USER_PSTATE_CFG_XPSS FALSE
#endif
#if OPTION_IO_CSTATE == TRUE
OPTION_ACPI_FEATURE CreateCStateAcpiTables;
#define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables
#else
OPTION_ACPI_FEATURE CreateAcpiTablesStub;
#define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub
#endif
#else
OPTION_SSDT_FEATURE GenerateSsdtStub;
OPTION_ACPI_FEATURE CreateAcpiTablesStub;
OPTION_PSTATE_GATHER PStateGatherStub;
OPTION_PSTATE_LEVELING PStateLevelingStub;
#define USER_SSDT_MAIN GenerateSsdtStub
#define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub
#define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub
#define USER_PSTATE_OPTION_GATHER PStateGatherStub
#define USER_PSTATE_OPTION_LEVEL PStateLevelingStub
#define USER_PSTATE_CFG_PPC FALSE
#define USER_PSTATE_CFG_PCT FALSE
#define USER_PSTATE_CFG_PSD FALSE
#define USER_PSTATE_CFG_PSS FALSE
#define USER_PSTATE_CFG_XPSS FALSE
// If ACPI Objects are disabled for PStates, we still need to check
// whether ACPI Objects are enabled for CStates
#if OPTION_IO_CSTATE == TRUE
OPTION_SSDT_FEATURE GenerateSsdt;
OPTION_PSTATE_GATHER PStateGatherMain;
OPTION_ACPI_FEATURE CreateCStateAcpiTables;
#undef USER_SSDT_MAIN
#define USER_SSDT_MAIN GenerateSsdt
#undef USER_PSTATE_OPTION_GATHER
#define USER_PSTATE_OPTION_GATHER PStateGatherMain
#undef USER_CSTATE_OPTION_MAIN
#define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables
#endif
#endif
#else
OPTION_SSDT_FEATURE GenerateSsdtStub;
OPTION_ACPI_FEATURE CreateAcpiTablesStub;
OPTION_PSTATE_GATHER PStateGatherStub;
OPTION_PSTATE_LEVELING PStateLevelingStub;
#define USER_SSDT_MAIN GenerateSsdtStub
#define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub
#define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub
#define USER_PSTATE_OPTION_GATHER PStateGatherStub
#define USER_PSTATE_OPTION_LEVEL PStateLevelingStub
#define USER_PSTATE_CFG_PPC FALSE
#define USER_PSTATE_CFG_PCT FALSE
#define USER_PSTATE_CFG_PSD FALSE
#define USER_PSTATE_CFG_PSS FALSE
#define USER_PSTATE_CFG_XPSS FALSE
#endif
/* Declare the instance of the PSTATE option configuration structure */
CONST OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration = {
PSTATE_STRUCT_VERSION,
USER_PSTATE_OPTION_GATHER,
USER_PSTATE_OPTION_LEVEL
};
CONST OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration = {
PSTATE_STRUCT_VERSION,
USER_SSDT_MAIN,
USER_PSTATE_OPTION_MAIN,
USER_CSTATE_OPTION_MAIN,
USER_PSTATE_CFG_PPC,
USER_PSTATE_CFG_PCT,
USER_PSTATE_CFG_PSD,
USER_PSTATE_CFG_PSS,
USER_PSTATE_CFG_XPSS,
{CFG_ACPI_SET_OEM_ID},
{CFG_ACPI_SET_OEM_TABLE_ID}
};
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateCpuFamilyServiceArray[] =
{
F15_TN_PSTATE_SERVICE_SUPPORT
F16_KB_PSTATE_SERVICE_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateFamilyServiceTable =
{
(sizeof (PstateCpuFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&PstateCpuFamilyServiceArray[0]
};
#endif // _OPTION_PSTATE_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: S3SCRIPT
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_S3SCRIPT_INSTALL_H_
#define _OPTION_S3SCRIPT_INSTALL_H_
#include "S3SaveState.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#ifndef OPTION_S3SCRIPT
#define OPTION_S3SCRIPT FALSE //if not define assume PI not use script
#endif
#if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE)
#if OPTION_S3SCRIPT == TRUE
#define P_S3_SCRIPT_INIT S3ScriptInitState
#endif
#endif
#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
#if OPTION_S3SCRIPT == TRUE
#define P_S3_SCRIPT_RESTORE S3ScriptRestoreState
#endif
#endif
#ifndef P_S3_SCRIPT_INIT
#define P_S3_SCRIPT_INIT S3ScriptInitStateStub
#endif
#ifndef P_S3_SCRIPT_RESTORE
#define P_S3_SCRIPT_RESTORE S3ScriptInitStateStub
#undef GNB_S3_DISPATCH_FUNCTION_TABLE
#endif
#ifndef GNB_S3_DISPATCH_FUNCTION_TABLE
#define GNB_S3_DISPATCH_FUNCTION_TABLE
#endif
/* Declare the instance of the S3SCRIPT option configuration structure */
S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration = {
P_S3_SCRIPT_INIT,
P_S3_SCRIPT_RESTORE
};
S3_DISPATCH_FUNCTION_ENTRY S3DispatchFunctionTable [] = {
GNB_S3_DISPATCH_FUNCTION_TABLE
{0, NULL}
};
#endif // _OPTION_S3SCRIPT_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: SLIT
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_SLIT_INSTALL_H_
#define _OPTION_SLIT_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#if AGESA_ENTRY_INIT_LATE == TRUE
#ifndef OPTION_SLIT
#error BLDOPT: Option not defined: "OPTION_SLIT"
#endif
#if OPTION_SLIT == TRUE
OPTION_SLIT_FEATURE GetAcpiSlitMain;
OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBuffer;
#define USER_SLIT_OPTION GetAcpiSlitMain
#define USER_SLIT_RELEASE_BUFFER ReleaseSlitBuffer
#else
OPTION_SLIT_FEATURE GetAcpiSlitStub;
OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub;
#define USER_SLIT_OPTION GetAcpiSlitStub
#define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub
#endif
#else
OPTION_SLIT_FEATURE GetAcpiSlitStub;
OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub;
#define USER_SLIT_OPTION GetAcpiSlitStub
#define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub
#endif
/* Declare the instance of the SLIT option configuration structure */
OPTION_SLIT_CONFIGURATION OptionSlitConfiguration = {
SLIT_STRUCT_VERSION,
USER_SLIT_OPTION,
USER_SLIT_RELEASE_BUFFER,
{CFG_ACPI_SET_OEM_ID},
{CFG_ACPI_SET_OEM_TABLE_ID}
};
#endif // _OPTION_SLIT_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: SRAT
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_SRAT_INSTALL_H_
#define _OPTION_SRAT_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#if AGESA_ENTRY_INIT_LATE == TRUE
#ifndef OPTION_SRAT
#error BLDOPT: Option not defined: "OPTION_SRAT"
#endif
#if OPTION_SRAT == TRUE
OPTION_SRAT_FEATURE GetAcpiSratMain;
#define USER_SRAT_OPTION GetAcpiSratMain
#else
OPTION_SRAT_FEATURE GetAcpiSratStub;
#define USER_SRAT_OPTION GetAcpiSratStub
#endif
#else
OPTION_SRAT_FEATURE GetAcpiSratStub;
#define USER_SRAT_OPTION GetAcpiSratStub
#endif
/* Declare the instance of the WHEA option configuration structure */
OPTION_SRAT_CONFIGURATION OptionSratConfiguration = {
SRAT_STRUCT_VERSION,
USER_SRAT_OPTION,
{CFG_ACPI_SET_OEM_ID},
{CFG_ACPI_SET_OEM_TABLE_ID}
};
#endif // _OPTION_WHEA_INSTALL_H_

84
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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: TDP Limiting.
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_TDP_LIMITING_INSTALL_H_
#define _OPTION_TDP_LIMITING_INSTALL_H_
#include "cpuTdpLimiting.h"
/* This option is designed to be included into the CPU features install
* file. The CPU features install file will define the options status.
* Check to validate the definition
*/
#define OPTION_TDP_LIMIT_FEAT
#define F15_TDP_LIMIT_SUPPORT
#if OPTION_CPU_TDP_LIMITING == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE)
// Family 15h
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureTdpLimit;
#undef OPTION_TDP_LIMIT_FEAT
#define OPTION_TDP_LIMIT_FEAT &CpuFeatureTdpLimit,
extern CONST TDP_LIMIT_FAMILY_SERVICES ROMDATA F15TdpLimitSupport;
#undef F15_TDP_LIMIT_SUPPORT
#define F15_TDP_LIMIT_SUPPORT {AMD_FAMILY_15, &F15TdpLimitSupport},
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA TdpLimitFamilyServiceArray[] =
{
F15_TDP_LIMIT_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA TdpLimitFamilyServiceTable =
{
(sizeof (TdpLimitFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&TdpLimitFamilyServiceArray[0]
};
#endif // _OPTION_TDP_LIMITING_INSTALL_H_

74
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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: WHEA
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_WHEA_INSTALL_H_
#define _OPTION_WHEA_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#if AGESA_ENTRY_INIT_LATE == TRUE
#ifndef OPTION_WHEA
#error BLDOPT: Option not defined: "OPTION_WHEA"
#endif
#if OPTION_WHEA == TRUE
OPTION_WHEA_FEATURE GetAcpiWheaMain;
#define USER_WHEA_OPTION GetAcpiWheaMain
#else
OPTION_WHEA_FEATURE GetAcpiWheaStub;
#define USER_WHEA_OPTION GetAcpiWheaStub
#endif
#else
OPTION_WHEA_FEATURE GetAcpiWheaStub;
#define USER_WHEA_OPTION GetAcpiWheaStub
#endif
/* Declare the instance of the WHEA option configuration structure */
OPTION_WHEA_CONFIGURATION OptionWheaConfiguration = {
WHEA_STRUCT_VERSION,
USER_WHEA_OPTION
};
#endif // _OPTION_WHEA_INSTALL_H_

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51
src/vendorcode/amd/agesa/f16kb/Dispatcher.h
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/* $NoKeywords:$ */
/**
* @file
*
* AMD Pushhigh Interface
*
* Contains interface to Pushhigh entry
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Legacy
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*/
#ifndef _DISPATCHER_H_
#define _DISPATCHER_H_
// AGESA function prototypes
AGESA_STATUS CALLCONV AmdAgesaDispatcher ( IN OUT VOID *ConfigPtr );
AGESA_STATUS CALLCONV AmdAgesaCallout ( IN UINT32 Func, IN UINTN Data, IN OUT VOID *ConfigPtr );
#endif // _DISPATCHER_H_

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@ -1,166 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Advanced API Interface for HT, Memory and CPU
*
* Contains additional declarations need to use HT, Memory and CPU Advanced interface, such as
* would be required by the basic interface implementations.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Include
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _ADVANCED_API_H_
#define _ADVANCED_API_H_
/*----------------------------------------------------------------------------
* HT FUNCTIONS PROTOTYPE
*
*----------------------------------------------------------------------------
*/
/**
* A constructor for the HyperTransport input structure.
*
* Sets inputs to valid, basic level, defaults.
*
* @param[in] StdHeader Opaque handle to standard config header
* @param[in] AmdHtInterface HT Interface structure to initialize.
*
* @retval AGESA_SUCCESS Constructors are not allowed to fail
*/
AGESA_STATUS
AmdHtInterfaceConstructor (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_INTERFACE *AmdHtInterface
);
/**
* The top level external interface for Hypertransport Initialization.
*
* Create our initial internal state, initialize the coherent fabric,
* initialize the non-coherent chains, and perform any required fabric tuning or
* optimization.
*
* @param[in] StdHeader Opaque handle to standard config header
* @param[in] PlatformConfiguration The platform configuration options.
* @param[in] AmdHtInterface HT Interface structure.
*
* @retval AGESA_SUCCESS Only information events logged.
* @retval AGESA_ALERT Sync Flood or CRC error logged.
* @retval AGESA_WARNING Example: expected capability not found
* @retval AGESA_ERROR logged events indicating some devices may not be available
* @retval AGESA_FATAL Mixed Family or MP capability mismatch
*
*/
AGESA_STATUS
AmdHtInitialize (
IN AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfiguration,
IN AMD_HT_INTERFACE *AmdHtInterface
);
/*----------------------------------------------------------------------------
* HT Recovery FUNCTIONS PROTOTYPE
*
*----------------------------------------------------------------------------
*/
/**
* A constructor for the HyperTransport input structure.
*
*/
AGESA_STATUS
AmdHtResetConstructor (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
);
/**
* Initialize HT at Reset for both Normal and Recovery.
*
*/
AGESA_STATUS
AmdHtInitReset (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
);
/**
* Initialize the Node and Socket maps for an AP Core.
*
*/
AGESA_STATUS
AmdHtInitRecovery (
IN AMD_CONFIG_PARAMS *StdHeader
);
///----------------------------------------------------------------------------
/// MEMORY FUNCTIONS PROTOTYPE
///
///----------------------------------------------------------------------------
AGESA_STATUS
AmdMemRecovery (
IN OUT MEM_DATA_STRUCT *MemPtr
);
AGESA_STATUS
AmdMemAuto (
IN OUT MEM_DATA_STRUCT *MemPtr
);
VOID
AmdMemInitDataStructDef (
IN OUT MEM_DATA_STRUCT *MemPtr,
IN OUT PLATFORM_CONFIGURATION *PlatFormConfig
);
VOID
memDefRet ( VOID );
BOOLEAN
memDefTrue ( VOID );
BOOLEAN
memDefFalse ( VOID );
VOID
MemRecDefRet ( VOID );
BOOLEAN
MemRecDefTrue ( VOID );
#endif // _ADVANCED_API_H_

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@ -1,159 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Common Return routines.
*
* Routines which do nothing, returning a result (preferably some version of zero) which
* is consistent with "do nothing" or "default". Useful for function pointer tables.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Common
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*
*/
#ifndef _COMMON_RETURNS_H_
#define _COMMON_RETURNS_H_
/**
* Return True
*
* @retval True Default case, no special action
*/
BOOLEAN
CommonReturnTrue ( VOID );
/**
* Return False.
*
* @retval FALSE Default case, no special action
*/
BOOLEAN
CommonReturnFalse ( VOID );
/**
* Return (UINT8)zero.
*
*
* @retval zero None, or only case zero.
*/
UINT8
CommonReturnZero8 ( VOID );
/**
* Return (UINT32)zero.
*
*
* @retval zero None, or only case zero.
*/
UINT32
CommonReturnZero32 ( VOID );
/**
* Return (UINT64)zero.
*
*
* @retval zero None, or only case zero.
*/
UINT64
CommonReturnZero64 ( VOID );
/**
* Return (UINT8)one.
*
*
* @retval one None, or only case one.
*/
UINT8
CommonReturnOne8 ( VOID );
/**
* Return (UINT32)one.
*
*
* @retval one None, or only case one.
*/
UINT32
CommonReturnOne32 ( VOID );
/**
* Return (UINT64)one.
*
*
* @retval one None, or only case one.
*/
UINT64
CommonReturnOne64 ( VOID );
/**
* Return NULL
*
* @retval NULL pointer to nothing
*/
VOID *
CommonReturnNULL ( VOID );
/**
* Return AGESA_SUCCESS.
*
* @retval AGESA_SUCCESS Success.
*/
AGESA_STATUS
CommonReturnAgesaSuccess ( VOID );
/**
* Return AGESA_ERROR.
*
* @retval AGESA_ERROR Error.
*/
AGESA_STATUS
CommonReturnAgesaError ( VOID );
/**
* Do Nothing.
*
*/
VOID
CommonVoid ( VOID );
/**
* ASSERT if this routine is called.
*
*/
VOID
CommonAssert ( VOID );
#endif // _COMMON_RETURNS_H_

581
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@ -1,581 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Collectively assign unique filecodes for assert and debug to each source file.
*
* Publish values for decorated filenames, which can be used for
* ASSERT and debug support using a preprocessor define like:
* @n <tt> \#define FILECODE MY_C_FILENAME_FILECODE </tt> @n
* This file serves as a reference for debugging to associate the code and filename.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Include
* @e \$Revision: 86079 $ @e \$Date: 2013-01-16 00:59:04 -0600 (Wed, 16 Jan 2013) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _FILECODE_H_
#define _FILECODE_H_
#define UNASSIGNED_FILE_FILECODE (0xFFFF)
/// For debug use in any Platform's options C file.
/// Can be reused for platforms and image builds, since only one options file can be built.
#define PLATFORM_SPECIFIC_OPTIONS_FILECODE (0xBBBB)
#define PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE (0xA001)
#define PROC_GNB_GNBINITATEARLY_FILECODE (0xA017)
#define PROC_GNB_GNBINITATENV_FILECODE (0xA020)
#define PROC_GNB_GNBINITATLATE_FILECODE (0xA021)
#define PROC_GNB_GNBINITATMID_FILECODE (0xA022)
#define PROC_GNB_GNBINITATPOST_FILECODE (0xA023)
#define PROC_GNB_GNBINITATRESET_FILECODE (0xA024)
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE (0xA025)
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE (0xA026)
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE (0xA027)
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE (0xA028)
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE (0xA029)
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE (0xA02A)
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE (0xA030)
#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE (0xA031)
#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE (0xA032)
#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXPOWERPLAYTABLE_FILECODE (0xA033)
#define PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE (0xA034)
#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE (0xA036)
#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE (0xA037)
#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE (0xA038)
#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE (0xA039)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE (0xA03B)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE (0xA03C)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE (0xA03D)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE (0xA03E)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE (0xA03F)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE (0xA041)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE (0xA043)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE (0xA045)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE (0xA046)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE (0xA047)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE (0xA048)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE (0xA049)
#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE (0xA08E)
#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE (0xA08F)
#define PROC_GNB_MODULES_GNBTABLE_GNBTABLE_FILECODE (0xA090)
#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GNBGFXINITLIBV1_FILECODE (0xA091)
#define PROC_GNB_MODULES_GNBIVRSLIB_GNBIVRSLIB_FILECODE (0xA0A8)
#define PROC_GNB_MODULES_GNBNBINITLIBV4_GNBNBINITLIBV4_FILECODE (0xA0A9)
#define PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBPCIETRANSLATION_FILECODE (0xA0AA)
#define PROC_GNB_MODULES_GNBSBLIB_GNBSBPCIE_FILECODE (0xA0BA)
#define PROC_GNB_MODULES_GNBSBLIB_GNBSBLIB_FILECODE (0xA0BB)
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBTIMERLIB_FILECODE (0xA0BD)
#define PROC_GNB_MODULES_GNBPCIECONFIG_GNBHANDLELIB_FILECODE (0xA0C0)
#define PROC_GNB_MODULES_GNBPCIEASPM_PCIEASPM_FILECODE (0xA0C2)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPHYSERVICESV5_FILECODE (0xA0C5)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPIFSERVICESV5_FILECODE (0xA0C6)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPORTSERVICESV5_FILECODE (0xA0C7)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPOWERMGMTV5_FILECODE (0xA0C8)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIESILICONSERVICESV5_FILECODE (0xA0C9)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEWRAPPERSERVICESV5_FILECODE (0xA0CA)
#define PROC_GNB_MODULES_GNBNBINITLIBV5_GNBNBINITLIBV5_FILECODE (0xA0CB)
#define PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBTRANSLATION_FILECODE (0xA0DB)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPOWERMGMTV4_FILECODE (0xA0DC)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPORTSERVICESV4_FILECODE (0xA0DD)
#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGMID_FILECODE (0xA0E0)
#define PROC_GNB_MODULES_GNBIOAPIC_GNBIOAPIC_FILECODE (0xA0EE)
#define PROC_GNB_MODULES_GNBPCIEMAXPAYLOAD_PCIEMAXPAYLOAD_FILECODE (0xA0F4)
#define PROC_GNB_MODULES_GNBPCIECLKPM_PCIECLKPM_FILECODE (0xA0F5)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIETOPOLOGYSERVICESV5_FILECODE (0xA100)
#define PROC_GNB_MODULES_GNBPCIETRAININGV2_PCIETRAININGV2_FILECODE (0xA101)
#define PROC_GNB_MODULES_GNBPCIETRAININGV2_PCIEWORKAROUNDSV2_FILECODE (0xA102)
#define PROC_RECOVERY_GNB_GNBRECOVERY_FILECODE (0xAE01)
#define PROC_RECOVERY_GNB_NBINITRECOVERY_FILECODE (0xAE02)
#define PROC_GNB_GNBINITATS3SAVE_FILECODE (0xAE03)
#define PROC_GNB_MODULES_GNBSVIEW_GNBSVIEW_FILECODE (0xAE04)
#define PROC_GNB_MODULES_GNBINITKB_GFXENVINITKB_FILECODE (0xAE20)
#define PROC_GNB_MODULES_GNBINITKB_GFXINTEGRATEDINFOTABLEKB_FILECODE (0xAE21)
#define PROC_GNB_MODULES_GNBINITKB_GFXMIDINITKB_FILECODE (0xAE22)
#define PROC_GNB_MODULES_GNBINITKB_GFXPOSTINITKB_FILECODE (0xAE23)
#define PROC_GNB_MODULES_GNBINITKB_GFXLIBKB_FILECODE (0xAE24)
#define PROC_GNB_MODULES_GNBINITKB_GNBEARLYINITKB_FILECODE (0xAE25)
#define PROC_GNB_MODULES_GNBINITKB_GNBENVINITKB_FILECODE (0xAE26)
#define PROC_GNB_MODULES_GNBINITKB_GNBMIDINITKB_FILECODE (0xAE27)
#define PROC_GNB_MODULES_GNBINITKB_GNBPOSTINITKB_FILECODE (0xAE28)
#define PROC_GNB_MODULES_GNBINITKB_GNBREGISTERACCKB_FILECODE (0xAE29)
#define PROC_GNB_MODULES_GNBINITKB_PCIECOMPLEXDATAKB_FILECODE (0xAE2A)
#define PROC_GNB_MODULES_GNBINITKB_PCIECONFIGKB_FILECODE (0xAE2B)
#define PROC_GNB_MODULES_GNBINITKB_PCIEEARLYINITKB_FILECODE (0xAE2C)
#define PROC_GNB_MODULES_GNBINITKB_PCIEENVINITKB_FILECODE (0xAE2D)
#define PROC_GNB_MODULES_GNBINITKB_PCIEMIDINITKB_FILECODE (0xAE2F)
#define PROC_GNB_MODULES_GNBINITKB_PCIEPOSTINITKB_FILECODE (0xAE30)
#define PROC_GNB_MODULES_GNBINITKB_PCIELIBKB_FILECODE (0xAE31)
#define PROC_GNB_MODULES_GNBINITKB_GFXGMCINITKB_FILECODE (0xAE32)
#define PROC_GNB_MODULES_GNBPCIEALIBV2_PCIEALIBV2_FILECODE (0xAE33)
#define PROC_GNB_MODULES_GNBINITKV_ALIBKVD_FILECODE (0xAE34)
#define PROC_GNB_MODULES_GNBINITKV_GNBREGISTERXLATKV_FILECODE (0xAE37)
#define PROC_GNB_MODULES_GNBINITKV_GNBFUSETABLEKV_FILECODE (0xAE39)
#define PROC_GNB_MODULES_GNBINITKV_GNBURAKV_FILECODE (0xAE3B)
#define PROC_GNB_MODULES_GNBINITKB_GNBURATOKENMAPKB_FILECODE (0xAE3E)
#define PROC_GNB_MODULES_GNBINITBK_GNBURABK_FILECODE (0xAE3F)
#define PROC_GNB_MODULES_GNBGFXINTTABLEV3_GFXINTEGRATEDINFOTABLE_FILECODE (0xAE42)
#define PROC_GNB_MODULES_GNBGFXINTTABLEV3_GFXPWRPLAYTABLE_FILECODE (0xAE43)
#define PROC_GNB_MODULES_GNBSCSLIBV1_GNBSCSLIBV1_FILECODE (0xAE44)
#define PROC_GNB_MODULES_GNBINITKB_GFXSAMUINITKB_FILECODE (0xAE45)
#define PROC_GNB_MODULES_GNBINITML_GFXENVINITML_FILECODE (0xAE50)
// FCH
#define PROC_FCH_AZALIA_AZALIARESET_FILECODE (0xB001)
#define PROC_FCH_AZALIA_AZALIAENV_FILECODE (0xB002)
#define PROC_FCH_AZALIA_AZALIAMID_FILECODE (0xB003)
#define PROC_FCH_AZALIA_AZALIALATE_FILECODE (0xB004)
#define PROC_FCH_COMMON_ACPILIB_FILECODE (0xB010)
#define PROC_FCH_COMMON_FCHLIB_FILECODE (0xB011)
#define PROC_FCH_COMMON_FCHCOMMON_FILECODE (0xB012)
#define PROC_FCH_COMMON_FCHCOMMONSMM_FILECODE (0xB013)
#define PROC_FCH_COMMON_MEMLIB_FILECODE (0xB014)
#define PROC_FCH_COMMON_PCILIB_FILECODE (0xB015)
#define PROC_FCH_COMMON_FCHPELIB_FILECODE (0xB016)
#define PROC_FCH_GEC_GECRESET_FILECODE (0xB020)
#define PROC_FCH_GEC_GECENV_FILECODE (0xB021)
#define PROC_FCH_GEC_GECMID_FILECODE (0xB022)
#define PROC_FCH_GEC_GECLATE_FILECODE (0xB023)
#define PROC_FCH_GEC_FAMILY_YANGTZE_YANGTZEGECSERVICE_FILECODE (0xB028)
#define PROC_FCH_GEC_FAMILY_YANGTZE_YANGTZEGECENVSERVICE_FILECODE (0xB029)
#define PROC_FCH_HWACPI_HWACPIRESET_FILECODE (0xB030)
#define PROC_FCH_HWACPI_HWACPIENV_FILECODE (0xB031)
#define PROC_FCH_HWACPI_HWACPIMID_FILECODE (0xB032)
#define PROC_FCH_HWACPI_HWACPILATE_FILECODE (0xB033)
#define PROC_FCH_HWACPI_FAMILY_YANGTZE_YANGTZEHWACPIENVSERVICE_FILECODE (0xB03C)
#define PROC_FCH_HWACPI_FAMILY_YANGTZE_YANGTZEHWACPIMIDSERVICE_FILECODE (0xB03D)
#define PROC_FCH_HWACPI_FAMILY_YANGTZE_YANGTZEHWACPILATESERVICE_FILECODE (0xB03E)
#define PROC_FCH_HWACPI_FAMILY_YANGTZE_YANGTZESSSERVICE_FILECODE (0xB03F)
#define PROC_FCH_HWM_HWMRESET_FILECODE (0xB050)
#define PROC_FCH_HWM_HWMENV_FILECODE (0xB051)
#define PROC_FCH_HWM_HWMMID_FILECODE (0xB052)
#define PROC_FCH_HWM_HWMLATE_FILECODE (0xB053)
#define PROC_FCH_HWM_FAMILY_YANGTZE_YANGTZEHWMENVSERVICE_FILECODE (0xB05A)
#define PROC_FCH_HWM_FAMILY_YANGTZE_YANGTZEHWMMIDSERVICE_FILECODE (0xB05B)
#define PROC_FCH_HWM_FAMILY_YANGTZE_YANGTZEHWMLATESERVICE_FILECODE (0xB05C)
#define PROC_FCH_IMC_IMCENV_FILECODE (0xB060)
#define PROC_FCH_IMC_IMCMID_FILECODE (0xB061)
#define PROC_FCH_IMC_IMCLATE_FILECODE (0xB062)
#define PROC_FCH_IMC_IMCLIB_FILECODE (0xB063)
#define PROC_FCH_IMC_IMCRESET_FILECODE (0xB064)
#define PROC_FCH_IMC_FCHECENV_FILECODE (0xB065)
#define PROC_FCH_IMC_FCHECMID_FILECODE (0xB066)
#define PROC_FCH_IMC_FCHECLATE_FILECODE (0xB067)
#define PROC_FCH_IMC_FCHECRESET_FILECODE (0xB068)
#define PROC_FCH_IMC_FAMILY_HUDSON2_HUDSON2IMCSERVICE_FILECODE (0xB069)
#define PROC_FCH_IMC_FAMILY_YUBA_YUBAIMCSERVICE_FILECODE (0xB06A)
#define PROC_FCH_IMC_FAMILY_YANGTZE_YANGTZEIMCSERVICE_FILECODE (0xB06B)
#define PROC_FCH_IMC_FAMILY_AVALON_AVALONIMCSERVICE_FILECODE (0xB36B)
#define PROC_FCH_IDE_IDEENV_FILECODE (0xB06D)
#define PROC_FCH_IDE_IDEMID_FILECODE (0xB06E)
#define PROC_FCH_IDE_IDELATE_FILECODE (0xB06F)
#define PROC_FCH_INTERFACE_INITRESETDEF_FILECODE (0xB070)
#define PROC_FCH_INTERFACE_INITENVDEF_FILECODE (0xB071)
#define PROC_FCH_INTERFACE_FCHINITRESET_FILECODE (0xB072)
#define PROC_FCH_INTERFACE_FCHINITENV_FILECODE (0xB073)
#define PROC_FCH_INTERFACE_FCHINITLATE_FILECODE (0xB074)
#define PROC_FCH_INTERFACE_FCHINITMID_FILECODE (0xB075)
#define PROC_FCH_INTERFACE_FCHINITS3_FILECODE (0xB076)
#define PROC_FCH_INTERFACE_FCHTASKLAUNCHER_FILECODE (0xB077)
#define PROC_FCH_IR_IRENV_FILECODE (0xB080)
#define PROC_FCH_IR_IRMID_FILECODE (0xB081)
#define PROC_FCH_IR_IRLATE_FILECODE (0xB082)
#define PROC_FCH_PCIB_PCIBRESET_FILECODE (0xB090)
#define PROC_FCH_PCIB_PCIBENV_FILECODE (0xB091)
#define PROC_FCH_PCIB_PCIBMID_FILECODE (0xB092)
#define PROC_FCH_PCIB_PCIBLATE_FILECODE (0xB093)
#define PROC_FCH_PCIE_ABRESET_FILECODE (0xB0A0)
#define PROC_FCH_PCIE_ABENV_FILECODE (0xB0A1)
#define PROC_FCH_PCIE_ABMID_FILECODE (0xB0A2)
#define PROC_FCH_PCIE_ABLATE_FILECODE (0xB0A3)
#define PROC_FCH_PCIE_GPPHP_FILECODE (0xB0A4)
#define PROC_FCH_PCIE_GPPLIB_FILECODE (0xB0A5)
#define PROC_FCH_PCIE_GPPRESET_FILECODE (0xB0A6)
#define PROC_FCH_PCIE_GPPENV_FILECODE (0xB0A7)
#define PROC_FCH_PCIE_GPPMID_FILECODE (0xB0A8)
#define PROC_FCH_PCIE_GPPLATE_FILECODE (0xB0A9)
#define PROC_FCH_PCIE_PCIERESET_FILECODE (0xB0AA)
#define PROC_FCH_PCIE_PCIEENV_FILECODE (0xB0AB)
#define PROC_FCH_PCIE_PCIEMID_FILECODE (0xB0AC)
#define PROC_FCH_PCIE_PCIELATE_FILECODE (0xB0AD)
#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABRESETSERVICE_FILECODE (0xB0AE)
#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABENVSERVICE_FILECODE (0xB0AF)
#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABSERVICE_FILECODE (0xB0B0)
#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPRESETSERVICE_FILECODE (0xB0B1)
#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPSERVICE_FILECODE (0xB0B2)
#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIEENVSERVICE_FILECODE (0xB0B3)
#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIESERVICE_FILECODE (0xB0B4)
#define PROC_FCH_PCIE_FAMILY_YUBA_YUBAABRESETSERVICE_FILECODE (0xB0B5)
#define PROC_FCH_PCIE_FAMILY_YUBA_YUBAABENVSERVICE_FILECODE (0xB0B6)
#define PROC_FCH_PCIE_FAMILY_YUBA_YUBAABSERVICE_FILECODE (0xB0B7)
#define PROC_FCH_PCIE_FAMILY_YANGTZE_YANGTZEABRESETSERVICE_FILECODE (0xB0B8)
#define PROC_FCH_PCIE_FAMILY_YANGTZE_YANGTZEABENVSERVICE_FILECODE (0xB0B9)
#define PROC_FCH_PCIE_FAMILY_YANGTZE_YANGTZEABSERVICE_FILECODE (0xB0BA)
#define PROC_FCH_PCIE_FAMILY_AVALON_AVALONABRESETSERVICE_FILECODE (0xB3B8)
#define PROC_FCH_PCIE_FAMILY_AVALON_AVALONABENVSERVICE_FILECODE (0xB3B9)
#define PROC_FCH_PCIE_FAMILY_AVALON_AVALONABSERVICE_FILECODE (0xB3BA)
#define PROC_FCH_SATA_AHCIENV_FILECODE (0xB0C0)
#define PROC_FCH_SATA_AHCIMID_FILECODE (0xB0C1)
#define PROC_FCH_SATA_AHCILATE_FILECODE (0xB0C2)
#define PROC_FCH_SATA_AHCILIB_FILECODE (0xB0C3)
#define PROC_FCH_SATA_IDE2AHCIENV_FILECODE (0xB0C4)
#define PROC_FCH_SATA_IDE2AHCIMID_FILECODE (0xB0C5)
#define PROC_FCH_SATA_IDE2AHCILATE_FILECODE (0xB0C6)
#define PROC_FCH_SATA_IDE2AHCILIB_FILECODE (0xB0C7)
#define PROC_FCH_SATA_RAIDENV_FILECODE (0xB0C8)
#define PROC_FCH_SATA_RAIDMID_FILECODE (0xB0C9)
#define PROC_FCH_SATA_RAIDLATE_FILECODE (0xB0CA)
#define PROC_FCH_SATA_RAIDLIB_FILECODE (0xB0CB)
#define PROC_FCH_SATA_SATAENV_FILECODE (0xB0CC)
#define PROC_FCH_SATA_SATAENVLIB_FILECODE (0xB0CD)
#define PROC_FCH_SATA_SATAIDEENV_FILECODE (0xB0CE)
#define PROC_FCH_SATA_SATAIDEMID_FILECODE (0xB0CF)
#define PROC_FCH_SATA_SATAIDELATE_FILECODE (0xB0D0)
#define PROC_FCH_SATA_SATAIDELIB_FILECODE (0xB0D1)
#define PROC_FCH_SATA_SATAMID_FILECODE (0xB0D2)
#define PROC_FCH_SATA_SATALATE_FILECODE (0xB0D3)
#define PROC_FCH_SATA_SATALIB_FILECODE (0xB0D4)
#define PROC_FCH_SATA_SATARESET_FILECODE (0xB0D5)
#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATARESETSERVICE_FILECODE (0xB0D6)
#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATAENVSERVICE_FILECODE (0xB0D7)
#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATASERVICE_FILECODE (0xB0D8)
#define PROC_FCH_SATA_FAMILY_YUBA_YUBASATARESETSERVICE_FILECODE (0xB0D9)
#define PROC_FCH_SATA_FAMILY_YUBA_YUBASATAENVSERVICE_FILECODE (0xB0DA)
#define PROC_FCH_SATA_FAMILY_YUBA_YUBASATASERVICE_FILECODE (0xB0DB)
#define PROC_FCH_SATA_FAMILY_YANGTZE_YANGTZESATARESETSERVICE_FILECODE (0xB0DC)
#define PROC_FCH_SATA_FAMILY_YANGTZE_YANGTZESATAENVSERVICE_FILECODE (0xB0DD)
#define PROC_FCH_SATA_FAMILY_YANGTZE_YANGTZESATASERVICE_FILECODE (0xB0DE)
#define PROC_FCH_SD_SDENV_FILECODE (0xB0E0)
#define PROC_FCH_SD_SDMID_FILECODE (0xB0E1)
#define PROC_FCH_SD_SDLATE_FILECODE (0xB0E2)
#define PROC_FCH_SD_FAMILY_YANGTZE_YANGTZESDSERVICE_FILECODE (0xB0E9)
#define PROC_FCH_SD_FAMILY_YANGTZE_YANGTZESDRESETSERVICE_FILECODE (0xB0EA)
#define PROC_FCH_SD_FAMILY_YANGTZE_YANGTZESDENVSERVICE_FILECODE (0xB0EB)
#define PROC_FCH_SPI_LPCRESET_FILECODE (0xB0F0)
#define PROC_FCH_SPI_LPCENV_FILECODE (0xB0F1)
#define PROC_FCH_SPI_LPCMID_FILECODE (0xB0F2)
#define PROC_FCH_SPI_LPCLATE_FILECODE (0xB0F3)
#define PROC_FCH_SPI_SPIRESET_FILECODE (0xB0F4)
#define PROC_FCH_SPI_SPIENV_FILECODE (0xB0F5)
#define PROC_FCH_SPI_SPIMID_FILECODE (0xB0F6)
#define PROC_FCH_SPI_SPILATE_FILECODE (0xB0F7)
#define PROC_FCH_SPI_FAMILY_YANGTZE_YANGTZELPCENVSERVICE_FILECODE (0xB0FE)
#define PROC_FCH_SPI_FAMILY_YANGTZE_YANGTZELPCRESETSERVICE_FILECODE (0xB0FF)
#define PROC_FCH_USB_EHCIRESET_FILECODE (0xB100)
#define PROC_FCH_USB_EHCIENV_FILECODE (0xB101)
#define PROC_FCH_USB_EHCIMID_FILECODE (0xB102)
#define PROC_FCH_USB_EHCILATE_FILECODE (0xB103)
#define PROC_FCH_USB_OHCIRESET_FILECODE (0xB104)
#define PROC_FCH_USB_OHCIENV_FILECODE (0xB105)
#define PROC_FCH_USB_OHCIMID_FILECODE (0xB106)
#define PROC_FCH_USB_OHCILATE_FILECODE (0xB107)
#define PROC_FCH_USB_USBRESET_FILECODE (0xB108)
#define PROC_FCH_USB_USBENV_FILECODE (0xB109)
#define PROC_FCH_USB_USBMID_FILECODE (0xB10A)
#define PROC_FCH_USB_USBLATE_FILECODE (0xB10B)
#define PROC_FCH_USB_XHCIRESET_FILECODE (0xB10C)
#define PROC_FCH_USB_XHCIENV_FILECODE (0xB10D)
#define PROC_FCH_USB_XHCIMID_FILECODE (0xB10E)
#define PROC_FCH_USB_XHCILATE_FILECODE (0xB10F)
#define PROC_FCH_USB_FAMILY_YANGTZE_YANGTZEEHCIENVSERVICE_FILECODE (0xB124)
#define PROC_FCH_USB_FAMILY_YANGTZE_YANGTZEEHCIMIDSERVICE_FILECODE (0xB125)
#define PROC_FCH_USB_FAMILY_YANGTZE_YANGTZEEHCILATESERVICE_FILECODE (0xB126)
#define PROC_FCH_USB_FAMILY_YANGTZE_YANGTZEOHCIENVSERVICE_FILECODE (0xB127)
#define PROC_FCH_USB_FAMILY_YANGTZE_YANGTZEOHCIMIDSERVICE_FILECODE (0xB128)
#define PROC_FCH_USB_FAMILY_YANGTZE_YANGTZEOHCILATESERVICE_FILECODE (0xB129)
#define PROC_FCH_USB_FAMILY_YANGTZE_YANGTZEXHCIRESETSERVICE_FILECODE (0xB12A)
#define PROC_FCH_USB_FAMILY_YANGTZE_YANGTZEXHCIENVSERVICE_FILECODE (0xB12B)
#define PROC_FCH_USB_FAMILY_YANGTZE_YANGTZEXHCIMIDSERVICE_FILECODE (0xB12C)
#define PROC_FCH_USB_FAMILY_YANGTZE_YANGTZEXHCILATESERVICE_FILECODE (0xB12D)
#define PROC_FCH_USB_XHCIRECOVERY_FILECODE (0xB12E)
#define PROC_FCH_PCIE_GPPPORTINIT_FILECODE (0xB12F)
#define PROC_FCH_PCIE_GPPALLINONE_FILECODE (0xB2C0)
#define LIB_AMDLIB_FILECODE (0xC001)
#define LEGACY_PROC_AGESACALLOUTS_FILECODE (0xC010)
#define LEGACY_PROC_HOBTRANSFER_FILECODE (0xC011)
#define LEGACY_PROC_DISPATCHER_FILECODE (0xC012)
#define PROC_COMMON_AMDINITEARLY_FILECODE (0xC020)
#define PROC_COMMON_AMDINITENV_FILECODE (0xC021)
#define PROC_COMMON_AMDINITLATE_FILECODE (0xC022)
#define PROC_COMMON_AMDINITMID_FILECODE (0xC023)
#define PROC_COMMON_AMDINITPOST_FILECODE (0xC024)
#define PROC_COMMON_AMDINITRECOVERY_FILECODE (0xC025)
#define PROC_COMMON_AMDINITRESET_FILECODE (0xC026)
#define PROC_COMMON_AMDINITRESUME_FILECODE (0xC027)
#define PROC_COMMON_AMDS3LATERESTORE_FILECODE (0xC028)
#define PROC_COMMON_AMDS3SAVE_FILECODE (0xC029)
#define PROC_COMMON_AMDLATERUNAPTASK_FILECODE (0xC02A)
#define PROC_COMMON_COMMONRETURNS_FILECODE (0xC0C0)
#define PROC_COMMON_CREATESTRUCT_FILECODE (0xC0D0)
#define PROC_COMMON_COMMONINITS_FILECODE (0xC0F0)
#define PROC_COMMON_S3RESTORESTATE_FILECODE (0xC0F8)
#define PROC_COMMON_S3SAVESTATE_FILECODE (0xC0F9)
#define PROC_CPU_CPUAPICUTILITIES_FILECODE (0xC401)
#define PROC_CPU_TABLE_FILECODE (0xC403)
#define PROC_CPU_TABLEHT_FILECODE (0xC404)
#define PROC_CPU_CPUEARLYINIT_FILECODE (0xC405)
#define PROC_CPU_CPUEVENTLOG_FILECODE (0xC406)
#define PROC_CPU_CPUFAMILYTRANSLATION_FILECODE (0xC407)
#define PROC_CPU_CPUGENERALSERVICES_FILECODE (0xC408)
#define PROC_CPU_CPULATEINIT_FILECODE (0xC40A)
#define PROC_CPU_CPUMICROCODEPATCH_FILECODE (0xC40B)
#define PROC_CPU_CPUWARMRESET_FILECODE (0xC40C)
#define PROC_CPU_HEAPMANAGER_FILECODE (0xC40D)
#define PROC_CPU_CPUBIST_FILECODE (0xC40E)
#define PROC_CPU_MMIOMAPMANAGER_FILECODE (0xC40F)
#define PROC_CPU_CPUPOSTINIT_FILECODE (0xC420)
#define PROC_CPU_CPUPOWERMGMT_FILECODE (0xC430)
#define PROC_CPU_CPUPOWERMGMTMULTISOCKET_FILECODE (0xC431)
#define PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE (0xC432)
#define PROC_CPU_S3_FILECODE (0xC460)
// Family 15h
// Family 16h
#define PROC_CPU_FAMILY_0X16_CPUF16BRANDID_FILECODE (0xCC00)
#define PROC_CPU_FAMILY_0X16_CPUF16UTILITIES_FILECODE (0xCC01)
#define PROC_CPU_FAMILY_0X16_CPUF16WHEAINITDATATABLES_FILECODE (0xCC02)
#define PROC_CPU_FAMILY_0X16_CPUF16CACHEDEFAULTS_FILECODE (0xCC03)
#define PROC_CPU_FAMILY_0X16_CPUF16DMI_FILECODE (0xCC04)
#define PROC_CPU_FAMILY_0X16_CPUF16PCIUNKNOWNTABLES_FILECODE (0xCC05)
#define PROC_CPU_FAMILY_0X16_CPUF16MSRUNKNOWNTABLES_FILECODE (0xCC06)
#define PROC_CPU_FAMILY_0X16_CPUF16PSTATEHPCMODE_FILECODE (0xCC07)
#define PROC_CPU_FAMILY_0X16_CPUF16MMIOMAP_FILECODE (0xCC08)
#define PROC_CPU_FAMILY_0X16_CPUF16PREFETCHMODE_FILECODE (0xCC09)
#define PROC_CPU_FAMILY_0X16_CPUF16APM_FILECODE (0xCC0A)
#define PROC_CPU_FAMILY_0X16_CPUF16CRAT_FILECODE (0xCC0B)
#define PROC_CPU_FAMILY_0X16_KB_F16KBLOGICALIDTABLES_FILECODE (0xCC20)
#define PROC_CPU_FAMILY_0X16_KB_F16KBINITEARLYTABLE_FILECODE (0xCC21)
#define PROC_CPU_FAMILY_0X16_KB_F16KBEQUIVALENCETABLE_FILECODE (0xCC22)
#define PROC_CPU_FAMILY_0X16_KB_F16KBMICROCODEPATCHTABLES_FILECODE (0xCC23)
#define PROC_CPU_FAMILY_0X16_KB_F16KBPCITABLES_FILECODE (0xCC24)
#define PROC_CPU_FAMILY_0X16_KB_F16KBMSRTABLES_FILECODE (0xCC25)
#define PROC_CPU_FAMILY_0X16_KB_F16KBSHAREDMSRTABLE_FILECODE (0xCC26)
#define PROC_CPU_FAMILY_0X16_KB_F16KBUTILITIES_FILECODE (0xCC27)
#define PROC_CPU_FAMILY_0X16_KB_F16KBC6STATE_FILECODE (0xCC28)
#define PROC_CPU_FAMILY_0X16_KB_F16KBCOREAFTERRESET_FILECODE (0xCC29)
#define PROC_CPU_FAMILY_0X16_KB_F16KBCPB_FILECODE (0xCC2A)
#define PROC_CPU_FAMILY_0X16_KB_F16KBDMI_FILECODE (0xCC2B)
#define PROC_CPU_FAMILY_0X16_KB_F16KBIOCSTATE_FILECODE (0xCC2C)
#define PROC_CPU_FAMILY_0X16_KB_F16KBNBAFTERRESET_FILECODE (0xCC2D)
#define PROC_CPU_FAMILY_0X16_KB_F16KBPOWERCHECK_FILECODE (0xCC2E)
#define PROC_CPU_FAMILY_0X16_KB_F16KBPSTATE_FILECODE (0xCC2F)
#define PROC_CPU_FAMILY_0X16_KB_F16KBPSI_FILECODE (0xCC30)
#define PROC_CPU_FAMILY_0X16_KB_F16KBHTC_FILECODE (0xCC31)
#define PROC_CPU_FAMILY_0X16_KB_F16KBPOWERMGMTSYSTEMTABLES_FILECODE (0xCC32)
#define PROC_CPU_FAMILY_0X16_KB_F16KBSCS_FILECODE (0xCC33)
#define PROC_CPU_FAMILY_0X16_KB_F16KBCACHEFLUSHONHALT_FILECODE (0xCC34)
#define PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE (0xDC01)
#define PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE (0xDC02)
#define PROC_CPU_FEATURE_CPUDMI_FILECODE (0xDC10)
#define PROC_CPU_FEATURE_CPUFEATURELEVELING_FILECODE (0xDC20)
#define PROC_CPU_FEATURE_CPUL3FEATURES_FILECODE (0xDC30)
#define PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE (0xDC41)
#define PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE (0xDC42)
#define PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE (0xDC43)
#define PROC_CPU_FEATURE_CPUSLIT_FILECODE (0xDC50)
#define PROC_CPU_FEATURE_CPUSRAT_FILECODE (0xDC60)
#define PROC_CPU_FEATURE_CPUWHEA_FILECODE (0xDC70)
#define PROC_CPU_FEATURE_CPUC6STATE_FILECODE (0xDC82)
#define PROC_CPU_FEATURE_CPUCPB_FILECODE (0xDC83)
#define PROC_CPU_FEATURE_CPULOWPWRPSTATE_FILECODE (0xDC84)
#define PROC_CPU_FEATURE_CPUIOCSTATE_FILECODE (0xDC85)
#define PROC_CPU_FEATURE_CPUPSTATEHPCMODE_FILECODE (0xDC86)
#define PROC_CPU_FEATURE_CPUAPM_FILECODE (0xDC87)
#define PROC_CPU_FEATURE_CPUFEATURES_FILECODE (0xDC90)
#define PROC_CPU_FEATURE_CPUMSGBASEDC1E_FILECODE (0xDCA0)
#define PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE (0xDCB0)
#define PROC_CPU_FEATURE_PRESERVEMAILBOX_FILECODE (0xDCC0)
#define PROC_CPU_FEATURE_CPUPSI_FILECODE (0xDCC1)
#define PROC_CPU_FEATURE_CPUHTC_FILECODE (0xDCC2)
#define PROC_CPU_FEATURE_CPUCRAT_FILECODE (0xDCD0)
#define PROC_CPU_FEATURE_CPUCDIT_FILECODE (0xDCD1)
#define PROC_CPU_FEATURE_CPUTDPLIMITING_FILECODE (0xDCD2)
#define PROC_CPU_FEATURE_CPUPREFETCHMODE_FILECODE (0xDCD3)
#define PROC_CPU_FEATURE_CPUSCS_FILECODE (0xDCD4)
#define PROC_IDS_CONTROL_IDSCTRL_FILECODE (0xE801)
#define PROC_IDS_LIBRARY_IDSLIB_FILECODE (0xE802)
#define PROC_IDS_DEBUG_IDSDEBUG_FILECODE (0xE803)
#define PROC_IDS_PERF_IDSPERF_FILECODE (0xE804)
#define PROC_IDS_LIBRARY_IDSREGACC_FILECODE (0xE810)
#define PROC_IDS_DEBUG_IDSDPHDTOUT_FILECODE (0xE811)
#define PROC_IDS_DEBUG_IDSDEBUGPRINT_FILECODE (0xE812)
#define PROC_IDS_DEBUG_IDSDPSERIAL_FILECODE (0xE813)
#define PROC_IDS_DEBUG_IDSDPREDIRECTIO_FILECODE (0xE814)
#define PROC_IDS_DEBUG_IDSDPRAM_FILECODE (0xE815)
#define PROC_IDS_DEBUG_IDSIDTTABLE_FILECODE (0xE81E)
#define PROC_IDS_CONTROL_IDSNVTOCMOS_FILECODE (0xE81F)
#define PROC_IDS_FAMILY_0X16_KB_IDSF16KBALLSERVICE_FILECODE (0xE821)
///0xE820 ~ 0xE840 is reserved for ids extend module
#define PROC_MEM_ARDK_MA_FILECODE (0xF001)
#define PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE (0xF081)
#define PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE (0xF082)
#define PROC_MEM_FEAT_ECC_MFECC_FILECODE (0xF083)
#define PROC_MEM_FEAT_ECC_MFEMP_FILECODE (0xF085)
#define PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE (0xF086)
#define PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE (0xF088)
#define PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE (0xF08A)
#define PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE (0xF08B)
#define PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE (0xF08D)
#define PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE (0xF08F)
#define PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE (0xF091)
#define PROC_MEM_FEAT_S3_MFS3_FILECODE (0xF092)
#define PROC_MEM_FEAT_TABLE_MFTDS_FILECODE (0xF093)
#define PROC_MEM_FEAT_CRAT_MFCRAT_FILECODE (0xF095)
#define PROC_MEM_FEAT_DATAEYE_MF2DDATAEYE_FILECODE (0xF097)
#define PROC_MEM_FEAT_RDWR2DTRAINING_MFWRDAT2DTRAINING_FILECODE (0xF098)
#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDWR2DEYERIMSEARCH_FILECODE (0xF099)
#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDDQS2DTRAINING_FILECODE (0xF09A)
#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDWR2DTRAINING_FILECODE (0xF09B)
#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDWR2DPATTERNGENERATION_FILECODE (0xF09C)
#define PROC_MEM_FEAT_RDWR2DTRAINING_KB_MFRDWR2DKB_FILECODE (0xF09D)
#define PROC_MEM_FEAT_RDWR2DTRAINING_ML_MFRDWR2DML_FILECODE (0xF09E)
#define PROC_MEM_FEAT_AGGRESSOR_MFAGGRESSOR_FILECODE (0xF09F)
#define PROC_MEM_MAIN_MDEF_FILECODE (0xF101)
#define PROC_MEM_MAIN_MINIT_FILECODE (0xF102)
#define PROC_MEM_MAIN_MM_FILECODE (0xF103)
#define PROC_MEM_FEAT_DMI_MFDMI_FILECODE (0xF104)
#define PROC_MEM_MAIN_MMECC_FILECODE (0xF105)
#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE (0xF106)
#define PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE (0xF10B)
#define PROC_MEM_MAIN_MMONLINESPARE_FILECODE (0xF10C)
#define PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE (0xF10D)
#define PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE (0xF10E)
#define PROC_MEM_MAIN_MUC_FILECODE (0xF10F)
#define PROC_MEM_MAIN_MMMEMCLR_FILECODE (0xF110)
#define PROC_MEM_MAIN_MMFLOW_FILECODE (0xF112)
#define PROC_MEM_MAIN_MERRHDL_FILECODE (0xF113)
#define PROC_MEM_MAIN_MMLVDDR3_FILECODE (0xF115)
#define PROC_MEM_MAIN_MMUMAALLOC_FILECODE (0xF116)
#define PROC_MEM_MAIN_MMMEMRESTORE_FILECODE (0xF117)
#define PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE (0xF118)
#define PROC_MEM_MAIN_MMAGGRESSOR_FILECODE (0xF119)
#define PROC_MEM_MAIN_KB_MMFLOWKB_FILECODE (0xF124)
#define PROC_MEM_NB_MN_FILECODE (0xF27C)
#define PROC_MEM_NB_MNDCT_FILECODE (0xF27D)
#define PROC_MEM_NB_MNPHY_FILECODE (0xF27E)
#define PROC_MEM_NB_MNMCT_FILECODE (0xF27F)
#define PROC_MEM_NB_MNS3_FILECODE (0xF280)
#define PROC_MEM_NB_MNFLOW_FILECODE (0xF281)
#define PROC_MEM_NB_MNFEAT_FILECODE (0xF282)
#define PROC_MEM_NB_MNTRAIN3_FILECODE (0xF284)
#define PROC_MEM_NB_MNREG_FILECODE (0xF285)
#define PROC_MEM_NB_MNPMU_FILECODE (0xF2B7)
#define PROC_MEM_NB_KB_MNREGKB_FILECODE (0xF2B8)
#define PROC_MEM_NB_KB_MNKB_FILECODE (0xF2B9)
#define PROC_MEM_NB_KB_MNMCTKB_FILECODE (0xF2BA)
#define PROC_MEM_NB_KB_MNOTKB_FILECODE (0xF2BB)
#define PROC_MEM_NB_KB_MNDCTKB_FILECODE (0xF2BC)
#define PROC_MEM_NB_KB_MNPHYKB_FILECODE (0xF2BD)
#define PROC_MEM_NB_KB_MNS3KB_FILECODE (0xF2BE)
#define PROC_MEM_NB_KB_MNIDENDIMMKB_FILECODE (0xF2BF)
#define PROC_MEM_NB_KB_MNFLOWKB_FILECODE (0xF2C0)
#define PROC_MEM_NB_KB_MNPROTOKB_FILECODE (0xF2C1)
#define PROC_MEM_PS_MP_FILECODE (0xF401)
#define PROC_MEM_PS_MPRTT_FILECODE (0xF422)
#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0xF423)
#define PROC_MEM_PS_MPODTPAT_FILECODE (0xF424)
#define PROC_MEM_PS_MPSAO_FILECODE (0xF425)
#define PROC_MEM_PS_MPMR0_FILECODE (0xF426)
#define PROC_MEM_PS_MPRC2IBT_FILECODE (0xF427)
#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0xF428)
#define PROC_MEM_PS_MPLRIBT_FILECODE (0xF429)
#define PROC_MEM_PS_MPLRNPR_FILECODE (0xF42A)
#define PROC_MEM_PS_MPLRNLR_FILECODE (0xF42B)
#define PROC_MEM_PS_MPS2D_FILECODE (0xF436)
#define PROC_MEM_PS_MPSEEDS_FILECODE (0xF437)
#define PROC_MEM_PS_KB_MPSKB3_FILECODE (0xF438)
#define PROC_MEM_PS_KB_MPKB3_FILECODE (0xF439)
#define PROC_MEM_PS_KB_MPUKB3_FILECODE (0xF43A)
#define PROC_MEM_PS_KB_FT3_MPSKBFT3_FILECODE (0xF43B)
#define PROC_MEM_PS_MPCADCFG_FILECODE (0xF43C)
#define PROC_MEM_PS_MPDATACFG_FILECODE (0xF43D)
#define PROC_MEM_TECH_MT_FILECODE (0xF501)
#define PROC_MEM_TECH_MTHDI_FILECODE (0xF502)
#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0xF504)
#define PROC_MEM_TECH_MTTECC_FILECODE (0xF505)
#define PROC_MEM_TECH_MTTHRC_FILECODE (0xF506)
#define PROC_MEM_TECH_MTTML_FILECODE (0xF507)
#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0xF509)
#define PROC_MEM_TECH_MTTSRC_FILECODE (0xF50B)
#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0xF50C)
#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0xF581)
#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0xF583)
#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0xF584)
#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0xF585)
#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0xF586)
#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0xF587)
#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0xF588)
#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0xF589)
#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0xF58A)
#define PROC_MEM_TECH_MTRRDDQS2DTRAINING_FILECODE (0xF58B)
#define PROC_MEM_TECH_MTRRDDQS2DEYERIMSEARCH_FILECODE (0xF58C)
#endif // _FILECODE_H_

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@ -1,201 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* General Services
*
* Provides Services similar to the external General Services API, except
* suited to use within AGESA components. Socket, Core and PCI identification.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Common
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _GENERAL_SERVICES_H_
#define _GENERAL_SERVICES_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
#define NUMBER_OF_EVENT_DATA_PARAMS 4
/**
* AMD Device id for MMIO check.
*/
#define AMD_DEV_VEN_ID 0x1022
#define AMD_DEV_VEN_ID_ADDRESS 0
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/**
* An AGESA Event Log entry.
*/
typedef struct {
AGESA_STATUS EventClass; ///< The severity of the event, its associated AGESA_STATUS.
UINT32 EventInfo; ///< Uniquely identifies the event.
UINT32 DataParam1; ///< Event specific additional data
UINT32 DataParam2; ///< Event specific additional data
UINT32 DataParam3; ///< Event specific additional data
UINT32 DataParam4; ///< Event specific additional data
} AGESA_EVENT;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
/**
* Get a specified Core's APIC ID.
*
* @param[in] StdHeader Header for library and services.
* @param[in] Socket The Core's Socket.
* @param[in] Core The Core id.
* @param[out] ApicAddress The Core's APIC ID.
* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
*
* @retval TRUE The core is present, APIC Id valid
* @retval FALSE The core is not present, APIC Id not valid.
*/
BOOLEAN
GetApicId (
IN AMD_CONFIG_PARAMS *StdHeader,
IN UINT32 Socket,
IN UINT32 Core,
OUT UINT8 *ApicAddress,
OUT AGESA_STATUS *AgesaStatus
);
/**
* Get Processor Module's PCI Config Space address.
*
* @param[in] StdHeader Header for library and services.
* @param[in] Socket The Core's Socket.
* @param[in] Module The Module in that Processor
* @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0)
* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
*
* @retval TRUE The core is present, PCI Address valid
* @retval FALSE The core is not present, PCI Address not valid.
*/
BOOLEAN
GetPciAddress (
IN AMD_CONFIG_PARAMS *StdHeader,
IN UINT32 Socket,
IN UINT32 Module,
OUT PCI_ADDR *PciAddress,
OUT AGESA_STATUS *AgesaStatus
);
/**
* "Who am I" for the current running core.
*
* @param[in] StdHeader Header for library and services.
* @param[out] Socket The current Core's Socket
* @param[out] Module The current Core's Processor Module
* @param[out] Core The current Core's core id.
* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
*
*/
VOID
IdentifyCore (
IN AMD_CONFIG_PARAMS *StdHeader,
OUT UINT32 *Socket,
OUT UINT32 *Module,
OUT UINT32 *Core,
OUT AGESA_STATUS *AgesaStatus
);
/**
* A boolean function determine executed CPU is BSP core.
*/
BOOLEAN
IsBsp (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
OUT AGESA_STATUS *AgesaStatus
);
/**
* This function logs AGESA events into the event log.
*/
VOID
PutEventLog (
IN AGESA_STATUS EventClass,
IN UINT32 EventInfo,
IN UINT32 DataParam1,
IN UINT32 DataParam2,
IN UINT32 DataParam3,
IN UINT32 DataParam4,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function gets event logs from the circular buffer.
*/
AGESA_STATUS
GetEventLog (
OUT AGESA_EVENT *EventRecord,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function gets event logs from the circular buffer without flushing the entry.
*/
BOOLEAN
PeekEventLog (
OUT AGESA_EVENT *EventRecord,
IN UINT16 Index,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*---------------------------------------------------------------------------------------*/
/**
* This routine programs the registers necessary to get the PCI MMIO mechanism
* up and functioning.
*/
VOID
InitializePciMmio (
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _GENERAL_SERVICES_H_

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/* $NoKeywords:$ */
/**
* @file
*
* GNB API definition.
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
* @e \$Revision: 84514 $ @e \$Date: 2012-12-17 10:44:17 -0600 (Mon, 17 Dec 2012) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*
*/
#ifndef _GNBINTERFACE_H_
#define _GNBINTERFACE_H_
AGESA_STATUS
GnbInitAtReset (
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
GnbInitAtEarly (
IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
);
VOID
GnbInitDataStructAtPostDef (
IN OUT GNB_POST_CONFIGURATION *GnbPostConfigPtr,
IN AMD_POST_PARAMS *PostParamsPtr
);
AGESA_STATUS
GnbInitAtPost (
IN OUT AMD_POST_PARAMS *PostParamsPtr
);
VOID
GnbInitDataStructAtEnvDef (
IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr,
IN AMD_ENV_PARAMS *EnvParamsPtr
);
VOID
GnbInitDataStructAtMidDef (
IN OUT GNB_MID_CONFIGURATION *GnbMidConfigPtr,
IN AMD_MID_PARAMS *MidParamsPtr
);
VOID
GnbInitDataStructAtLateDef (
IN OUT GNB_LATE_CONFIGURATION *GnbLateConfigPtr,
IN AMD_LATE_PARAMS *LateParamsPtr
);
AGESA_STATUS
GnbInitAtEnv (
IN AMD_ENV_PARAMS *EnvParamsPtr
);
AGESA_STATUS
GnbInitAtMid (
IN OUT AMD_MID_PARAMS *MidParamsPtr
);
AGESA_STATUS
GnbInitAtLate (
IN OUT AMD_LATE_PARAMS *LateParamsPtr
);
AGESA_STATUS
GnbInitAtPostAfterDram (
IN OUT AMD_POST_PARAMS *PostParamsPtr
);
AGESA_STATUS
AmdGnbRecovery (
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
GnbInitAtEarlier (
IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
);
AGESA_STATUS
GnbInitAtS3Save (
IN OUT AMD_S3SAVE_PARAMS *AmdS3SaveParams
);
#endif

1418
src/vendorcode/amd/agesa/f16kb/Include/Ids.h
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src/vendorcode/amd/agesa/f16kb/Include/IdsHt.h
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/* $NoKeywords:$ */
/**
* @file
*
* AMD IDS HyperTransport Definitions
*
* Contains AMD AGESA Integrated Debug HT related items.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: IDS
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _IDS_HT_H_
#define _IDS_HT_H_
// Frequency equates for call backs which take an actual frequency setting
#define HT_FREQUENCY_200M 0
#define HT_FREQUENCY_400M 2
#define HT_FREQUENCY_600M 4
#define HT_FREQUENCY_800M 5
#define HT_FREQUENCY_1000M 6
#define HT_FREQUENCY_1200M 7
#define HT_FREQUENCY_1400M 8
#define HT_FREQUENCY_1600M 9
#define HT_FREQUENCY_1800M 10
#define HT_FREQUENCY_2000M 11
#define HT_FREQUENCY_2200M 12
#define HT_FREQUENCY_2400M 13
#define HT_FREQUENCY_2600M 14
#define HT_FREQUENCY_2800M 17
#define HT_FREQUENCY_3000M 18
#define HT_FREQUENCY_3200M 19
#define HT_FREQUENCY_3600M 20
/**
* HT IDS: HT Link Port Override params.
*
* Provide an absolute override of HT Link Port settings. No checking is done that
* the settings obey limits or capabilities, this responsibility rests with the user.
*
* Rules for values of structure items:
* - Socket
* - HT_LIST_TERMINAL == end of port override list, rest of item is not accessed
* - HT_LIST_MATCH_ANY == Match Any Socket
* - 0 .. 7 == The matching socket
* - Link
* - HT_LIST_MATCH_ANY == Match Any package link (that is not the internal links)
* - HT_LIST_MATCH_INTERNAL_LINK == Match the internal links
* - 0 .. 7 == The matching package link. 0 .. 3 are the ganged links or sublink 0's, 4 .. 7 are the sublink1's.
* - Frequency
* - HT_LIST_TERMINAL == Do not override the frequency, AUTO setting
* - HT_FREQUENCY_200M .. HT_FREQUENCY_3600M = The frequency value to use
* - Widthin
* - HT_LIST_TERMINAL == Do not override the width, AUTO setting
* - 2, 4, 8, 16, 32 == The width value to use
* - Widthout
* - HT_LIST_TERMINAL == Do not override the width, AUTO setting
* - 2, 4, 8, 16, 32 == The width value to use
*/
typedef struct {
// Match Fields
UINT8 Socket; ///< The Socket which this port is on.
UINT8 Link; ///< The port for this package link on that socket.
// Override fields
UINT8 Frequency; ///< Absolutely override the port's frequency.
UINT8 WidthIn; ///< Absolutely override the port's width.
UINT8 WidthOut; ///< Absolutely override the port's width.
} HTIDS_PORT_OVERRIDE;
/**
* A list of port overrides to search.
*/
typedef HTIDS_PORT_OVERRIDE *HTIDS_PORT_OVERRIDE_LIST;
VOID
HtIdsGetPortOverride (
IN BOOLEAN IsSourcePort,
IN OUT PORT_DESCRIPTOR *Port0,
IN OUT PORT_DESCRIPTOR *Port1,
IN OUT HTIDS_PORT_OVERRIDE_LIST *PortOverrideList,
IN STATE_DATA *State
);
typedef
VOID
F_HtIdsGetPortOverride (
IN BOOLEAN IsSourcePort,
IN OUT PORT_DESCRIPTOR *Port0,
IN OUT PORT_DESCRIPTOR *Port1,
IN OUT HTIDS_PORT_OVERRIDE_LIST *PortOverrideList,
IN STATE_DATA *State
);
typedef F_HtIdsGetPortOverride* PF_HtIdsGetPortOverride;
#endif // _IDS_HT_H

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/* $NoKeywords:$ */
/**
* @file
*
* AMD Integrated Debug Routines for performance analysis
*
* Contains AMD AGESA debug macros and functions for performance analysis
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: IDS
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _IDS_PERFORMANCE_DATA_POINT
#define _IDS_PERFORMANCE_DATA_POINT
#define IDS_PERF_VERSION 0x00010000ul //version number 0.1.0.0
/// Time points performance function used
typedef enum {
TP_BEGINPROCAMDINITEARLY = 0x100, ///< BeginProcAmdInitEarly
TP_ENDPROCAMDINITEARLY = 0x101, ///< EndProcAmdInitEarly
TP_BEGINAMDHTINITIALIZE = 0x102, ///< BeginAmdHtInitialize
TP_ENDAMDHTINITIALIZE = 0x103, ///< EndAmdHtInitialize
TP_BEGINGNBINITATEARLIER = 0x104, ///< BeginGnbInitAtEarlier
TP_ENDGNBINITATEARLIER = 0x105, ///< EndGnbInitAtEarlier
TP_BEGINAMDCPUEARLY = 0x106, ///< BeginAmdCpuEarly
TP_ENDAMDCPUEARLY = 0x107, ///< EndAmdCpuEarly
TP_BEGINGNBINITATEARLY = 0x108, ///< BeginGnbInitAtEarly
TP_ENDGNBINITATEARLY = 0x109, ///< EndGnbInitAtEarly
TP_BEGINPROCAMDINITENV = 0x10A, ///< BeginProcAmdInitEnv
TP_ENDPROCAMDINITENV = 0x10B, ///< EndProcAmdInitEnv
TP_BEGININITENV = 0x10C, ///< BeginInitEnv
TP_ENDINITENV = 0x10D, ///< EndInitEnv
TP_BEGINGNBINITATENV = 0x10E, ///< BeginGnbInitAtEnv
TP_ENDGNBINITATENV = 0x10F, ///< EndGnbInitAtEnv
TP_BEGINPROCAMDINITLATE = 0x110, ///< BeginProcAmdInitLate
TP_ENDPROCAMDINITLATE = 0x111, ///< EndProcAmdInitLate
TP_BEGINCREATSYSTEMTABLE = 0x112, ///< BeginCreatSystemTable
TP_ENDCREATSYSTEMTABLE = 0x113, ///< EndCreatSystemTable
TP_BEGINDISPATCHCPUFEATURESLATE = 0x114, ///< BeginDispatchCpuFeaturesLate
TP_ENDDISPATCHCPUFEATURESLATE = 0x115, ///< EndDispatchCpuFeaturesLate
TP_BEGINAMDCPULATE = 0x116, ///< BeginAmdCpuLate
TP_ENDAMDCPULATE = 0x117, ///< EndAmdCpuLate
TP_BEGINGNBINITATLATE = 0x118, ///< BeginGnbInitAtLate
TP_ENDGNBINITATLATE = 0x119, ///< EndGnbInitAtLate
TP_BEGINPROCAMDINITMID = 0x11A, ///< BeginProcAmdInitMid
TP_ENDPROCAMDINITMID = 0x11B, ///< EndProcAmdInitMid
TP_BEGINDISPATCHCPUFEATURESMID = 0x11C, ///< BeginDispatchCpuFeaturesMid
TP_ENDDISPATCHCPUFEATURESMID = 0x11D, ///< EndDispatchCpuFeaturesMid
TP_BEGININITMID = 0x11E, ///< BeginInitMid
TP_ENDINITMID = 0x11F, ///< EndInitMid
TP_BEGINGNBINITATMID = 0x120, ///< BeginGnbInitAtMid
TP_ENDGNBINITATMID = 0x121, ///< EndGnbInitAtMid
TP_BEGINPROCAMDINITPOST = 0x122, ///< BeginProcAmdInitPost
TP_ENDPROCAMDINITPOST = 0x123, ///< EndProcAmdInitPost
TP_BEGINGNBINITATPOST = 0x124, ///< BeginGnbInitAtPost
TP_ENDGNBINITATPOST = 0x125, ///< EndGnbInitAtPost
TP_BEGINAMDMEMAUTO = 0x126, ///< BeginAmdMemAuto
TP_ENDAMDMEMAUTO = 0x127, ///< EndAmdMemAuto
TP_BEGINAMDCPUPOST = 0x128, ///< BeginAmdCpuPost
TP_ENDAMDCPUPOST = 0x129, ///< EndAmdCpuPost
TP_BEGINGNBINITATPOSTAFTERDRAM = 0x12A, ///< BeginGnbInitAtPostAfterDram
TP_ENDGNBINITATPOSTAFTERDRAM = 0x12B, ///< EndGnbInitAtPostAfterDram
TP_BEGINPROCAMDINITRESET = 0x12C, ///< BeginProcAmdInitReset
TP_ENDPROCAMDINITRESET = 0x12D, ///< EndProcAmdInitReset
TP_BEGININITRESET = 0x12E, ///< BeginInitReset
TP_ENDINITRESET = 0x12F, ///< EndInitReset
TP_BEGINHTINITRESET = 0x130, ///< BeginHtInitReset
TP_ENDHTINITRESET = 0x131, ///< EndHtInitReset
TP_BEGINPROCAMDINITRESUME = 0x132, ///< BeginProcAmdInitResume
TP_ENDPROCAMDINITRESUME = 0x133, ///< EndProcAmdInitResume
TP_BEGINAMDMEMS3RESUME = 0x134, ///< BeginAmdMemS3Resume
TP_ENDAMDMEMS3RESUME = 0x135, ///< EndAmdMemS3Resume
TP_BEGINDISPATCHCPUFEATURESS3RESUME = 0x136, ///< BeginDispatchCpuFeaturesS3Resume
TP_ENDDISPATCHCPUFEATURESS3RESUME = 0x137, ///< EndDispatchCpuFeaturesS3Resume
TP_BEGINSETCORESTSCFREQSEL = 0x138, ///< BeginSetCoresTscFreqSel
TP_ENDSETCORESTSCFREQSEL = 0x139, ///< EndSetCoresTscFreqSel
TP_BEGINMEMFMCTMEMCLR_INIT = 0x13A, ///< BeginMemFMctMemClr_Init
TP_ENDNMEMFMCTMEMCLR_INIT = 0x13B, ///< EndnMemFMctMemClr_Init
TP_BEGINMEMBEFOREMEMDATAINIT = 0x13C, ///< BeginMemBeforeMemDataInit
TP_ENDMEMBEFOREMEMDATAINIT = 0x13D, ///< EndMemBeforeMemDataInit
TP_BEGINPROCAMDMEMAUTO = 0x13E, ///< BeginProcAmdMemAuto
TP_ENDPROCAMDMEMAUTO = 0x13F, ///< EndProcAmdMemAuto
TP_BEGINMEMMFLOWC32 = 0x140, ///< BeginMemMFlowC32
TP_ENDMEMMFLOWC32 = 0x141, ///< EndMemMFlowC32
TP_BEGINMEMINITIALIZEMCT = 0x142, ///< BeginMemInitializeMCT
TP_ENDMEMINITIALIZEMCT = 0x143, ///< EndMemInitializeMCT
TP_BEGINMEMSYSTEMMEMORYMAPPING = 0x144, ///< BeginMemSystemMemoryMapping
TP_ENDMEMSYSTEMMEMORYMAPPING = 0x145, ///< EndMemSystemMemoryMapping
TP_BEGINMEMDRAMTRAINING = 0x146, ///< BeginMemDramTraining
TP_ENDMEMDRAMTRAINING = 0x147, ///< EndMemDramTraining
TP_BEGINMEMOTHERTIMING = 0x148, ///< BeginMemOtherTiming
TP_ENDMEMOTHERTIMING = 0x149, ///< EndMemOtherTiming
TP_BEGINMEMUMAMEMTYPING = 0x14A, ///< BeginMemUMAMemTyping
TP_ENDMEMUMAMEMTYPING = 0x14B, ///< EndMemUMAMemTyping
TP_BEGINMEMMEMCLR = 0x14C, ///< BeginMemMemClr
TP_ENDMEMMEMCLR = 0x14D, ///< EndMemMemClr
TP_BEGINMEMMFLOWTN = 0x14E, ///< BeginMemMFlowTN
TP_ENDMEMMFLOWTN = 0x14F, ///< EndMemMFlowTN
TP_BEGINAGESAHOOKBEFOREDRAMINIT = 0x150, ///< BeginAgesaHookBeforeDramInit
TP_ENDAGESAHOOKBEFOREDRAMINIT = 0x151, ///< EndAgesaHookBeforeDramInit
TP_BEGINPROCMEMDRAMTRAINING = 0x152, ///< BeginProcMemDramTraining
TP_ENDPROCMEMDRAMTRAINING = 0x153, ///< EndProcMemDramTraining
TP_BEGINGNBINITATS3SAVE = 0x154, ///< BeginGnbInitAtS3Save
TP_ENDGNBINITATS3SAVE = 0x155, ///< EndGnbInitAtS3Save
TP_BEGINGNBLOADSCSDATA = 0x156, ///< BeginGnbLoadScsData
TP_ENDGNBLOADSCSDATA = 0x157, ///< EndGnbLoadScsData
TP_BEGINGNBPCIETRAINING = 0x158, ///< BeginGnbPcieTraining
TP_ENDGNBPCIETRAINING = 0x159, ///< EndGnbPcieTraining
IDS_TP_END ///< End of IDS TP list
} IDS_PERF_DATA;
#endif

89
src/vendorcode/amd/agesa/f16kb/Include/OptionCdit.h
View File

@ -1,89 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD CDIT option API.
*
* Contains structures and values used to control the CDIT option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_CDIT_H_
#define _OPTION_CDIT_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/**
* Create the ACPI Component Locality Distance Information Table.
*
*/
typedef AGESA_STATUS OPTION_CDIT_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfig,
OUT VOID **CditPtr
);
#define CDIT_STRUCT_VERSION 0x01
/// The Option Configuration of CDIT
typedef struct {
UINT16 OptCditVersion; ///< The version number of CDIT
OPTION_CDIT_FEATURE *CditFeature; ///< The Option Feature of CDIT
UINT8 OemIdString[6]; ///< Configurable OEM Id
UINT8 OemTableIdString[8]; ///< Configurable OEM Table Id
} OPTION_CDIT_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_CDIT_H_

545
src/vendorcode/amd/agesa/f16kb/Include/OptionCpuSpecificServicesInstallReset.h
View File

@ -1,545 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of CPU specific services support
*
* This file resets and generates default services of CPU specific services.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Include
* @e \$Revision: 85962 $ @e \$Date: 2013-01-14 20:12:29 -0600 (Mon, 14 Jan 2013) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
//
// Undefine service table name
//
#undef CpuSrvcTableName
//
// Definitions types of a service to undefine
//
// * CpuSrvc<ServiceName>
// * DfltCpuSrvc<ServiceName>
// * DfltAssertCpuSrvc<ServiceName>
// * OvrdDfltCpuSrvc<ServiceName>
// * OvrdDfltAssertCpuSrvc<ServiceName>
// * FinalDfltCpuSrvc<ServiceName>
// * FinalDfltAssertCpuSrvc<ServiceName>
// * FinalCpuSrvc<ServiceName>
//
//
// Reset default services definitions
//
#undef CpuSrvcRevision
#undef CpuSrvcDisablePstate
#undef CpuSrvcTransitionPstate
#undef CpuSrvcGetProcIddMax
#undef CpuSrvcGetTscRate
#undef CpuSrvcGetCurrentNbFrequency
#undef CpuSrvcGetMinMaxNbFrequency
#undef CpuSrvcGetNbPstateInfo
#undef CpuSrvcIsNbCofInitNeeded
#undef CpuSrvcGetNbIddMax
#undef CpuSrvcLaunchApCore
#undef CpuSrvcGetNumberOfPhysicalCores
#undef CpuSrvcGetApMailboxFromHardware
#undef CpuSrvcSetApCoreNumber
#undef CpuSrvcGetApCoreNumber
#undef CpuSrvcTransferApCoreNumber
#undef CpuSrvcGetStoredNodeNumber
#undef CpuSrvcCoreIdPositionInInitialApicId
#undef CpuSrvcSaveFeatures
#undef CpuSrvcWriteFeatures
#undef CpuSrvcSetWarmResetFlag
#undef CpuSrvcGetWarmResetFlag
#undef CpuSrvcGetBrandString1
#undef CpuSrvcGetBrandString2
#undef CpuSrvcGetMicroCodePatchesStruct
#undef CpuSrvcGetMicrocodeEquivalenceTable
#undef CpuSrvcGetCacheInfo
#undef CpuSrvcGetSysPmTableStruct
#undef CpuSrvcGetWheaInitData
#undef CpuSrvcGetPlatformTypeSpecificInfo
#undef CpuSrvcIsNbPstateEnabled
#undef CpuSrvcNextLinkHasHtPhyFeats
#undef CpuSrvcSetHtPhyRegister
#undef CpuSrvcGetNextHtLinkFeatures
#undef CpuSrvcRegisterTableList
#undef CpuSrvcTableEntryTypeDescriptors
#undef CpuSrvcPackageLinkMap
#undef CpuSrvcComputeUnitMap
#undef CpuSrvcInitCacheDisabled
#undef CpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
#undef CpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
#undef CpuSrvcPatchLoaderIsSharedByCU
#undef DfltCpuSrvcRevision
#undef DfltCpuSrvcDisablePstate
#undef DfltCpuSrvcTransitionPstate
#undef DfltCpuSrvcGetProcIddMax
#undef DfltCpuSrvcGetTscRate
#undef DfltCpuSrvcGetCurrentNbFrequency
#undef DfltCpuSrvcGetMinMaxNbFrequency
#undef DfltCpuSrvcGetNbPstateInfo
#undef DfltCpuSrvcIsNbCofInitNeeded
#undef DfltCpuSrvcGetNbIddMax
#undef DfltCpuSrvcLaunchApCore
#undef DfltCpuSrvcGetNumberOfPhysicalCores
#undef DfltCpuSrvcGetApMailboxFromHardware
#undef DfltCpuSrvcSetApCoreNumber
#undef DfltCpuSrvcGetApCoreNumber
#undef DfltCpuSrvcTransferApCoreNumber
#undef DfltCpuSrvcGetStoredNodeNumber
#undef DfltCpuSrvcCoreIdPositionInInitialApicId
#undef DfltCpuSrvcSaveFeatures
#undef DfltCpuSrvcWriteFeatures
#undef DfltCpuSrvcSetWarmResetFlag
#undef DfltCpuSrvcGetWarmResetFlag
#undef DfltCpuSrvcGetBrandString1
#undef DfltCpuSrvcGetBrandString2
#undef DfltCpuSrvcGetMicroCodePatchesStruct
#undef DfltCpuSrvcGetMicrocodeEquivalenceTable
#undef DfltCpuSrvcGetCacheInfo
#undef DfltCpuSrvcGetSysPmTableStruct
#undef DfltCpuSrvcGetWheaInitData
#undef DfltCpuSrvcGetPlatformTypeSpecificInfo
#undef DfltCpuSrvcIsNbPstateEnabled
#undef DfltCpuSrvcNextLinkHasHtPhyFeats
#undef DfltCpuSrvcSetHtPhyRegister
#undef DfltCpuSrvcGetNextHtLinkFeatures
#undef DfltCpuSrvcRegisterTableList
#undef DfltCpuSrvcTableEntryTypeDescriptors
#undef DfltCpuSrvcPackageLinkMap
#undef DfltCpuSrvcComputeUnitMap
#undef DfltCpuSrvcInitCacheDisabled
#undef DfltCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
#undef DfltCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
#undef DfltCpuSrvcPatchLoaderIsSharedByCU
#undef DfltAssertCpuSrvcRevision
#undef DfltAssertCpuSrvcDisablePstate
#undef DfltAssertCpuSrvcTransitionPstate
#undef DfltAssertCpuSrvcGetProcIddMax
#undef DfltAssertCpuSrvcGetTscRate
#undef DfltAssertCpuSrvcGetCurrentNbFrequency
#undef DfltAssertCpuSrvcGetMinMaxNbFrequency
#undef DfltAssertCpuSrvcGetNbPstateInfo
#undef DfltAssertCpuSrvcIsNbCofInitNeeded
#undef DfltAssertCpuSrvcGetNbIddMax
#undef DfltAssertCpuSrvcLaunchApCore
#undef DfltAssertCpuSrvcGetNumberOfPhysicalCores
#undef DfltAssertCpuSrvcGetApMailboxFromHardware
#undef DfltAssertCpuSrvcSetApCoreNumber
#undef DfltAssertCpuSrvcGetApCoreNumber
#undef DfltAssertCpuSrvcTransferApCoreNumber
#undef DfltAssertCpuSrvcGetStoredNodeNumber
#undef DfltAssertCpuSrvcCoreIdPositionInInitialApicId
#undef DfltAssertCpuSrvcSaveFeatures
#undef DfltAssertCpuSrvcWriteFeatures
#undef DfltAssertCpuSrvcSetWarmResetFlag
#undef DfltAssertCpuSrvcGetWarmResetFlag
#undef DfltAssertCpuSrvcGetBrandString1
#undef DfltAssertCpuSrvcGetBrandString2
#undef DfltAssertCpuSrvcGetMicroCodePatchesStruct
#undef DfltAssertCpuSrvcGetMicrocodeEquivalenceTable
#undef DfltAssertCpuSrvcGetCacheInfo
#undef DfltAssertCpuSrvcGetSysPmTableStruct
#undef DfltAssertCpuSrvcGetWheaInitData
#undef DfltAssertCpuSrvcGetPlatformTypeSpecificInfo
#undef DfltAssertCpuSrvcIsNbPstateEnabled
#undef DfltAssertCpuSrvcNextLinkHasHtPhyFeats
#undef DfltAssertCpuSrvcSetHtPhyRegister
#undef DfltAssertCpuSrvcGetNextHtLinkFeatures
#undef DfltAssertCpuSrvcRegisterTableList
#undef DfltAssertCpuSrvcTableEntryTypeDescriptors
#undef DfltAssertCpuSrvcPackageLinkMap
#undef DfltAssertCpuSrvcComputeUnitMap
#undef DfltAssertCpuSrvcInitCacheDisabled
#undef DfltAssertCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
#undef DfltAssertCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
#undef DfltAssertCpuSrvcPatchLoaderIsSharedByCU
#undef OvrdDfltCpuSrvcRevision
#undef OvrdDfltCpuSrvcDisablePstate
#undef OvrdDfltCpuSrvcTransitionPstate
#undef OvrdDfltCpuSrvcGetProcIddMax
#undef OvrdDfltCpuSrvcGetTscRate
#undef OvrdDfltCpuSrvcGetCurrentNbFrequency
#undef OvrdDfltCpuSrvcGetMinMaxNbFrequency
#undef OvrdDfltCpuSrvcGetNbPstateInfo
#undef OvrdDfltCpuSrvcIsNbCofInitNeeded
#undef OvrdDfltCpuSrvcGetNbIddMax
#undef OvrdDfltCpuSrvcLaunchApCore
#undef OvrdDfltCpuSrvcGetNumberOfPhysicalCores
#undef OvrdDfltCpuSrvcGetApMailboxFromHardware
#undef OvrdDfltCpuSrvcSetApCoreNumber
#undef OvrdDfltCpuSrvcGetApCoreNumber
#undef OvrdDfltCpuSrvcTransferApCoreNumber
#undef OvrdDfltCpuSrvcGetStoredNodeNumber
#undef OvrdDfltCpuSrvcCoreIdPositionInInitialApicId
#undef OvrdDfltCpuSrvcSaveFeatures
#undef OvrdDfltCpuSrvcWriteFeatures
#undef OvrdDfltCpuSrvcSetWarmResetFlag
#undef OvrdDfltCpuSrvcGetWarmResetFlag
#undef OvrdDfltCpuSrvcGetBrandString1
#undef OvrdDfltCpuSrvcGetBrandString2
#undef OvrdDfltCpuSrvcGetMicroCodePatchesStruct
#undef OvrdDfltCpuSrvcGetMicrocodeEquivalenceTable
#undef OvrdDfltCpuSrvcGetCacheInfo
#undef OvrdDfltCpuSrvcGetSysPmTableStruct
#undef OvrdDfltCpuSrvcGetWheaInitData
#undef OvrdDfltCpuSrvcGetPlatformTypeSpecificInfo
#undef OvrdDfltCpuSrvcIsNbPstateEnabled
#undef OvrdDfltCpuSrvcNextLinkHasHtPhyFeats
#undef OvrdDfltCpuSrvcSetHtPhyRegister
#undef OvrdDfltCpuSrvcGetNextHtLinkFeatures
#undef OvrdDfltCpuSrvcRegisterTableList
#undef OvrdDfltCpuSrvcTableEntryTypeDescriptors
#undef OvrdDfltCpuSrvcPackageLinkMap
#undef OvrdDfltCpuSrvcComputeUnitMap
#undef OvrdDfltCpuSrvcInitCacheDisabled
#undef OvrdDfltCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
#undef OvrdDfltCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
#undef OvrdDfltCpuSrvcPatchLoaderIsSharedByCU
#undef OvrdDfltAssertCpuSrvcRevision
#undef OvrdDfltAssertCpuSrvcDisablePstate
#undef OvrdDfltAssertCpuSrvcTransitionPstate
#undef OvrdDfltAssertCpuSrvcGetProcIddMax
#undef OvrdDfltAssertCpuSrvcGetTscRate
#undef OvrdDfltAssertCpuSrvcGetCurrentNbFrequency
#undef OvrdDfltAssertCpuSrvcGetMinMaxNbFrequency
#undef OvrdDfltAssertCpuSrvcGetNbPstateInfo
#undef OvrdDfltAssertCpuSrvcIsNbCofInitNeeded
#undef OvrdDfltAssertCpuSrvcGetNbIddMax
#undef OvrdDfltAssertCpuSrvcLaunchApCore
#undef OvrdDfltAssertCpuSrvcGetNumberOfPhysicalCores
#undef OvrdDfltAssertCpuSrvcGetApMailboxFromHardware
#undef OvrdDfltAssertCpuSrvcSetApCoreNumber
#undef OvrdDfltAssertCpuSrvcGetApCoreNumber
#undef OvrdDfltAssertCpuSrvcTransferApCoreNumber
#undef OvrdDfltAssertCpuSrvcGetStoredNodeNumber
#undef OvrdDfltAssertCpuSrvcCoreIdPositionInInitialApicId
#undef OvrdDfltAssertCpuSrvcSaveFeatures
#undef OvrdDfltAssertCpuSrvcWriteFeatures
#undef OvrdDfltAssertCpuSrvcSetWarmResetFlag
#undef OvrdDfltAssertCpuSrvcGetWarmResetFlag
#undef OvrdDfltAssertCpuSrvcGetBrandString1
#undef OvrdDfltAssertCpuSrvcGetBrandString2
#undef OvrdDfltAssertCpuSrvcGetMicroCodePatchesStruct
#undef OvrdDfltAssertCpuSrvcGetMicrocodeEquivalenceTable
#undef OvrdDfltAssertCpuSrvcGetCacheInfo
#undef OvrdDfltAssertCpuSrvcGetSysPmTableStruct
#undef OvrdDfltAssertCpuSrvcGetWheaInitData
#undef OvrdDfltAssertCpuSrvcGetPlatformTypeSpecificInfo
#undef OvrdDfltAssertCpuSrvcIsNbPstateEnabled
#undef OvrdDfltAssertCpuSrvcNextLinkHasHtPhyFeats
#undef OvrdDfltAssertCpuSrvcSetHtPhyRegister
#undef OvrdDfltAssertCpuSrvcGetNextHtLinkFeatures
#undef OvrdDfltAssertCpuSrvcRegisterTableList
#undef OvrdDfltAssertCpuSrvcTableEntryTypeDescriptors
#undef OvrdDfltAssertCpuSrvcPackageLinkMap
#undef OvrdDfltAssertCpuSrvcComputeUnitMap
#undef OvrdDfltAssertCpuSrvcInitCacheDisabled
#undef OvrdDfltAssertCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
#undef OvrdDfltAssertCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
#undef OvrdDfltAssertCpuSrvcPatchLoaderIsSharedByCU
#undef FinalDfltCpuSrvcRevision
#undef FinalDfltCpuSrvcDisablePstate
#undef FinalDfltCpuSrvcTransitionPstate
#undef FinalDfltCpuSrvcGetProcIddMax
#undef FinalDfltCpuSrvcGetTscRate
#undef FinalDfltCpuSrvcGetCurrentNbFrequency
#undef FinalDfltCpuSrvcGetMinMaxNbFrequency
#undef FinalDfltCpuSrvcGetNbPstateInfo
#undef FinalDfltCpuSrvcIsNbCofInitNeeded
#undef FinalDfltCpuSrvcGetNbIddMax
#undef FinalDfltCpuSrvcLaunchApCore
#undef FinalDfltCpuSrvcGetNumberOfPhysicalCores
#undef FinalDfltCpuSrvcGetApMailboxFromHardware
#undef FinalDfltCpuSrvcSetApCoreNumber
#undef FinalDfltCpuSrvcGetApCoreNumber
#undef FinalDfltCpuSrvcTransferApCoreNumber
#undef FinalDfltCpuSrvcGetStoredNodeNumber
#undef FinalDfltCpuSrvcCoreIdPositionInInitialApicId
#undef FinalDfltCpuSrvcSaveFeatures
#undef FinalDfltCpuSrvcWriteFeatures
#undef FinalDfltCpuSrvcSetWarmResetFlag
#undef FinalDfltCpuSrvcGetWarmResetFlag
#undef FinalDfltCpuSrvcGetBrandString1
#undef FinalDfltCpuSrvcGetBrandString2
#undef FinalDfltCpuSrvcGetMicroCodePatchesStruct
#undef FinalDfltCpuSrvcGetMicrocodeEquivalenceTable
#undef FinalDfltCpuSrvcGetCacheInfo
#undef FinalDfltCpuSrvcGetSysPmTableStruct
#undef FinalDfltCpuSrvcGetWheaInitData
#undef FinalDfltCpuSrvcGetPlatformTypeSpecificInfo
#undef FinalDfltCpuSrvcIsNbPstateEnabled
#undef FinalDfltCpuSrvcNextLinkHasHtPhyFeats
#undef FinalDfltCpuSrvcSetHtPhyRegister
#undef FinalDfltCpuSrvcGetNextHtLinkFeatures
#undef FinalDfltCpuSrvcRegisterTableList
#undef FinalDfltCpuSrvcTableEntryTypeDescriptors
#undef FinalDfltCpuSrvcPackageLinkMap
#undef FinalDfltCpuSrvcComputeUnitMap
#undef FinalDfltCpuSrvcInitCacheDisabled
#undef FinalDfltCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
#undef FinalDfltCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
#undef FinalDfltCpuSrvcPatchLoaderIsSharedByCU
#undef FinalDfltAssertCpuSrvcRevision
#undef FinalDfltAssertCpuSrvcDisablePstate
#undef FinalDfltAssertCpuSrvcTransitionPstate
#undef FinalDfltAssertCpuSrvcGetProcIddMax
#undef FinalDfltAssertCpuSrvcGetTscRate
#undef FinalDfltAssertCpuSrvcGetCurrentNbFrequency
#undef FinalDfltAssertCpuSrvcGetMinMaxNbFrequency
#undef FinalDfltAssertCpuSrvcGetNbPstateInfo
#undef FinalDfltAssertCpuSrvcIsNbCofInitNeeded
#undef FinalDfltAssertCpuSrvcGetNbIddMax
#undef FinalDfltAssertCpuSrvcLaunchApCore
#undef FinalDfltAssertCpuSrvcGetNumberOfPhysicalCores
#undef FinalDfltAssertCpuSrvcGetApMailboxFromHardware
#undef FinalDfltAssertCpuSrvcSetApCoreNumber
#undef FinalDfltAssertCpuSrvcGetApCoreNumber
#undef FinalDfltAssertCpuSrvcTransferApCoreNumber
#undef FinalDfltAssertCpuSrvcGetStoredNodeNumber
#undef FinalDfltAssertCpuSrvcCoreIdPositionInInitialApicId
#undef FinalDfltAssertCpuSrvcSaveFeatures
#undef FinalDfltAssertCpuSrvcWriteFeatures
#undef FinalDfltAssertCpuSrvcSetWarmResetFlag
#undef FinalDfltAssertCpuSrvcGetWarmResetFlag
#undef FinalDfltAssertCpuSrvcGetBrandString1
#undef FinalDfltAssertCpuSrvcGetBrandString2
#undef FinalDfltAssertCpuSrvcGetMicroCodePatchesStruct
#undef FinalDfltAssertCpuSrvcGetMicrocodeEquivalenceTable
#undef FinalDfltAssertCpuSrvcGetCacheInfo
#undef FinalDfltAssertCpuSrvcGetSysPmTableStruct
#undef FinalDfltAssertCpuSrvcGetWheaInitData
#undef FinalDfltAssertCpuSrvcGetPlatformTypeSpecificInfo
#undef FinalDfltAssertCpuSrvcIsNbPstateEnabled
#undef FinalDfltAssertCpuSrvcNextLinkHasHtPhyFeats
#undef FinalDfltAssertCpuSrvcSetHtPhyRegister
#undef FinalDfltAssertCpuSrvcGetNextHtLinkFeatures
#undef FinalDfltAssertCpuSrvcRegisterTableList
#undef FinalDfltAssertCpuSrvcTableEntryTypeDescriptors
#undef FinalDfltAssertCpuSrvcPackageLinkMap
#undef FinalDfltAssertCpuSrvcComputeUnitMap
#undef FinalDfltAssertCpuSrvcInitCacheDisabled
#undef FinalDfltAssertCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
#undef FinalDfltAssertCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
#undef FinalDfltAssertCpuSrvcPatchLoaderIsSharedByCU
#undef FinalCpuSrvcRevision
#undef FinalCpuSrvcDisablePstate
#undef FinalCpuSrvcTransitionPstate
#undef FinalCpuSrvcGetProcIddMax
#undef FinalCpuSrvcGetTscRate
#undef FinalCpuSrvcGetCurrentNbFrequency
#undef FinalCpuSrvcGetMinMaxNbFrequency
#undef FinalCpuSrvcGetNbPstateInfo
#undef FinalCpuSrvcIsNbCofInitNeeded
#undef FinalCpuSrvcGetNbIddMax
#undef FinalCpuSrvcLaunchApCore
#undef FinalCpuSrvcGetNumberOfPhysicalCores
#undef FinalCpuSrvcGetApMailboxFromHardware
#undef FinalCpuSrvcSetApCoreNumber
#undef FinalCpuSrvcGetApCoreNumber
#undef FinalCpuSrvcTransferApCoreNumber
#undef FinalCpuSrvcGetStoredNodeNumber
#undef FinalCpuSrvcCoreIdPositionInInitialApicId
#undef FinalCpuSrvcSaveFeatures
#undef FinalCpuSrvcWriteFeatures
#undef FinalCpuSrvcSetWarmResetFlag
#undef FinalCpuSrvcGetWarmResetFlag
#undef FinalCpuSrvcGetBrandString1
#undef FinalCpuSrvcGetBrandString2
#undef FinalCpuSrvcGetMicroCodePatchesStruct
#undef FinalCpuSrvcGetMicrocodeEquivalenceTable
#undef FinalCpuSrvcGetCacheInfo
#undef FinalCpuSrvcGetSysPmTableStruct
#undef FinalCpuSrvcGetWheaInitData
#undef FinalCpuSrvcGetPlatformTypeSpecificInfo
#undef FinalCpuSrvcIsNbPstateEnabled
#undef FinalCpuSrvcNextLinkHasHtPhyFeats
#undef FinalCpuSrvcSetHtPhyRegister
#undef FinalCpuSrvcGetNextHtLinkFeatures
#undef FinalCpuSrvcRegisterTableList
#undef FinalCpuSrvcTableEntryTypeDescriptors
#undef FinalCpuSrvcPackageLinkMap
#undef FinalCpuSrvcComputeUnitMap
#undef FinalCpuSrvcInitCacheDisabled
#undef FinalCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
#undef FinalCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
#undef FinalCpuSrvcPatchLoaderIsSharedByCU
//
// Define null CPU specific services - no redefinition is expected.
//
#define NullCpuSrvcRevision (UINT16) 0
#define NullCpuSrvcDisablePstate (PF_CPU_DISABLE_PSTATE) CommonReturnAgesaSuccess
#define NullCpuSrvcTransitionPstate (PF_CPU_TRANSITION_PSTATE) CommonReturnAgesaSuccess
#define NullCpuSrvcGetProcIddMax (PF_CPU_GET_IDD_MAX) CommonReturnFalse
#define NullCpuSrvcGetTscRate (PF_CPU_GET_TSC_RATE) CommonReturnAgesaSuccess
#define NullCpuSrvcGetCurrentNbFrequency (PF_CPU_GET_NB_FREQ) CommonReturnAgesaError
#define NullCpuSrvcGetMinMaxNbFrequency (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonReturnAgesaError
#define NullCpuSrvcGetNbPstateInfo (PF_CPU_GET_NB_PSTATE_INFO) CommonReturnFalse
#define NullCpuSrvcIsNbCofInitNeeded (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnAgesaSuccess
#define NullCpuSrvcGetNbIddMax (PF_CPU_GET_NB_IDD_MAX) CommonReturnFalse
#define NullCpuSrvcLaunchApCore (PF_CPU_AP_INITIAL_LAUNCH) CommonReturnFalse
#define NullCpuSrvcGetNumberOfPhysicalCores (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonReturnZero8
#define NullCpuSrvcGetApMailboxFromHardware (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonReturnAgesaSuccess
#define NullCpuSrvcSetApCoreNumber (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid
#define NullCpuSrvcGetApCoreNumber (PF_CPU_GET_AP_CORE_NUMBER) CommonReturnOne32
#define NullCpuSrvcTransferApCoreNumber (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid
#define NullCpuSrvcGetStoredNodeNumber (PF_CPU_GET_STORED_NODE_NUMBER) CommonReturnZero32
#define NullCpuSrvcCoreIdPositionInInitialApicId (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonReturnAgesaSuccess
#define NullCpuSrvcSaveFeatures (PF_CPU_SAVE_FEATURES) CommonVoid
#define NullCpuSrvcWriteFeatures (PF_CPU_WRITE_FEATURES) CommonVoid
#define NullCpuSrvcSetWarmResetFlag (PF_CPU_SET_WARM_RESET_FLAG) CommonReturnAgesaSuccess
#define NullCpuSrvcGetWarmResetFlag (PF_CPU_GET_WARM_RESET_FLAG) CommonReturnAgesaSuccess
#define NullCpuSrvcGetBrandString1 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) GetEmptyArray
#define NullCpuSrvcGetBrandString2 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) GetEmptyArray
#define NullCpuSrvcGetMicroCodePatchesStruct (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) GetEmptyArray
#define NullCpuSrvcGetMicrocodeEquivalenceTable (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) GetEmptyArray
#define NullCpuSrvcGetCacheInfo (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) GetEmptyArray
#define NullCpuSrvcGetSysPmTableStruct (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) GetEmptyArray
#define NullCpuSrvcGetWheaInitData (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) GetEmptyArray
#define NullCpuSrvcGetPlatformTypeSpecificInfo (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess
#define NullCpuSrvcIsNbPstateEnabled (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse
#define NullCpuSrvcNextLinkHasHtPhyFeats (PF_NEXT_LINK_HAS_HTPHY_FEATS) CommonReturnFalse
#define NullCpuSrvcSetHtPhyRegister (PF_SET_HT_PHY_REGISTER) CommonVoid
#define NullCpuSrvcGetNextHtLinkFeatures (PF_GET_NEXT_HT_LINK_FEATURES) CommonVoid
#define NullCpuSrvcRegisterTableList (REGISTER_TABLE **) NULL
#define NullCpuSrvcTableEntryTypeDescriptors (TABLE_ENTRY_TYPE_DESCRIPTOR *) NULL
#define NullCpuSrvcPackageLinkMap (PACKAGE_HTLINK_MAP) NULL
#define NullCpuSrvcComputeUnitMap (COMPUTE_UNIT_MAP *) NULL
#define NullCpuSrvcInitCacheDisabled (FAMILY_CACHE_INIT_POLICY) InitCacheDisabled
#define NullCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable (PF_GET_EARLY_INIT_TABLE) CommonVoid
#define NullCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable (PF_GET_EARLY_INIT_TABLE) CommonVoid
#define NullCpuSrvcPatchLoaderIsSharedByCU (BOOLEAN) FALSE
//
// Define default cpu specific services assertion if possible
//
#define DfltAssertCpuSrvcRevision NullCpuSrvcRevision
#define DfltAssertCpuSrvcDisablePstate (PF_CPU_DISABLE_PSTATE) CommonAssert
#define DfltAssertCpuSrvcTransitionPstate (PF_CPU_TRANSITION_PSTATE) CommonAssert
#define DfltAssertCpuSrvcGetProcIddMax (PF_CPU_GET_IDD_MAX) CommonAssert
#define DfltAssertCpuSrvcGetTscRate (PF_CPU_GET_TSC_RATE) CommonAssert
#define DfltAssertCpuSrvcGetCurrentNbFrequency (PF_CPU_GET_NB_FREQ) CommonAssert
#define DfltAssertCpuSrvcGetMinMaxNbFrequency (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert
#define DfltAssertCpuSrvcGetNbPstateInfo (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert
#define DfltAssertCpuSrvcIsNbCofInitNeeded (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert
#define DfltAssertCpuSrvcGetNbIddMax (PF_CPU_GET_NB_IDD_MAX) CommonAssert
#define DfltAssertCpuSrvcLaunchApCore (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert
#define DfltAssertCpuSrvcGetNumberOfPhysicalCores (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert
#define DfltAssertCpuSrvcGetApMailboxFromHardware (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert
#define DfltAssertCpuSrvcSetApCoreNumber (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert
#define DfltAssertCpuSrvcGetApCoreNumber (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert
#define DfltAssertCpuSrvcTransferApCoreNumber (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert
#define DfltAssertCpuSrvcGetStoredNodeNumber (PF_CPU_GET_STORED_NODE_NUMBER) CommonAssert
#define DfltAssertCpuSrvcCoreIdPositionInInitialApicId (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert
#define DfltAssertCpuSrvcSaveFeatures (PF_CPU_SAVE_FEATURES) CommonAssert
#define DfltAssertCpuSrvcWriteFeatures (PF_CPU_WRITE_FEATURES) CommonAssert
#define DfltAssertCpuSrvcSetWarmResetFlag (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert
#define DfltAssertCpuSrvcGetWarmResetFlag (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert
#define DfltAssertCpuSrvcGetBrandString1 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert
#define DfltAssertCpuSrvcGetBrandString2 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert
#define DfltAssertCpuSrvcGetMicroCodePatchesStruct (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert
#define DfltAssertCpuSrvcGetMicrocodeEquivalenceTable (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert
#define DfltAssertCpuSrvcGetCacheInfo (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert
#define DfltAssertCpuSrvcGetSysPmTableStruct (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert
#define DfltAssertCpuSrvcGetWheaInitData (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert
#define DfltAssertCpuSrvcGetPlatformTypeSpecificInfo (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert
#define DfltAssertCpuSrvcIsNbPstateEnabled (PF_IS_NB_PSTATE_ENABLED) CommonAssert
#define DfltAssertCpuSrvcNextLinkHasHtPhyFeats (PF_NEXT_LINK_HAS_HTPHY_FEATS) CommonAssert
#define DfltAssertCpuSrvcSetHtPhyRegister (PF_SET_HT_PHY_REGISTER) CommonAssert
#define DfltAssertCpuSrvcGetNextHtLinkFeatures (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert
#define DfltAssertCpuSrvcRegisterTableList NullCpuSrvcRegisterTableList
#define DfltAssertCpuSrvcTableEntryTypeDescriptors NullCpuSrvcTableEntryTypeDescriptors
#define DfltAssertCpuSrvcPackageLinkMap NullCpuSrvcPackageLinkMap
#define DfltAssertCpuSrvcComputeUnitMap NullCpuSrvcComputeUnitMap
#define DfltAssertCpuSrvcInitCacheDisabled (FAMILY_CACHE_INIT_POLICY) InitCacheDisabled
#define DfltAssertCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable (PF_GET_EARLY_INIT_TABLE) CommonAssert
#define DfltAssertCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable (PF_GET_EARLY_INIT_TABLE) CommonAssert
#define DfltAssertCpuSrvcPatchLoaderIsSharedByCU NullCpuSrvcPatchLoaderIsSharedByCU
//
// Define family specific services default when feature is enabled in the build
//
#define DfltCpuSrvcRevision NullCpuSrvcRevision
#define DfltCpuSrvcDisablePstate DfltAssertCpuSrvcDisablePstate
#define DfltCpuSrvcTransitionPstate DfltAssertCpuSrvcTransitionPstate
#define DfltCpuSrvcGetProcIddMax NullCpuSrvcGetProcIddMax
#define DfltCpuSrvcGetTscRate DfltAssertCpuSrvcGetTscRate
#define DfltCpuSrvcGetCurrentNbFrequency DfltAssertCpuSrvcGetCurrentNbFrequency
#define DfltCpuSrvcGetMinMaxNbFrequency NullCpuSrvcGetMinMaxNbFrequency
#define DfltCpuSrvcGetNbPstateInfo NullCpuSrvcGetNbPstateInfo
#define DfltCpuSrvcIsNbCofInitNeeded (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnFalse
#define DfltCpuSrvcGetNbIddMax DfltAssertCpuSrvcGetNbIddMax
#define DfltCpuSrvcLaunchApCore NullCpuSrvcLaunchApCore
#define DfltCpuSrvcGetNumberOfPhysicalCores (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonReturnOne8
#define DfltCpuSrvcGetApMailboxFromHardware DfltAssertCpuSrvcGetApMailboxFromHardware
#define DfltCpuSrvcSetApCoreNumber NullCpuSrvcSetApCoreNumber
#define DfltCpuSrvcGetApCoreNumber NullCpuSrvcGetApCoreNumber
#define DfltCpuSrvcTransferApCoreNumber NullCpuSrvcTransferApCoreNumber
#define DfltCpuSrvcGetStoredNodeNumber NullCpuSrvcGetStoredNodeNumber
#define DfltCpuSrvcCoreIdPositionInInitialApicId (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonReturnOne32
#define DfltCpuSrvcSaveFeatures NullCpuSrvcSaveFeatures
#define DfltCpuSrvcWriteFeatures NullCpuSrvcWriteFeatures
#define DfltCpuSrvcSetWarmResetFlag (PF_CPU_SET_WARM_RESET_FLAG) CommonVoid
#define DfltCpuSrvcGetWarmResetFlag DfltAssertCpuSrvcGetWarmResetFlag
#define DfltCpuSrvcGetBrandString1 NullCpuSrvcGetBrandString1
#define DfltCpuSrvcGetBrandString2 NullCpuSrvcGetBrandString2
#define DfltCpuSrvcGetMicroCodePatchesStruct NullCpuSrvcGetMicroCodePatchesStruct
#define DfltCpuSrvcGetMicrocodeEquivalenceTable NullCpuSrvcGetMicrocodeEquivalenceTable
#define DfltCpuSrvcGetCacheInfo NullCpuSrvcGetCacheInfo
#define DfltCpuSrvcGetSysPmTableStruct NullCpuSrvcGetSysPmTableStruct
#define DfltCpuSrvcGetWheaInitData NullCpuSrvcGetWheaInitData
#define DfltCpuSrvcGetPlatformTypeSpecificInfo NullCpuSrvcGetPlatformTypeSpecificInfo
#define DfltCpuSrvcIsNbPstateEnabled NullCpuSrvcIsNbPstateEnabled
#define DfltCpuSrvcNextLinkHasHtPhyFeats NullCpuSrvcNextLinkHasHtPhyFeats
#define DfltCpuSrvcSetHtPhyRegister NullCpuSrvcSetHtPhyRegister
#define DfltCpuSrvcGetNextHtLinkFeatures (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse
#define DfltCpuSrvcRegisterTableList NullCpuSrvcRegisterTableList
#define DfltCpuSrvcTableEntryTypeDescriptors NullCpuSrvcTableEntryTypeDescriptors
#define DfltCpuSrvcPackageLinkMap NullCpuSrvcPackageLinkMap
#define DfltCpuSrvcComputeUnitMap NullCpuSrvcComputeUnitMap
// NOTE: From CPUs with compute units and moving forward, we use InitCacheEnabled.
#define DfltCpuSrvcInitCacheDisabled (FAMILY_CACHE_INIT_POLICY) InitCacheEnabled
#define DfltCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable NullCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
#define DfltCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable NullCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
#define DfltCpuSrvcPatchLoaderIsSharedByCU NullCpuSrvcPatchLoaderIsSharedByCU

193
src/vendorcode/amd/agesa/f16kb/Include/OptionCrat.h
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@ -1,193 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD CRAT option API.
*
* Contains structures and values used to control the CRAT option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_CRAT_H_
#define _OPTION_CRAT_H_
#include "cpuLateInit.h"
#include "cpuCrat.h"
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_CRAT_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN OUT VOID **CratPtr
);
#define CRAT_STRUCT_VERSION 0x01
/// The Option Configuration of CRAT
typedef struct {
UINT16 OptCratVersion; ///< The version number of CRAT
OPTION_CRAT_FEATURE *CratFeature; ///< The Option Feature of CRAT
UINT8 OemIdString[6]; ///< Configurable OEM Id
UINT8 OemTableIdString[8]; ///< Configurable OEM Table Id
} OPTION_CRAT_CONFIGURATION;
/*---------------------------------------------------------------------------------------*/
/**
* Family specific call to generat CRAT cache affinity structure.
*
* @param[in] CratHeaderStructPtr CRAT header pointer
* @param[in, out] TableEnd The end of CRAT
* @param[in, out] StdHeader Standard Head Pointer
*
*
*/
typedef VOID F_GENERATE_CRAT_CACHE (
IN CRAT_HEADER *CratHeaderStructPtr,
IN OUT UINT8 **TableEnd,
IN AMD_CONFIG_PARAMS *StdHeader
);
/// Reference to a Method.
typedef F_GENERATE_CRAT_CACHE *PF_GENERATE_CRAT_CACHE;
/*---------------------------------------------------------------------------------------*/
/**
* Family specific call to generat CRAT TLB affinity structure.
*
* @param[in] CratHeaderStructPtr CRAT header pointer
* @param[in, out] TableEnd The end of CRAT
* @param[in, out] StdHeader Standard Head Pointer
*
*
*/
typedef VOID F_GENERATE_CRAT_TLB (
IN CRAT_HEADER *CratHeaderStructPtr,
IN OUT UINT8 **TableEnd,
IN AMD_CONFIG_PARAMS *StdHeader
);
/// Reference to a Method.
typedef F_GENERATE_CRAT_TLB *PF_GENERATE_CRAT_TLB;
/**
* Provide the interface to the CRAT Family Specific Services.
*
* Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
* Each supported Family must provide an implementation for all methods in this interface, even if the
* implementation is a CommonReturn().
*/
typedef struct _CRAT_FAMILY_SERVICES {
UINT16 Revision; ///< Interface version
// Public Methods.
PF_GENERATE_CRAT_CACHE generateCratCacheEntry; ///< Method: Family specific call to generat CRAT cache affinity structure
PF_GENERATE_CRAT_TLB generateCratTLBEntry; ///< Method: Family specific call to generat CRAT TLB affinity structure
} CRAT_FAMILY_SERVICES;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
VOID
MakeHSAProcUnitEntry (
IN CRAT_HEADER *CratHeaderStructPtr,
IN OUT UINT8 **TableEnd,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
MakeMemoryEntry (
IN CRAT_HEADER *CratHeaderStructPtr,
IN OUT UINT8 **TableEnd,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
MakeCacheEntry (
IN CRAT_HEADER *CratHeaderStructPtr,
IN OUT UINT8 **TableEnd,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
MakeTLBEntry (
IN CRAT_HEADER *CratHeaderStructPtr,
IN OUT UINT8 **TableEnd,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
/// @todo
//VOID
//MakeFPUEntry (
// IN CRAT_HEADER *CratHeaderStructPtr,
// IN OUT UINT8 **TableEnd,
// IN OUT AMD_CONFIG_PARAMS *StdHeader
// );
/// @todo
//VOID
//MakeIOEntry (
// IN CRAT_HEADER *CratHeaderStructPtr,
// IN OUT UINT8 **TableEnd,
// IN OUT AMD_CONFIG_PARAMS *StdHeader
// );
UINT8 *
AddOneCratEntry (
IN CRAT_ENTRY_TYPE CratEntryType,
IN CRAT_HEADER *CratHeaderStructPtr,
IN OUT UINT8 **TableEnd,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
#endif // _OPTION_CRAT_H_

89
src/vendorcode/amd/agesa/f16kb/Include/OptionDmi.h
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@ -1,89 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD DMI option API.
*
* Contains structures and values used to control the DMI option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_DMI_H_
#define _OPTION_DMI_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_DMI_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN OUT DMI_INFO **DmiPtr
);
typedef AGESA_STATUS OPTION_DMI_RELEASE_BUFFER (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
#define DMI_STRUCT_VERSION 0x01
/// DMI option configuration. Determine the item of structure when compiling.
typedef struct {
UINT16 OptDmiVersion; ///< Dmi version.
OPTION_DMI_FEATURE *DmiFeature; ///< Feature main routine, otherwise dummy.
OPTION_DMI_RELEASE_BUFFER *DmiReleaseBuffer; ///< Release buffer
UINT16 NumEntries; ///< Number of entry.
VOID *((*FamilyList)[]); ///< Family service.
} OPTION_DMI_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_DMI_H_

75
src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hEarlySample.h
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@ -1,75 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Family 16h 'early sample' support
*
* This file defines the required structures for family 16h pre-production processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_FAMILY_16H_EARLY_SAMPLE_H_
#define _OPTION_FAMILY_16H_EARLY_SAMPLE_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*
* Install family 16h model 0x00 - 0x0F Early Sample support
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
#endif // _OPTION_FAMILY_16H_EARLY_SAMPLE_H_

81
src/vendorcode/amd/agesa/f16kb/Include/OptionGfxRecovery.h
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@ -1,81 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD GFX Recovery option API.
*
* Contains structures and values used to control the GfxRecovery option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_GFX_RECOVERY_H_
#define _OPTION_GFX_RECOVERY_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_GFX_RECOVERY_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
#define GFX_RECOVERY_STRUCT_VERSION 0x01
/// The Option Configuration of GFX Recovery
typedef struct {
UINT16 OptGfxRecoveryVersion; ///< The version number of GFX Recovery
OPTION_GFX_RECOVERY_FEATURE *GfxRecoveryFeature; ///< The Option Feature of GFX Recovery
} OPTION_GFX_RECOVERY_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_GFX_RECOVERY_H_

134
src/vendorcode/amd/agesa/f16kb/Include/OptionGnb.h
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@ -1,134 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD ALIB option API.
*
* Contains structures and values used to control the ALIB option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 86709 $ @e \$Date: 2013-01-24 17:39:09 -0600 (Thu, 24 Jan 2013) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_GNB_H_
#define _OPTION_GNB_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_GNB_FEATURE (
IN AMD_CONFIG_PARAMS *StdHeader
);
typedef AGESA_STATUS F_ALIB_UPDATE (
IN OUT VOID *AlibSsdtBuffer,
IN AMD_CONFIG_PARAMS *StdHeader
);
typedef VOID* F_ALIB_GET (
IN AMD_CONFIG_PARAMS *StdHeader
);
/// The Option Configuration
typedef struct {
UINT64 Type; ///< Type
OPTION_GNB_FEATURE *GnbFeature; ///< The GNB Feature
UINT8 TestPoint; ///< The post code for each entry
} OPTION_GNB_CONFIGURATION;
/// The Build time options configuration
typedef struct {
BOOLEAN IgfxModeAsPcieEp; ///< Itegrated Gfx mode Pcie EP or Legacy
BOOLEAN LclkDeepSleepEn; ///< Default for LCLK deep sleep
BOOLEAN LclkDpmEn; ///< Default for LCLK DPM
UINT8 GmcPowerGating; ///< Control GMC power gating
BOOLEAN SmuSclkClockGatingEnable; ///< Control SMU SCLK gating
BOOLEAN PcieAspmBlackListEnable; ///< Control Pcie Aspm Black List
BOOLEAN IvrsRelativeAddrNamesSupport; ///< Support for relative address names
BOOLEAN GnbLoadRealF1Table;
UINT32 CfgGnbLinkReceiverDetectionPooling; ///< Receiver pooling detection time in us.
UINT32 CfgGnbLinkL0Pooling; ///< Pooling for link to get to L0 in us
UINT32 CfgGnbLinkGpioResetAssertionTime; ///< Gpio reset assertion time in us
UINT32 CfgGnbLinkResetToTrainingTime; ///< Time duration between deassert GPIO reset and release training in us
UINT8 CfgGnbTrainingAlgorithm; ///< distribution of training across interface calls
BOOLEAN CfgForceCableSafeOff; ///< Force cable safe off
BOOLEAN CfgOrbClockGatingEnable; ///< Control ORB clock gating
UINT8 CfgPciePowerGatingFlags; ///< Pcie Power gating flags
BOOLEAN CfgStub;
BOOLEAN CfgIocSclkClockGatingEnable; ///< Control IOC SCLK clock gating
BOOLEAN CfgIommuL1ClockGatingEnable; ///< Control IOMMU L1 clock gating
BOOLEAN CfgIommuL2ClockGatingEnable; ///< Control IOMMU L2 clock gating
BOOLEAN CfgAltVddNb; ///< AltVDDNB support
BOOLEAN CfgBapmSupport; ///< BAPM support
BOOLEAN CfgUnusedSimdPowerGatingEnable; ///< Control unused SIMD power gate
BOOLEAN CfgUnusedRbPowerGatingEnable; ///< Control unused SIMD power gate
BOOLEAN CfgNbdpmEnable; ///< NBDPM refers to dynamically reprogramming High and Low NB Pstates under different system usage scenarios
BOOLEAN CfgGmcClockGating; ///< Control GMC clock power gate
BOOLEAN CfgMaxPayloadEnable; ///< Enables configuration of Max_Payload_Size in PCIe device links
BOOLEAN CfgOrbDynWakeEnable; ///< Enables ORB Dynamic wake up
BOOLEAN CfgLoadlineEnable; ///< Enable Loadline Optimization
BOOLEAN CfgPciePhyIsolationEnable; ///< Enable Pcie Phy Isolation
BOOLEAN CfgLhtcSupport; ///< LHTC support
UINT8 CfgSviRevision; ///< SVI revision
BOOLEAN CfgScsSupport; ///< Scs support
BOOLEAN CfgSamuPatchEnabled;
UINT8 OemIdString[6]; ///< Configurable ACPI OEM Id
UINT8 OemTableIdString[8]; ///< Configurable ACPI OEM Table Id
BOOLEAN CfgTdcSupport; ///< TDC tracking support
BOOLEAN CfgPkgPowerTrackingSupport; ///< Package Power tracking
BOOLEAN CfgNativeGen1PLL; ///< Control Native Gen1 PLL
UINT8 CfgUmaSteering; ///< Configurable UMA Steering
} GNB_BUILD_OPTIONS;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_GNB_H_

365
src/vendorcode/amd/agesa/f16kb/Include/OptionMemory.h
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@ -1,365 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Memory option API.
*
* Contains structures and values used to control the Memory option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 85859 $ @e \$Date: 2013-01-14 02:57:14 -0600 (Mon, 14 Jan 2013) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_MEMORY_H_
#define _OPTION_MEMORY_H_
/* Memory Includes */
#include "mm.h"
#include "mn.h"
#include "mt.h"
#include "ma.h"
#include "mp.h"
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
#define MAX_FF_TYPES 6 ///< Maximum number of DDR Form factors (UDIMMs, RDIMMMs, SODIMMS) supported
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/*
* STANDARD MEMORY FEATURE FUNCTION POINTER
*/
typedef BOOLEAN OPTION_MEM_FEATURE_NB (
IN OUT MEM_NB_BLOCK *NBPtr
);
typedef BOOLEAN MEM_TECH_FEAT (
IN OUT MEM_TECH_BLOCK *TechPtr
);
typedef UINT8 MEM_TABLE_FEAT (
IN OUT MEM_TABLE_ALIAS **MTPtr
);
#define MEM_FEAT_BLOCK_NB_STRUCT_VERSION 0x01
/**
* MEMORY FEATURE BLOCK - This structure serves as a vector table for standard
* memory feature implementation functions. It contains vectors for all of the
* features that are supported by the various Northbridge devices supported by
* AGESA.
*/
typedef struct _MEM_FEAT_BLOCK_NB {
UINT16 OptMemFeatVersion; ///< Version of memory feature block.
OPTION_MEM_FEATURE_NB *OnlineSpare; ///< Online spare support.
OPTION_MEM_FEATURE_NB *InterleaveBanks; ///< Bank (Chip select) interleaving support.
OPTION_MEM_FEATURE_NB *UndoInterleaveBanks; ///< Undo Bank (Chip Select) interleaving.
OPTION_MEM_FEATURE_NB *CheckInterleaveNodes; ///< Check for Node interleaving support.
OPTION_MEM_FEATURE_NB *InterleaveNodes; ///< Node interleaving support.
OPTION_MEM_FEATURE_NB *InterleaveChannels; ///< Channel interleaving support.
OPTION_MEM_FEATURE_NB *InterleaveRegion; ///< Interleave Region support.
OPTION_MEM_FEATURE_NB *CheckEcc; ///< Check for ECC support.
OPTION_MEM_FEATURE_NB *InitEcc; ///< ECC support.
OPTION_MEM_FEATURE_NB *Training; ///< Choose the type of training (Parallel, standard or hardcoded).
OPTION_MEM_FEATURE_NB *LvDdr3; ///< Low voltage DDR3 dimm support
OPTION_MEM_FEATURE_NB *OnDimmThermal; ///< On-Dimm thermal management
MEM_TECH_FEAT *DramInit; ///< Choose the type of Dram init (hardware based or software based).
OPTION_MEM_FEATURE_NB *ExcludeDIMM; ///< Exclude a dimm.
OPTION_MEM_FEATURE_NB *InitEarlySampleSupport; ///< Initialize early sample support.
OPTION_MEM_FEATURE_NB *InitCPG; ///< Continuous pattern generation.
OPTION_MEM_FEATURE_NB *InitHwRxEn; ///< Hardware Receiver Enable Training Initilization.
OPTION_MEM_FEATURE_NB *InitAMP; ///< AMP initialization.
OPTION_MEM_FEATURE_NB *DataEye; ///< Get 2D training data eye.
OPTION_MEM_FEATURE_NB *InitRdWr2DTraining; ///< Initialize Read and/or Write 2D Training Feature.
OPTION_MEM_FEATURE_NB *AggressorInit; ///< Aggressor initialization.
} MEM_FEAT_BLOCK_NB;
typedef AGESA_STATUS MEM_MAIN_FLOW_CONTROL (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
);
typedef BOOLEAN OPTION_MEM_FEATURE_MAIN (
IN MEM_MAIN_DATA_BLOCK *MMPtr
);
typedef BOOLEAN MEM_NB_CONSTRUCTOR (
IN OUT MEM_NB_BLOCK *NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
CONST IN MEM_FEAT_BLOCK_NB *FeatPtr,
IN MEM_SHARED_DATA *mmSharedPtr, ///< Pointer to Memory scratchpad
IN UINT8 NodeID
);
typedef BOOLEAN MEM_TECH_CONSTRUCTOR (
IN OUT MEM_TECH_BLOCK *TechPtr,
IN OUT MEM_NB_BLOCK *NBPtr
);
typedef VOID MEM_INITIALIZER (
IN OUT MEM_DATA_STRUCT *MemPtr
);
typedef AGESA_STATUS MEM_PLATFORM_CFG (
IN struct _MEM_DATA_STRUCT *MemData,
IN UINT8 SocketID,
IN CH_DEF_STRUCT *CurrentChannel
);
typedef BOOLEAN MEM_IDENDIMM_CONSTRUCTOR (
IN OUT MEM_NB_BLOCK *NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
);
typedef VOID MEM_TECH_TRAINING_FEAT (
IN OUT MEM_TECH_BLOCK *TechPtr,
IN UINT8 Pass
);
typedef BOOLEAN MEM_RESUME_CONSTRUCTOR (
IN OUT VOID *S3NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
);
typedef AGESA_STATUS MEM_PLAT_SPEC_CFG (
IN struct _MEM_DATA_STRUCT *MemData,
IN OUT CH_DEF_STRUCT *CurrentChannel,
IN OUT MEM_PS_BLOCK *PsPtr
);
typedef AGESA_STATUS MEM_FLOW_CFG (
IN OUT MEM_MAIN_DATA_BLOCK *MemData
);
#define MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION 0x01
/**
* MAIN FEATURE BLOCK - This structure serves as vector table for memory features
* that shared between all northbridge devices.
*/
typedef struct _MEM_FEAT_BLOCK_MAIN {
UINT16 OptMemFeatVersion; ///< Version of main feature block.
OPTION_MEM_FEATURE_MAIN *Training; ///< Training features.
OPTION_MEM_FEATURE_MAIN *ExcludeDIMM; ///< Exclude a dimm.
OPTION_MEM_FEATURE_MAIN *OnlineSpare; ///< On-line spare.
OPTION_MEM_FEATURE_MAIN *InterleaveNodes; ///< Node interleave.
OPTION_MEM_FEATURE_MAIN *InitEcc; ///< Initialize ECC on all nodes if they all support it.
OPTION_MEM_FEATURE_MAIN *MemClr; ///< Memory Clear.
OPTION_MEM_FEATURE_MAIN *MemDmi; ///< Memory DMI Support.
OPTION_MEM_FEATURE_MAIN *MemCrat; ///< Memory CRAT Support.
OPTION_MEM_FEATURE_MAIN *LvDDR3; ///< Low voltage DDR3 support.
OPTION_MEM_FEATURE_MAIN *UmaAllocation; ///< Uma Allocation.
OPTION_MEM_FEATURE_MAIN *MemSave; ///< Memory Context Save
OPTION_MEM_FEATURE_MAIN *MemRestore; ///< Memory Context Restore
OPTION_MEM_FEATURE_MAIN *MemS3Save; ///< Memory S3 Save
OPTION_MEM_FEATURE_MAIN *AggressorDetermination; ///< Aggressor Chipselects for all DCTs on all nodes.
} MEM_FEAT_BLOCK_MAIN;
#define MEM_NB_SUPPORT_STRUCT_VERSION 0x01
#define MEM_TECH_FEAT_BLOCK_STRUCT_VERSION 0x01
#define MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION 0x01
#define MEM_TECH_LRDIMM_STRUCT_VERSION 0x01
/**
* MEMORY TECHNOLOGY FEATURE BLOCK - This structure serves as a vector table for standard
* memory feature implementation functions. It contains vectors for all of the
* features that are supported by the various Technology features supported by
* AGESA.
*/
typedef struct _MEM_TECH_FEAT_BLOCK {
UINT16 OptMemTechFeatVersion; ///< Version of memory Tech feature block.
MEM_TECH_FEAT *EnterHardwareTraining; ///<Enter HW WL Training
MEM_TECH_FEAT *SwWLTraining; ///<SW Write Levelization training
MEM_TECH_FEAT *HwBasedWLTrainingPart1; ///<HW based write levelization Training Part 1
MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart1; ///<HW based DQS receiver Enabled Training Part 1
MEM_TECH_FEAT *HwBasedWLTrainingPart2; ///<HW based write levelization Training Part 2
MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart2; ///<HW based DQS receiver Enabled Training Part 2
MEM_TECH_FEAT *TrainExitHwTrn; ///<Exit HW WL Training
MEM_TECH_FEAT *NonOptimizedSWDQSRecEnTrainingPart1; ///< Non-Optimized Software based receiver Enable Training part 1
MEM_TECH_FEAT *OptimizedSwDqsRecEnTrainingPart1; ///< Optimized Software based receiver Enable Training part 1
MEM_TECH_FEAT *NonOptimizedSRdWrPosTraining; ///< Non-Optimized Rd Wr Position training
MEM_TECH_FEAT *OptimizedSRdWrPosTraining; ///< Optimized Rd Wr Position training
MEM_TECH_FEAT *MaxRdLatencyTraining; ///< MaxReadLatency Training
MEM_TECH_FEAT *RdPosTraining; ///< HW Rx En Seed Training
MEM_TECH_FEAT *RdDqs2DTraining; ///< 2D Rd DQS Training
} MEM_TECH_FEAT_BLOCK;
/**
* MEMORY TECHNOLOGY LRDIMM BLOCK - This structure serves as a vector table for standard
* memory feature implementation functions. It contains vectors for all of the
* features that are supported by the various LRDIMM features supported by
* AGESA.
*/
typedef struct _MEM_TECH_LRDIMM {
UINT16 OptMemTechLrdimmVersion; ///< Version of memory Tech feature block.
MEM_TECH_FEAT *MemTInitializeLrdimm; ///< LRDIMM initialization
} MEM_TECH_LRDIMM;
/**
* MEMORY NORTHBRIDGE SUPPORT STRUCT - This structure groups the Northbridge dependent
* options together in a list to provide a single access point for all code to use
* and to ensure that everything corresponding to the same NB type is grouped together.
*
* The Technology Block pointers are not included in this structure because DRAM technology
* needs to be decoupled from the northbridge type.
*
*/
typedef struct _MEM_NB_SUPPORT {
UINT16 MemNBSupportVersion; ///< Version of northbridge support.
MEM_NB_CONSTRUCTOR *MemConstructNBBlock; ///< NorthBridge block constructor.
MEM_INITIALIZER *MemNInitDefaults; ///< Default value initialization for MEM_DATA_STRUCT.
CONST MEM_FEAT_BLOCK_NB *MemFeatBlock; ///< Memory feature block.
MEM_RESUME_CONSTRUCTOR *MemS3ResumeConstructNBBlock; ///< S3 memory initialization northbridge block constructor.
MEM_IDENDIMM_CONSTRUCTOR *MemIdentifyDimmConstruct; ///< Constructor for address to dimm identification.
} MEM_NB_SUPPORT;
/*
* MEMORY Non-Training FEATURES - This structure serves as a vector table for standard
* memory non-training feature implementation functions. It contains vectors for all of the
* features that are supported by the various Technology devices supported by
* AGESA.
*/
/**
* MAIN TRAINING SEQUENCE LIST - This structure serves as vector table for memory features
* that shared between all northbridge devices.
*/
typedef struct _MEM_FEAT_TRAIN_SEQ {
UINT16 OptMemTrainingSequenceListVersion; ///< Version of main feature block.
OPTION_MEM_FEATURE_NB *TrainingSequence; ///< Training Sequence function.
OPTION_MEM_FEATURE_NB *TrainingSequenceEnabled; ///< Enable function.
CONST MEM_TECH_FEAT_BLOCK *MemTechFeatBlock; ///< Memory feature block.
} MEM_FEAT_TRAIN_SEQ;
/**
* PLATFORM SPECIFIC CONFIGURATION BLOCK - This structure groups various PSC table
* entries which are used by PSC engine
*/
typedef struct _MEM_PSC_TABLE_BLOCK {
PSC_TBL_ENTRY **TblEntryOfMaxFreq; ///< Table entry of MaxFreq.
PSC_TBL_ENTRY **TblEntryOfDramTerm; ///< Table entry of Dram Term.
PSC_TBL_ENTRY **TblEntryOfODTPattern; ///< Table entry of ODT Pattern.
PSC_TBL_ENTRY **TblEntryOfSAO; ///< Table entry of Slow access mode, AddrTmg and ODC..
PSC_TBL_ENTRY **TblEntryOfMR0WR; ///< Table entry of MR0[WR].
PSC_TBL_ENTRY **TblEntryOfMR0CL; ///< Table entry of MR0[CL].
PSC_TBL_ENTRY **TblEntryOfRC2IBT; ///< Table entry of RC2 IBT.
PSC_TBL_ENTRY **TblEntryOfRC10OpSpeed; ///< Table entry of RC10[operating speed].
PSC_TBL_ENTRY **TblEntryOfLRIBT;///< Table entry of LRDIMM IBT
PSC_TBL_ENTRY **TblEntryOfLRNPR; ///< Table entry of LRDIMM F0RC13[NumPhysicalRanks].
PSC_TBL_ENTRY **TblEntryOfLRNLR; ///< Table entry of LRDIMM F0RC13[NumLogicalRanks].
PSC_TBL_ENTRY **TblEntryOfGen; ///< Table entry of CLKDis map and CKE, ODT as well as ChipSel tri-state map.
PSC_TBL_ENTRY **TblEntryOfS2D; ///< Table entry of 2D training configs
PSC_TBL_ENTRY **TblEntryOfWLSeed; ///< Table entry of WL seed
PSC_TBL_ENTRY **TblEntryOfHWRxENSeed; ///< Table entry of HW RxEN seed
} MEM_PSC_TABLE_BLOCK;
typedef BOOLEAN MEM_PSC_FLOW (
IN OUT MEM_NB_BLOCK *NBPtr,
CONST IN MEM_PSC_TABLE_BLOCK *EntryOfTables
);
/**
* PLATFORM SPECIFIC CONFIGURATION FLOW BLOCK - Pointers to the sub-engines of platform
* specific configuration.
*/
typedef struct _MEM_PSC_FLOW_BLOCK {
CONST MEM_PSC_TABLE_BLOCK *EntryOfTables; ///<Entry of NB specific MEM_PSC_TABLE_BLOCK
MEM_PSC_FLOW *MaxFrequency; ///< Sub-engine which performs "Max Frequency" value extraction.
MEM_PSC_FLOW *DramTerm; ///< Sub-engine which performs "Dram Term" value extraction.
MEM_PSC_FLOW *ODTPattern; ///< Sub-engine which performs "ODT Pattern" value extraction.
MEM_PSC_FLOW *SAO; ///< Sub-engine which performs "Slow access mode, AddrTmg and ODC" value extraction.
MEM_PSC_FLOW *MR0WrCL; ///< Sub-engine which performs "MR0[WR] and MR0[CL]" value extraction.
MEM_PSC_FLOW *RC2IBT; ///< Sub-engine "RC2 IBT" value extraction.
MEM_PSC_FLOW *RC10OpSpeed; ///< Sub-engine "RC10[operating speed]" value extraction.
MEM_PSC_FLOW *LRIBT; ///< Sub-engine "LRDIMM IBT" value extraction.
MEM_PSC_FLOW *LRNPR; ///< Sub-engine "LRDIMM F0RC13[NumPhysicalRanks]" value extraction.
MEM_PSC_FLOW *LRNLR; ///< Sub-engine "LRDIMM F0RC13[NumLogicalRanks]" value extraction.
MEM_PSC_FLOW *S2D; ///< Sub-engine which performs 2D training configuration checking
MEM_PSC_FLOW *TrainingSeedVal; ///< Sub-engine for WL and HW RxEn pass1 seed value extraction
} MEM_PSC_FLOW_BLOCK;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
/* Feature Default Return */
BOOLEAN MemFDefRet (
IN OUT MEM_NB_BLOCK *NBPtr
);
BOOLEAN MemMDefRet (
IN MEM_MAIN_DATA_BLOCK *MMPtr
);
BOOLEAN MemMDefRetFalse (
IN MEM_MAIN_DATA_BLOCK *MMPtr
);
/* Table Feature Default Return */
UINT8 MemFTableDefRet (
IN OUT MEM_TABLE_ALIAS **MTPtr
);
/* S3 Feature Default Return */
BOOLEAN MemFS3DefConstructorRet (
IN OUT VOID *S3NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
);
BOOLEAN MemNIdentifyDimmConstructorRetDef (
IN OUT MEM_NB_BLOCK *NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
);
BOOLEAN
MemProcessConditionalOverrides (
IN PSO_TABLE *PlatformMemoryConfiguration,
IN OUT MEM_NB_BLOCK *NBPtr,
IN UINT8 PsoAction,
IN UINT8 Dimm
);
#endif // _OPTION_MEMORY_H_

215
src/vendorcode/amd/agesa/f16kb/Include/OptionMultiSocket.h
View File

@ -1,215 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Multi-socket option API.
*
* Contains structures and values used to control the multi-socket option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_MULTISOCKET_H_
#define _OPTION_MULTISOCKET_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/**
* This function loops through all possible socket locations, gathering the number
* of power management steps each populated socket requires, and returns the
* highest number.
*
* @param[out] NumSystemSteps Maximum number of system steps required
* @param[in] StdHeader Config handle for library and services
*
*/
typedef VOID OPTION_MULTISOCKET_PM_STEPS (
OUT UINT8 *NumSystemSteps,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function loops through all possible socket locations, starting core 0 of
* each populated socket to perform the passed in AP_TASK. After starting all
* other core 0s, the BSC will perform the AP_TASK as well. This must be run by
* the system BSC only.
*
* @param[in] TaskPtr Function descriptor
* @param[in] StdHeader Config handle for library and services
* @param[in] ConfigParams AMD entry point's CPU parameter structure
*
* @return The most severe error code from AP_TASK
*
*/
typedef AGESA_STATUS OPTION_MULTISOCKET_PM_CORE0_TASK (
IN VOID *TaskPtr,
IN AMD_CONFIG_PARAMS *StdHeader,
IN VOID *ConfigParams
);
/**
* This function loops through all possible socket locations, comparing the
* maximum NB frequencies to determine the slowest. This function also
* determines if all coherent NB frequencies are equivalent.
*
* @param[in] NbPstate NB P-state number to check (0 = fastest)
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[out] SystemNbCofNumerator NB frequency numerator for the system in MHz
* @param[out] SystemNbCofDenominator NB frequency denominator for the system
* @param[out] SystemNbCofsMatch Whether or not all NB frequencies are equivalent
* @param[out] NbPstateIsEnabledOnAllCPUs Whether or not NbPstate is valid on all CPUs
* @param[in] StdHeader Config handle for library and services
*
* @retval TRUE At least one processor has NbPstate enabled.
* @retval FALSE NbPstate is disabled on all CPUs
*/
typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF (
IN UINT32 NbPstate,
IN PLATFORM_CONFIGURATION *PlatformConfig,
OUT UINT32 *SystemNbCofNumerator,
OUT UINT32 *SystemNbCofDenominator,
OUT BOOLEAN *SystemNbCofsMatch,
OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function loops through all possible socket locations, checking whether
* any populated sockets require NB COF VID programming.
*
* @param[in] StdHeader Config handle for library and services
*
*/
typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF_UPDATE (
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function loops through all possible socket locations, collecting any
* power management initialization errors that may have occurred. These errors
* are transferred from the core 0s of the socket in which the errors occurred
* to the BSC's heap. The BSC's heap is then searched for the most severe error
* that occurred, and returns it. This function must be called by the BSC only.
*
* @param[in] StdHeader Config handle for library and services
*
*/
typedef AGESA_STATUS OPTION_MULTISOCKET_PM_GET_EVENTS (
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function loops through all possible socket locations and Nb Pstates,
* comparing the NB frequencies to determine the slowest NB P0 and NB Pmin in
* the system.
*
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[out] MinSysNbFreq NB frequency numerator for the system in MHz
* @param[out] MinP0NbFreq NB frequency numerator for P0 in MHz
* @param[in] StdHeader Config handle for library and services
*/
typedef VOID OPTION_MULTISOCKET_PM_NB_MIN_COF (
IN PLATFORM_CONFIGURATION *PlatformConfig,
OUT UINT32 *MinSysNbFreq,
OUT UINT32 *MinP0NbFreq,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function returns the current running core's PCI Config Space address.
*
* @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0)
* @param[in] StdHeader Header for library and services.
*/
typedef BOOLEAN OPTION_MULTISOCKET_GET_PCI_ADDRESS (
OUT PCI_ADDR *PciAddress,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function writes to all nodes on the executing core's socket.
*
* @param[in] PciAddress The Function and Register to update
* @param[in] Mask The bitwise AND mask to apply to the current register value
* @param[in] Data The bitwise OR mask to apply to the current register value
* @param[in] StdHeader Header for library and services.
*
*/
typedef VOID OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI (
IN PCI_ADDR *PciAddress,
IN UINT32 Mask,
IN UINT32 Data,
IN AMD_CONFIG_PARAMS *StdHeader
);
#define MULTISOCKET_STRUCT_VERSION 0x01
/**
* Provide build configuration of cpu multi-socket or single socket support.
*
*/
typedef struct {
UINT16 OptMultiSocketVersion; ///< Table version
OPTION_MULTISOCKET_PM_STEPS *GetNumberOfSystemPmSteps; ///< Method: Get number of power mgt tasks
OPTION_MULTISOCKET_PM_CORE0_TASK *BscRunCodeOnAllSystemCore0s; ///< Method: Perform tasks on Core 0 of each processor
OPTION_MULTISOCKET_PM_NB_COF *GetSystemNbPstateSettings; ///< Method: Find the Northbridge frequency for the specified Nb Pstate in the system.
OPTION_MULTISOCKET_PM_NB_COF_UPDATE *GetSystemNbCofVidUpdate; ///< Method: Determine if any Northbridges in the system need to update their COF/VID.
OPTION_MULTISOCKET_PM_GET_EVENTS *BscRetrievePmEarlyInitErrors; ///< Method: Gathers error information from all Core 0s.
OPTION_MULTISOCKET_PM_NB_MIN_COF *GetMinNbCof; ///< Method: Get the minimum system and minimum P0 Northbridge frequency.
OPTION_MULTISOCKET_GET_PCI_ADDRESS *GetCurrPciAddr; ///< Method: Get PCI Config Space Address for the current running core.
OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI *ModifyCurrSocketPci; ///< Method: Writes to all nodes on the executing core's socket.
} OPTION_MULTISOCKET_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_MULTISOCKET_H_

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@ -1,117 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD ACPI PState option API.
*
* Contains structures and values used to control the PStates option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_PSTATE_H_
#define _OPTION_PSTATE_H_
#include "cpuPstateTables.h"
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_SSDT_FEATURE (
IN AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN OUT VOID **AcpiPstatePtr
);
typedef UINT32 OPTION_ACPI_FEATURE (
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN PSTATE_LEVELING *PStateLevelingBuffer,
IN OUT VOID **AcpiPStatePtr,
IN UINT8 LocalApicId,
IN AMD_CONFIG_PARAMS *StdHeader
);
typedef AGESA_STATUS OPTION_PSTATE_GATHER (
IN AMD_CONFIG_PARAMS *StdHeader,
IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr
);
typedef AGESA_STATUS OPTION_PSTATE_LEVELING (
IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
#define PSTATE_STRUCT_VERSION 0x01
/// Indirection vectors for POST/PEI PState code
typedef struct {
UINT16 OptPstateVersion; ///< revision of this structure
OPTION_PSTATE_GATHER *PstateGather; ///< vector for data gathering routine
OPTION_PSTATE_LEVELING *PstateLeveling; ///< vector for leveling routine
} OPTION_PSTATE_POST_CONFIGURATION;
/// Indirection vectors for LATE/DXE PState code
typedef struct {
UINT16 OptPstateVersion; ///< revision of this structure
OPTION_SSDT_FEATURE *SsdtFeature; ///< vector for routine to generate SSDT
OPTION_ACPI_FEATURE *PstateFeature; ///< vector for routine to generate ACPI PState Objects
OPTION_ACPI_FEATURE *CstateFeature; ///< vector for routine to generate ACPI CState Objects
BOOLEAN CfgPstatePpc; ///< boolean for creating _PPC method
BOOLEAN CfgPstatePct; ///< boolean for creating _PCT method
BOOLEAN CfgPstatePsd; ///< boolean for creating _PSD method
BOOLEAN CfgPstatePss; ///< boolean for creating _PSS method
BOOLEAN CfgPstateXpss; ///< boolean for creating _XPSS method
UINT8 OemIdString[6]; ///< Configurable OEM Id
UINT8 OemTableIdString[8]; ///< Configurable OEM Table Id
} OPTION_PSTATE_LATE_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_PSTATE_H_

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@ -1,98 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD SLIT option API.
*
* Contains structures and values used to control the SLIT option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_SLIT_H_
#define _OPTION_SLIT_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/**
* Create the ACPI System Locality Distance Information Table.
*
*/
typedef AGESA_STATUS OPTION_SLIT_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN OUT VOID **SlitPtr
);
/**
* Clean up DRAM used during SLIT creation.
*
*/
typedef AGESA_STATUS OPTION_SLIT_RELEASE_BUFFER (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
#define SLIT_STRUCT_VERSION 0x01
/// The Option Configuration of SLIT
typedef struct {
UINT16 OptSlitVersion; ///< The version number of SLIT
OPTION_SLIT_FEATURE *SlitFeature; ///< The Option Feature of SLIT
OPTION_SLIT_RELEASE_BUFFER *SlitReleaseBuffer; ///< Release buffer
UINT8 OemIdString[6]; ///< Configurable OEM Id
UINT8 OemTableIdString[8]; ///< Configurable OEM Table Id
} OPTION_SLIT_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_SLIT_H_

84
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@ -1,84 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD SRAT option API.
*
* Contains structures and values used to control the SRAT option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_SRAT_H_
#define _OPTION_SRAT_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_SRAT_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN OUT VOID **SratPtr
);
#define SRAT_STRUCT_VERSION 0x01
/// The Option Configuration of SRAT
typedef struct {
UINT16 OptSratVersion; ///< The version number of SRAT
OPTION_SRAT_FEATURE *SratFeature; ///< The Option Feature of SRAT
UINT8 OemIdString[6]; ///< Configurable OEM Id
UINT8 OemTableIdString[8]; ///< Configurable OEM Table Id
} OPTION_SRAT_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_SRAT_H_

83
src/vendorcode/amd/agesa/f16kb/Include/OptionWhea.h
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@ -1,83 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD WHEA option API.
*
* Contains structures and values used to control the WHEA option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_WHEA_H_
#define _OPTION_WHEA_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_WHEA_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN OUT VOID **WheaMcePtr,
IN OUT VOID **WheaCmcPtr
);
#define WHEA_STRUCT_VERSION 0x01
/// The Option Configuration of WHEA
typedef struct {
UINT16 OptWheaVersion; ///< The version number of WHEA
OPTION_WHEA_FEATURE *WheaFeature; ///< The Option Feature of WHEA
} OPTION_WHEA_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_WHEA_H_

68
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@ -1,68 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AGESA options structures
*
* Contains options control structures for the AGESA build options
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTIONS_H_
#define _OPTIONS_H_
/**
* Provide topology limits for loops and runtime, based on supported families.
*/
typedef struct {
UINT32 PlatformNumberOfSockets; ///< The limit to the number of processors based on
///< supported families and other build options.
UINT32 PlatformNumberOfModules; ///< The limit to the number of modules in a processor, based
///< on supported families.
} OPTIONS_CONFIG_TOPOLOGY;
/**
* Dispatch Table.
*
* The push high dispatcher uses this table to find what entries are currently in the build image.
*/
typedef struct {
UINT32 FunctionId; ///< The function id specified.
IMAGE_ENTRY EntryPoint; ///< The corresponding entry point to call.
} DISPATCH_TABLE;
#endif // _OPTIONS_H_

109
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@ -1,109 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD HyperTransport option API.
*
* Contains option pre-compile logic. This file is used by the options
* installer and internally by the HT code initializers.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_HT_H_
#define _OPTION_HT_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/**
* Provide HT build option results
*/
typedef struct {
CONST BOOLEAN IsUsingRecoveryHt; ///< Manual BUID Swap List processing should assume that HT Recovery was used.
CONST BOOLEAN IsSetHtCrcFlood; ///< Enable setting of HT CRC Flood.
///< Build-time only customizable - @BldCfgItem{BLDCFG_SET_HTCRC_SYNC_FLOOD}
CONST BOOLEAN IsUsingUnitIdClumping; ///< Enable automatically HT Spec compliant Unit Id Clumping.
///< Build-time only customizable - @BldCfgItem{BLDCFG_USE_UNIT_ID_CLUMPING}
CONST AMD_HT_INTERFACE *HtOptionPlatformDefaults; ///< A set of build time options for HT constructor.
CONST VOID *HtOptionInternalInterface; ///< Use this internal interface initializer.
CONST VOID *HtOptionInternalFeatures; ///< Use this internal feature set initializer.
CONST VOID *HtOptionFamilyNorthbridgeList; ///< Use this list of northbridge initializers.
CONST UINT8 *CONST *HtOptionBuiltinTopologies; ///< Use this list of built-in topologies.
} OPTION_HT_CONFIGURATION;
typedef AGESA_STATUS
F_OPTION_HT_INIT_RESET (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
);
typedef F_OPTION_HT_INIT_RESET *PF_OPTION_HT_INIT_RESET;
typedef AGESA_STATUS
F_OPTION_HT_RESET_CONSTRUCTOR (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
);
typedef F_OPTION_HT_RESET_CONSTRUCTOR *PF_OPTION_HT_RESET_CONSTRUCTOR;
/**
* Provide HT reset initialization build option results
*/
typedef struct {
PF_OPTION_HT_INIT_RESET HtInitReset; ///< Method: HT reset initialization.
PF_OPTION_HT_RESET_CONSTRUCTOR HtResetConstructor; ///< Method: HT reset initialization.
} OPTION_HT_INIT_RESET;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_HT_H_

516
src/vendorcode/amd/agesa/f16kb/Include/PlatformMemoryConfiguration.h
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@ -1,516 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Platform Specific Memory Configuration
*
* Contains Definitions and Macros for control of AGESA Memory code on a per platform basis
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _PLATFORM_MEMORY_CONFIGURATION_H_
#define _PLATFORM_MEMORY_CONFIGURATION_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
#ifndef PSO_ENTRY
#define PSO_ENTRY UINT8
#endif
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* PLATFORM SPECIFIC MEMORY DEFINITIONS
*----------------------------------------------------------------------------------------
*/
///
/// Memory Speed and DIMM Population Masks
///
///< DDR Speed Masks
///< Specifies the DDR Speed on a memory channel
///
#define ANY_SPEED 0xFFFFFFFFul
#define DDR400 ((UINT32) 1 << (DDR400_FREQUENCY / 66))
#define DDR533 ((UINT32) 1 << (DDR533_FREQUENCY / 66))
#define DDR667 ((UINT32) 1 << (DDR667_FREQUENCY / 66))
#define DDR800 ((UINT32) 1 << (DDR800_FREQUENCY / 66))
#define DDR1066 ((UINT32) 1 << (DDR1066_FREQUENCY / 66))
#define DDR1333 ((UINT32) 1 << (DDR1333_FREQUENCY / 66))
#define DDR1600 ((UINT32) 1 << (DDR1600_FREQUENCY / 66))
#define DDR1866 ((UINT32) 1 << (DDR1866_FREQUENCY / 66))
#define DDR2133 ((UINT32) 1 << (DDR2133_FREQUENCY / 66))
#define DDR2400 ((UINT32) 1 << (DDR2400_FREQUENCY / 66))
///
///< DIMM POPULATION MASKS
///< Specifies the DIMM Population on a channel (can be added together to specify configuration).
///< ex. SR_DIMM0 + SR_DIMM1 : Single Rank Dimm in slot 0 AND Slot 1
///< SR_DIMM0 + DR_DIMM0 + SR_DIMM1 +DR_DIMM1 : Single OR Dual rank in Slot 0 AND Single OR Dual rank in Slot 1
///
#define ANY_ 0xFF ///< Any dimm configuration the current channel
#define SR_DIMM0 0x0001 ///< Single rank dimm in slot 0 on the current channel
#define SR_DIMM1 0x0010 ///< Single rank dimm in slot 1 on the current channel
#define SR_DIMM2 0x0100 ///< Single rank dimm in slot 2 on the current channel
#define SR_DIMM3 0x1000 ///< Single rank dimm in slot 3 on the current channel
#define DR_DIMM0 0x0002 ///< Dual rank dimm in slot 0 on the current channel
#define DR_DIMM1 0x0020 ///< Dual rank dimm in slot 1 on the current channel
#define DR_DIMM2 0x0200 ///< Dual rank dimm in slot 2 on the current channel
#define DR_DIMM3 0x2000 ///< Dual rank dimm in slot 3 on the current channel
#define QR_DIMM0 0x0004 ///< Quad rank dimm in slot 0 on the current channel
#define QR_DIMM1 0x0040 ///< Quad rank dimm in slot 1 on the current channel
#define QR_DIMM2 0x0400 ///< Quad rank dimm in slot 2 on the current channel
#define QR_DIMM3 0x4000 ///< Quad rank dimm in slot 3 on the current channel
#define LR_DIMM0 0x0001 ///< Lrdimm in slot 0 on the current channel
#define LR_DIMM1 0x0010 ///< Lrdimm in slot 1 on the current channel
#define LR_DIMM2 0x0100 ///< Lrdimm in slot 2 on the current channel
#define LR_DIMM3 0x1000 ///< Lrdimm in slot 3 on the current channel
#define ANY_DIMM0 0x000F ///< Any Dimm combination in slot 0 on the current channel
#define ANY_DIMM1 0x00F0 ///< Any Dimm combination in slot 1 on the current channel
#define ANY_DIMM2 0x0F00 ///< Any Dimm combination in slot 2 on the current channel
#define ANY_DIMM3 0xF000 ///< Any Dimm combination in slot 3 on the current channel
///
///< CS POPULATION MASKS
///< Specifies the CS Population on a channel (can be added together to specify configuration).
///< ex. CS0 + CS1 : CS0 and CS1 apply to the setting
///
#define CS_ANY_ 0xFF ///< Any CS configuration
#define CS0_ 0x01 ///< CS0 bit map mask
#define CS1_ 0x02 ///< CS1 bit map mask
#define CS2_ 0x04 ///< CS2 bit map mask
#define CS3_ 0x08 ///< CS3 bit map mask
#define CS4_ 0x10 ///< CS4 bit map mask
#define CS5_ 0x20 ///< CS5 bit map mask
#define CS6_ 0x40 ///< CS6 bit map mask
#define CS7_ 0x80 ///< CS7 bit map mask
///
///< Number of Dimms on the current channel
///< This is a mask used to indicate the number of dimms in a channel
///< They can be added to indicate multiple conditions (i.e 1 OR 2 Dimms)
///
#define ANY_NUM 0xFF ///< Any number of Dimms
#define NO_DIMM 0x00 ///< No Dimms present
#define ONE_DIMM 0x01 ///< One dimm Poulated on the current channel
#define TWO_DIMM 0x02 ///< Two dimms Poulated on the current channel
#define THREE_DIMM 0x04 ///< Three dimms Poulated on the current channel
#define FOUR_DIMM 0x08 ///< Four dimms Poulated on the current channel
///
///< DIMM VOLTAGE MASKS
///
#define VOLT_ANY_ 0xFF ///< Any voltage configuration
#define VOLT1_5_ 0x01 ///< Voltage 1.5V bit map mask
#define VOLT1_35_ 0x02 ///< Voltage 1.35V bit map mask
#define VOLT1_25_ 0x04 ///< Voltage 1.25V bit map mask
//
// < Not applicable
//
#define NA_ 0 ///< Not applicable
/*----------------------------------------------------------------------------------------
*
* Platform Specific Override Definitions for Socket, Channel and Dimm
* This indicates where a platform override will be applied.
*
*----------------------------------------------------------------------------------------
*/
///
///< SOCKET MASKS
///< Indicates associated processor sockets to apply override settings
///
#define ANY_SOCKET 0xFF ///< Apply to all sockets
#define SOCKET0 0x01 ///< Apply to socket 0
#define SOCKET1 0x02 ///< Apply to socket 1
#define SOCKET2 0x04 ///< Apply to socket 2
#define SOCKET3 0x08 ///< Apply to socket 3
#define SOCKET4 0x10 ///< Apply to socket 4
#define SOCKET5 0x20 ///< Apply to socket 5
#define SOCKET6 0x40 ///< Apply to socket 6
#define SOCKET7 0x80 ///< Apply to socket 7
///
///< CHANNEL MASKS
///< Indicates Memory channels where override should be applied
///
#define ANY_CHANNEL 0xFF ///< Apply to all Memory channels
#define CHANNEL_A 0x01 ///< Apply to Channel A
#define CHANNEL_B 0x02 ///< Apply to Channel B
#define CHANNEL_C 0x04 ///< Apply to Channel C
#define CHANNEL_D 0x08 ///< Apply to Channel D
///
/// DIMM MASKS
/// Indicates Dimm Slots where override should be applied
///
#define ALL_DIMMS 0xFF ///< Apply to all dimm slots
#define DIMM0 0x01 ///< Apply to Dimm Slot 0
#define DIMM1 0x02 ///< Apply to Dimm Slot 1
#define DIMM2 0x04 ///< Apply to Dimm Slot 2
#define DIMM3 0x08 ///< Apply to Dimm Slot 3
///
/// REGISTER ACCESS MASKS
/// Not supported as an at this time
///
#define ACCESS_NB0 0x0
#define ACCESS_NB1 0x1
#define ACCESS_NB2 0x2
#define ACCESS_NB3 0x3
#define ACCESS_NB4 0x4
#define ACCESS_PHY 0x5
#define ACCESS_DCT_XT 0x6
///
/// MOTHER BOARD DESIGN LAYERS MASKS
/// Indicates the layer design of mother board
///
#define LAYERS_4 0x0
#define LAYERS_6 0x1
/*----------------------------------------------------------------------------------------
*
* Platform Specific Overriding Table Definitions
*
*----------------------------------------------------------------------------------------
*/
#define PSO_END 0 ///< Table End
#define PSO_CKE_TRI 1 ///< CKE Tristate Map
#define PSO_ODT_TRI 2 ///< ODT Tristate Map
#define PSO_CS_TRI 3 ///< CS Tristate Map
#define PSO_MAX_DIMMS 4 ///< Max Dimms per channel
#define PSO_CLK_SPEED 5 ///< Clock Speed
#define PSO_DIMM_TYPE 6 ///< Dimm Type
#define PSO_MEMCLK_DIS 7 ///< MEMCLK Disable Map
#define PSO_MAX_CHNLS 8 ///< Max Channels per Socket
#define PSO_BUS_SPEED 9 ///< Max Memory Bus Speed
#define PSO_MAX_CHIPSELS 10 ///< Max Chipsel per Channel
#define PSO_MEM_TECH 11 ///< Channel Memory Type
#define PSO_WL_SEED 12 ///< DDR3 Write Levelization Seed delay
#define PSO_RXEN_SEED 13 ///< Hardwared based RxEn seed
#define PSO_NO_LRDIMM_CS67_ROUTING 14 ///< CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
#define PSO_SOLDERED_DOWN_SODIMM_TYPE 15 ///< Soldered down SODIMM type
#define PSO_LVDIMM_VOLT1_5_SUPPORT 16 ///< Force LvDimm voltage to 1.5V
#define PSO_MIN_RD_WR_DATAEYE_WIDTH 17 ///< Min RD/WR dataeye width
#define PSO_CPU_FAMILY_TO_OVERRIDE 18 ///< CPU family signature to tell following PSO macros are CPU family dependent
#define PSO_MAX_SOLDERED_DOWN_DIMMS 19 ///< Max Soldered-down Dimms per channel
#define PSO_MEMORY_POWER_POLICY 20 ///< Memory power policy override
#define PSO_MOTHER_BOARD_LAYERS 21 ///< Mother board layer design
/*----------------------------------
* CONDITIONAL PSO SPECIFIC ENTRIES
*---------------------------------*/
// Condition Types
#define CONDITIONAL_PSO_MIN 100 ///< Start of Conditional Entry Types
#define PSO_CONDITION_AND 100 ///< And Block - Start of Conditional block
#define PSO_CONDITION_LOC 101 ///< Location - Specify Socket, Channel, Dimms to be affected
#define PSO_CONDITION_SPD 102 ///< SPD - Specify a specific SPD value on a Dimm on the channel
#define PSO_CONDITION_REG 103 // Reserved
#define PSO_CONDITION_MAX 103 ///< End Of Condition Entry Types
// Action Types
#define PSO_ACTION_MIN 120 ///< Start of Action Entry Types
#define PSO_ACTION_ODT 120 ///< ODT values to override
#define PSO_ACTION_ADDRTMG 121 ///< Address/Timing values to override
#define PSO_ACTION_ODCCONTROL 122 ///< ODC Control values to override
#define PSO_ACTION_SLEWRATE 123 ///< Slew Rate value to override
#define PSO_ACTION_REG 124 // Reserved
#define PSO_ACTION_SPEEDLIMIT 125 ///< Memory Bus speed Limit based on configuration
#define PSO_ACTION_MAX 125 ///< End of Action Entry Types
#define CONDITIONAL_PSO_MAX 139 ///< End of Conditional Entry Types
/*----------------------------------
* TABLE DRIVEN PSO SPECIFIC ENTRIES
*---------------------------------*/
// Condition descriptor
#define PSO_TBLDRV_CONFIG 200 ///< Configuration Descriptor
// Overriding entry types
#define PSO_TBLDRV_START 210 ///< Start of Table Driven Overriding Entry Types
#define PSO_TBLDRV_SPEEDLIMIT 210 ///< Speed Limit
#define PSO_TBLDRV_ODT_RTTNOM 211 ///< RttNom
#define PSO_TBLDRV_ODT_RTTWR 212 ///< RttWr
#define PSO_TBLDRV_ODTPATTERN 213 ///< Odt Patterns
#define PSO_TBLDRV_ADDRTMG 214 ///< Address/Timing values
#define PSO_TBLDRV_ODCCTRL 215 ///< ODC Control values
#define PSO_TBLDRV_SLOWACCMODE 216 ///< Slow Access Mode
#define PSO_TBLDRV_MR0_CL 217 ///< MR0[CL]
#define PSO_TBLDRV_MR0_WR 218 ///< MR0[WR]
#define PSO_TBLDRV_RC2_IBT 219 ///< RC2[IBT]
#define PSO_TBLDRV_RC10_OPSPEED 220 ///< RC10[Opearting Speed]
#define PSO_TBLDRV_LRDIMM_IBT 221 ///< LrDIMM IBT
#define PSO_TBLDRV_2D_TRAINING 222 ///< 2D training
#define PSO_TBLDRV_INVALID_TYPE 223 ///< Invalid Type
#define PSO_TBLDRV_END 223 ///< End of Table Driven Overriding Entry Types
/*----------------------------------------------------------------------------------------
* CONDITIONAL OVERRIDE TABLE MACROS
*----------------------------------------------------------------------------------------
*/
#define CPU_FAMILY_TO_OVERRIDE(CpuFamilyRevision) \
PSO_CPU_FAMILY_TO_OVERRIDE, 4, \
((CpuFamilyRevision) & 0x0FF), (((CpuFamilyRevision) >> 8)& 0x0FF), (((CpuFamilyRevision) >> 16)& 0x0FF), (((CpuFamilyRevision) >> 24)& 0x0FF)
#define MEMCLK_DIS_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
PSO_MEMCLK_DIS, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map \
, Bit7Map
#define CKE_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \
PSO_CKE_TRI, 7, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map
#define ODT_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \
PSO_ODT_TRI, 7, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map
#define CS_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
PSO_CS_TRI, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map
#define NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) \
PSO_MAX_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfDimmSlotsPerChannel
#define NUMBER_OF_SOLDERED_DOWN_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfSolderedDownDimmsPerChannel) \
PSO_MAX_SOLDERED_DOWN_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfSolderedDownDimmsPerChannel
#define NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) \
PSO_MAX_CHIPSELS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfChipSelectsPerChannel
#define NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) \
PSO_MAX_CHNLS, 4, SocketID, ANY_CHANNEL, ALL_DIMMS, NumberOfChannelsPerSocket
#define OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, TimingMode, BusSpeed) \
PSO_BUS_SPEED, 11, SocketID, ChannelID, ALL_DIMMS, TimingMode, (TimingMode >> 8), (TimingMode >> 16), (TimingMode >> 24), \
BusSpeed, (BusSpeed >> 8), (BusSpeed >> 16), (BusSpeed >> 24)
#define DRAM_TECHNOLOGY(SocketID, MemTechType) \
PSO_MEM_TECH, 7, SocketID, ANY_CHANNEL, ALL_DIMMS, MemTechType, (MemTechType >> 8), (MemTechType >> 16), (MemTechType >> 24)
#define WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
Byte6Seed, Byte7Seed, ByteEccSeed) \
PSO_WL_SEED, 12, SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
Byte6Seed, Byte7Seed, ByteEccSeed
#define HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
Byte6Seed, Byte7Seed, ByteEccSeed) \
PSO_RXEN_SEED, 21, SocketID, ChannelID, DimmID, Byte0Seed, (Byte0Seed >> 8), Byte1Seed, (Byte1Seed >> 8), Byte2Seed, (Byte2Seed >> 8), \
Byte3Seed, (Byte3Seed >> 8), Byte4Seed, (Byte4Seed >> 8), Byte5Seed, (Byte5Seed >> 8), Byte6Seed, (Byte6Seed >> 8), \
Byte7Seed, (Byte7Seed >> 8), ByteEccSeed, (ByteEccSeed >> 8)
#define NO_LRDIMM_CS67_ROUTING(SocketID, ChannelID) \
PSO_NO_LRDIMM_CS67_ROUTING, 4, SocketID, ChannelID, ALL_DIMMS, TRUE
#define SOLDERED_DOWN_SODIMM_TYPE(SocketID, ChannelID) \
PSO_SOLDERED_DOWN_SODIMM_TYPE, 4, SocketID, ChannelID, ALL_DIMMS, TRUE
#define LVDIMM_FORCE_VOLT1_5_FOR_D0 \
PSO_LVDIMM_VOLT1_5_SUPPORT, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, TRUE
#define MIN_RD_WR_DATAEYE_WIDTH(SocketID, ChannelID, MinRdDataeyeWidth, MinWrDataeyeWidth) \
PSO_MIN_RD_WR_DATAEYE_WIDTH, 5, SocketID, ChannelID, ALL_DIMMS, MinRdDataeyeWidth, MinWrDataeyeWidth
#define MEMORY_POWER_POLICY_OVERRIDE(PowerPolicy) \
PSO_MEMORY_POWER_POLICY, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, PowerPolicy
#define MOTHER_BOARD_LAYERS(Layers) \
PSO_MOTHER_BOARD_LAYERS, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, Layers
/*----------------------------------------------------------------------------------------
* CONDITIONAL OVERRIDE TABLE MACROS
*----------------------------------------------------------------------------------------
*/
#define CONDITION_AND \
PSO_CONDITION_AND, 0
#define COND_LOC(SocketMsk, ChannelMsk, DimmMsk) \
PSO_CONDITION_LOC, 3, SocketMsk, ChannelMsk, DimmMsk
#define COND_SPD(Byte, Mask, Value) \
PSO_CONDITION_SPD, 3, Byte, Mask, Value
#define COND_REG(Access, Offset, Mask, Value) \
PSO_CONDITION_REG, 11, Access, (Offset & 0x0FF), (Offset >> 8), \
((Mask) & 0x0FF), (((Mask) >> 8) & 0x0FF), (((Mask) >> 16) & 0x0FF), (((Mask) >> 24) & 0x0FF), \
((Value) & 0x0FF), (((Value) >> 8) & 0x0FF), (((Value) >> 16) & 0x0FF), (((Value) >> 24) & 0x0FF)
#define ACTION_ODT(Frequency, Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt) \
PSO_ACTION_ODT, 9, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), ((Frequency >> 24)& 0x0FF), \
Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt
#define ACTION_ADDRTMG(Frequency, DimmConfig, AddrTmg) \
PSO_ACTION_ADDRTMG, 10, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
(AddrTmg & 0x0FF), ((AddrTmg >> 8)& 0x0FF), ((AddrTmg >> 16)& 0x0FF), ((AddrTmg >> 24)& 0x0FF)
#define ACTION_ODCCTRL(Frequency, DimmConfig, OdcCtrl) \
PSO_ACTION_ODCCONTROL, 10, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
(OdcCtrl & 0x0FF), ((OdcCtrl >> 8)& 0x0FF), ((OdcCtrl >> 16)& 0x0FF), ((OdcCtrl >> 24)& 0x0FF)
#define ACTION_SLEWRATE(Frequency, DimmConfig, SlewRate) \
PSO_ACTION_SLEWRATE, 10, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
(SlewRate & 0x0FF), ((SlewRate >> 8)& 0x0FF), ((SlewRate >> 16)& 0x0FF), ((SlewRate >> 24)& 0x0FF)
#define ACTION_SPEEDLIMIT(DimmConfig, Dimms, SpeedLimit15, SpeedLimit135, SpeedLimit125) \
PSO_ACTION_SPEEDLIMIT, 9, \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), Dimms, \
(SpeedLimit15 & 0x0FF), ((SpeedLimit15 >> 8)& 0x0FF), \
(SpeedLimit135 & 0x0FF), ((SpeedLimit135 >> 8)& 0x0FF), \
(SpeedLimit125 & 0x0FF), ((SpeedLimit125 >> 8)& 0x0FF)
/*----------------------------------------------------------------------------------------
* END OF CONDITIONAL OVERRIDE TABLE MACROS
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* TABLE DRIVEN OVERRIDE MACROS
*----------------------------------------------------------------------------------------
*/
/// Configuration sub-descriptors
typedef enum {
CONFIG_GENERAL, ///< CONFIG_GENERAL
CONFIG_SPEEDLIMIT, ///< CONFIG_SPEEDLIMIT
CONFIG_RC2IBT, ///< CONFIG_RC2IBT
CONFIG_DONT_CARE, ///< CONFIG_DONT_CARE
} Config_Type;
// ====================
// Configuration Macros
// ====================
#define TBLDRV_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig) \
PSO_TBLDRV_CONFIG, 9, \
CONFIG_GENERAL, \
DimmPerCH, DimmVolt, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF)
#define TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE(DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm) \
PSO_TBLDRV_CONFIG, 7, \
CONFIG_SPEEDLIMIT, \
DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm
#define TBLDRV_RC2IBT_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig, NumOfReg) \
PSO_TBLDRV_CONFIG, 10, \
CONFIG_RC2IBT, \
DimmPerCH, DimmVolt, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
NumOfReg
//==================
// Overriding Macros
//==================
#define TBLDRV_CONFIG_ENTRY_SPEEDLIMIT(SpeedLimit1_5, SpeedLimit1_35, SpeedLimit1_25) \
PSO_TBLDRV_SPEEDLIMIT, 6, \
(SpeedLimit1_5 & 0x0FF), ((SpeedLimit1_5 >> 8)& 0x0FF), \
(SpeedLimit1_35 & 0x0FF), ((SpeedLimit1_35 >> 8)& 0x0FF), \
(SpeedLimit1_25 & 0x0FF), ((SpeedLimit1_25 >> 8)& 0x0FF)
#define TBLDRV_CONFIG_ENTRY_ODT_RTTNOM(TgtCS, RttNom) \
PSO_TBLDRV_ODT_RTTNOM, 2, \
TgtCS, RttNom
#define TBLDRV_CONFIG_ENTRY_ODT_RTTWR(TgtCS, RttWr) \
PSO_TBLDRV_ODT_RTTWR, 2, \
TgtCS, RttWr
#define TBLDRV_CONFIG_ENTRY_ODTPATTERN(RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow) \
PSO_TBLDRV_ODTPATTERN, 16, \
((RdODTCSHigh) & 0x0FF), (((RdODTCSHigh) >> 8)& 0x0FF), (((RdODTCSHigh) >> 16)& 0x0FF), (((RdODTCSHigh) >> 24)& 0x0FF), \
((RdODTCSLow) & 0x0FF), (((RdODTCSLow) >> 8)& 0x0FF), (((RdODTCSLow) >> 16)& 0x0FF), (((RdODTCSLow) >> 24)& 0x0FF), \
((WrODTCSHigh) & 0x0FF), (((WrODTCSHigh) >> 8)& 0x0FF), (((WrODTCSHigh) >> 16)& 0x0FF), (((WrODTCSHigh) >> 24)& 0x0FF), \
((WrODTCSLow) & 0x0FF), (((WrODTCSLow) >> 8)& 0x0FF), (((WrODTCSLow) >> 16)& 0x0FF), (((WrODTCSLow) >> 24)& 0x0FF)
#define TBLDRV_CONFIG_ENTRY_ADDRTMG(AddrTmg) \
PSO_TBLDRV_ADDRTMG, 4, \
((AddrTmg) & 0x0FF), (((AddrTmg) >> 8)& 0x0FF), (((AddrTmg) >> 16)& 0x0FF), (((AddrTmg) >> 24)& 0x0FF)
#define TBLDRV_CONFIG_ENTRY_ODCCTRL(OdcCtrl) \
PSO_TBLDRV_ODCCTRL, 4, \
((OdcCtrl) & 0x0FF), (((OdcCtrl) >> 8)& 0x0FF), (((OdcCtrl) >> 16)& 0x0FF), (((OdcCtrl) >> 24)& 0x0FF)
#define TBLDRV_CONFIG_ENTRY_SLOWACCMODE(SlowAccMode) \
PSO_TBLDRV_SLOWACCMODE, 1, \
SlowAccMode
#define TBLDRV_CONFIG_ENTRY_RC2_IBT(TgtDimm, IBT) \
PSO_TBLDRV_RC2_IBT, 2, \
TgtDimm, IBT
#define TBLDRV_OVERRIDE_MR0_CL(RegValOfTcl, MR0CL13, MR0CL0) \
PSO_TBLDRV_CONFIG, 1, \
CONFIG_DONT_CARE, \
PSO_TBLDRV_MR0_CL, 3, \
RegValOfTcl, MR0CL13, MR0CL0
#define TBLDRV_OVERRIDE_MR0_WR(RegValOfTwr, MR0WR) \
PSO_TBLDRV_CONFIG, 1, \
CONFIG_DONT_CARE, \
PSO_TBLDRV_MR0_WR, 2, \
RegValOfTwr, MR0WR
#define TBLDRV_OVERRIDE_RC10_OPSPEED(Frequency, MR10OPSPEED) \
PSO_TBLDRV_CONFIG, 1, \
CONFIG_DONT_CARE, \
PSO_TBLDRV_RC10_OPSPEED, 5, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
MR10OPSPEED
#define TBLDRV_CONFIG_ENTRY_LRDMM_IBT(F0RC8, F1RC0, F1RC1, F1RC2) \
PSO_TBLDRV_LRDIMM_IBT, 4, \
F0RC8, F1RC0, F1RC1, F1RC2
#define TBLDRV_CONFIG_ENTRY_2D_TRAINING(Training2dMode) \
PSO_TBLDRV_2D_TRAINING, 1, \
Training2dMode
//============================
// Macros for removing entries
//============================
#define INVALID_CONFIG_FLAG 0x8000
#define TBLDRV_INVALID_CONFIG \
PSO_TBLDRV_INVALID_TYPE, 0
/*----------------------------------------------------------------------------------------
* END OF TABLE DRIVEN OVERRIDE MACROS
*----------------------------------------------------------------------------------------
*/
#endif // _PLATFORM_MEMORY_CONFIGURATION_H_

164
src/vendorcode/amd/agesa/f16kb/Include/Topology.h
View File

@ -1,164 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Topology interface definitions.
*
* Contains AMD AGESA internal interface for topology related data which
* is consumed by code other than HyperTransport init (and produced by
* HyperTransport init.)
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _TOPOLOGY_H_
#define _TOPOLOGY_H_
// Defines for limiting data structure maximum allocation and limit checking.
#define MAX_NODES 8
#define MAX_SOCKETS MAX_NODES
#define MAX_DIES 2
// Defines useful with package link
#define HT_LIST_MATCH_INTERNAL_LINK_0 0xFA
#define HT_LIST_MATCH_INTERNAL_LINK_1 0xFB
#define HT_LIST_MATCH_INTERNAL_LINK_2 0xFC
/**
* Hop Count Table.
* This is a heap data structure. The Hops array is filled as a size x size matrix.
* The unused space, if any, is all at the end.
*/
typedef struct {
UINT8 Size; ///< The row and column size of actual hop count data */
UINT8 Hops[MAX_NODES * MAX_NODES]; ///< Room for a dynamic two dimensional array of [size][size] */
} HOP_COUNT_TABLE;
/**
* Socket and Module to Node Map Item.
* Provide the Node Id and core id range for each module in each processor.
*/
typedef struct {
UINT8 Node; ///< The module's Node id.
UINT8 LowCore; ///< The lowest processor core id for this module.
UINT8 HighCore; ///< The highest processor core id for this module.
UINT8 EnabledComputeUnits; ///< The value of Enabled for this processor module.
UINT8 DualCoreComputeUnits; ///< The value of DualCore for this processor module.
UINT8 TripleCoreComputeUnits;///< The value of TripleCore for this processor module.
UINT8 QuadCoreComputeUnits; ///< The value of QuadCore for this processor module.
} SOCKET_DIE_TO_NODE_ITEM;
/**
* Socket and Module to Node Map.
* This type is a pointer to the actual map, it can be used for a struct item or
* for typecasting a heap buffer pointer.
*/
typedef SOCKET_DIE_TO_NODE_ITEM (*SOCKET_DIE_TO_NODE_MAP)[MAX_SOCKETS][MAX_DIES];
/**
* Node id to Socket Die Map Item.
*/
typedef struct {
UINT8 Socket; ///< socket of the processor containing the Node.
UINT8 Die; ///< the module in the processor which is Node.
} NODE_TO_SOCKET_DIE_ITEM;
/**
* Node id to Socket Die Map.
*/
typedef NODE_TO_SOCKET_DIE_ITEM (*NODE_TO_SOCKET_DIE_MAP)[MAX_NODES];
/**
* Provide AP core with socket and node context at start up.
* This information is posted to the AP cores using a register as a mailbox.
*/
typedef struct {
UINT32 Node:4; ///< The node id of Core's node.
UINT32 Socket:4; ///< The socket of this Core's node.
UINT32 Module:2; ///< The internal module number for Core's node.
UINT32 ModuleType:2; ///< Single Module = 0, Multi-module = 1.
UINT32 :20; ///< Reserved
} AP_MAIL_INFO_FIELDS;
/**
* AP info fields can be written and read to a register.
*/
typedef union {
UINT32 Info; ///< Just a number for register access, or opaque passing.
AP_MAIL_INFO_FIELDS Fields; ///< access to the info fields.
} AP_MAIL_INFO;
/**
* Provide AP core with system degree and system core number at start up.
* This information is posted to the AP cores using a register as a mailbox.
*/
typedef struct {
UINT32 SystemDegree:3; ///< The number of connected links
UINT32 :3; ///< Reserved
UINT32 HeapIndex:6; ///< The zero-based system core number
UINT32 :20; ///< Reserved
} AP_MAIL_EXT_INFO_FIELDS;
/**
* AP info fields can be written and read to a register.
*/
typedef union {
UINT32 Info; ///< Just a number for register access, or opaque passing.
AP_MAIL_EXT_INFO_FIELDS Fields; ///< access to the info fields.
} AP_MAIL_EXT_INFO;
/**
* AP Info mailbox set.
*/
typedef struct {
AP_MAIL_INFO ApMailInfo; ///< The AP mail info
AP_MAIL_EXT_INFO ApMailExtInfo; ///< The extended AP mail info
} AP_MAILBOXES;
/**
* Provide a northbridge to package mapping for link assignments.
*
*/
typedef struct {
UINT8 Link; ///< The Node's link
UINT8 Module; ///< The internal module position of Node
UINT8 PackageLink; ///< The corresponding package link
} PACKAGE_HTLINK_MAP_ITEM;
/**
* A Processor's complete set of link assignments
*/
typedef PACKAGE_HTLINK_MAP_ITEM (*PACKAGE_HTLINK_MAP)[];
#endif // _TOPOLOGY_H_

135
src/vendorcode/amd/agesa/f16kb/Legacy/Proc/Dispatcher.c
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@ -1,135 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD binary block interface
*
* Contains the block entry function dispatcher
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Legacy
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Dispatcher.h"
#include "Options.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE LEGACY_PROC_DISPATCHER_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
extern CONST DISPATCH_TABLE DispatchTable[];
extern AMD_MODULE_HEADER mCpuModuleID;
/*---------------------------------------------------------------------------------------*/
/**
* The Dispatcher is the entry point into the AGESA software. It takes a function
* number as entry parameter in order to invoke the published function
*
* @param[in,out] ConfigPtr
*
* @return AGESA Status.
*
*/
AGESA_STATUS
CALLCONV
AmdAgesaDispatcher (
IN OUT VOID *ConfigPtr
)
{
AGESA_STATUS Status;
MODULE_ENTRY ModuleEntry;
DISPATCH_TABLE *Entry;
Status = AGESA_UNSUPPORTED;
ModuleEntry = NULL;
Entry = (DISPATCH_TABLE *) DispatchTable;
while (Entry->FunctionId != 0) {
if ((((AMD_CONFIG_PARAMS *) ConfigPtr)->Func) == Entry->FunctionId) {
Status = Entry->EntryPoint (ConfigPtr);
break;
}
Entry++;
}
// 2. Try next dispatcher if possible, and we have not already got status back
if ((mCpuModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) {
ModuleEntry = (MODULE_ENTRY) mCpuModuleID.NextBlock->ModuleDispatcher;
if (ModuleEntry != NULL) {
Status = (*ModuleEntry) (ConfigPtr);
}
}
return (Status);
}
/*---------------------------------------------------------------------------------------*/
/**
* The host environment interface of callout.
*
* @param[in] Func
* @param[in] Data
* @param[in,out] ConfigPtr
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
CALLCONV
AmdAgesaCallout (
IN UINT32 Func,
IN UINTN Data,
IN OUT VOID *ConfigPtr
)
{
UINT32 Result;
Result = AGESA_UNSUPPORTED;
if (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr == NULL) {
return Result;
}
Result = (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr) (Func, Data, ConfigPtr);
return (Result);
}

3
src/vendorcode/amd/agesa/f16kb/Legacy/Proc/Makefile.inc
View File

@ -1,3 +0,0 @@
libagesa-y += Dispatcher.c
libagesa-y += agesaCallouts.c
libagesa-y += hobTransfer.c

486
src/vendorcode/amd/agesa/f16kb/Legacy/Proc/agesaCallouts.c
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@ -1,486 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD CPU AGESA Callout Functions
*
* Contains code to set / get useful platform information.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Common
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*****************************************************************************
* AMD Generic Encapsulated Software Architecture
*
* Description: agesaCallouts.c - AGESA Call out functions
*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Dispatcher.h"
#include "cpuServices.h"
#include "Ids.h"
#include "FchPlatform.h"
#include "Filecode.h"
#include "FchPlatform.h"
#define FILECODE LEGACY_PROC_AGESACALLOUTS_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S - (AGESA ONLY)
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
*
* Call the host environment interface to do the warm or cold reset.
*
* @param[in] ResetType Warm or Cold Reset is requested
* @param[in,out] StdHeader Config header
*
*/
VOID
AgesaDoReset (
IN UINTN ResetType,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
WARM_RESET_REQUEST Request;
// Clear warm request bit and set state bits to the current post stage
GetWarmResetFlag (StdHeader, &Request);
Request.RequestBit = FALSE;
Request.StateBits = Request.PostStage;
SetWarmResetFlag (StdHeader, &Request);
Status = AmdAgesaCallout (AGESA_DO_RESET, (UINT32)ResetType, (VOID *) StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
*
* Call the host environment interface to allocate buffer in main system memory.
*
* @param[in] FcnData
* @param[in,out] AllocParams Heap manager parameters
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaAllocateBuffer (
IN UINTN FcnData,
IN OUT AGESA_BUFFER_PARAMS *AllocParams
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_ALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) AllocParams);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to deallocate buffer in main system memory.
*
* @param[in] FcnData
* @param[in,out] DeallocParams Heap Manager parameters
*
* @return The AGESA Status returned from the callout.
*/
AGESA_STATUS
AgesaDeallocateBuffer (
IN UINTN FcnData,
IN OUT AGESA_BUFFER_PARAMS *DeallocParams
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_DEALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) DeallocParams);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
*
* Call the host environment interface to Locate buffer Pointer in main system memory
*
* @param[in] FcnData
* @param[in,out] LocateParams Heap manager parameters
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaLocateBuffer (
IN UINTN FcnData,
IN OUT AGESA_BUFFER_PARAMS *LocateParams
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_LOCATE_BUFFER, (UINT32)FcnData, (VOID *) LocateParams);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to launch APs
*
* @param[in] ApicIdOfCore
* @param[in,out] LaunchApParams
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaRunFcnOnAp (
IN UINTN ApicIdOfCore,
IN AP_EXE_PARAMS *LaunchApParams
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_RUNFUNC_ONAP, (UINT32)ApicIdOfCore, (VOID *) LaunchApParams);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to read an SPD's content.
*
* @param[in] FcnData
* @param[in,out] ReadSpd
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaReadSpd (
IN UINTN FcnData,
IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_READ_SPD, (UINT32)FcnData, ReadSpd);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to read an SPD's content.
*
* @param[in] FcnData
* @param[in,out] ReadSpd
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaReadSpdRecovery (
IN UINTN FcnData,
IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_READ_SPD_RECOVERY, (UINT32)FcnData, ReadSpd);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] FcnData
* @param[in,out] MemData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaHookBeforeDramInitRecovery (
IN UINTN FcnData,
IN OUT MEM_DATA_STRUCT *MemData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, (UINT32)FcnData, MemData);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] SocketIdModuleId - (SocketID << 8) | ModuleId
* @param[in,out] MemData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaHookBeforeDramInit (
IN UINTN SocketIdModuleId,
IN OUT MEM_DATA_STRUCT *MemData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DRAM_INIT, (UINT32)SocketIdModuleId, MemData);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] SocketIdModuleId - (SocketID << 8) | ModuleId
* @param[in,out] MemData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaHookBeforeDQSTraining (
IN UINTN SocketIdModuleId,
IN OUT MEM_DATA_STRUCT *MemData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DQS_TRAINING, (UINT32)SocketIdModuleId, MemData);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] FcnData
* @param[in,out] MemData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaHookBeforeExitSelfRefresh (
IN UINTN FcnData,
IN OUT MEM_DATA_STRUCT *MemData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_EXIT_SELF_REF, (UINT32)FcnData, MemData);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] Data
* @param[in,out] IdsCalloutData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaGetIdsData (
IN UINTN Data,
IN OUT IDS_CALLOUT_STRUCT *IdsCalloutData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_GET_IDS_INIT_DATA, (UINT32)Data, IdsCalloutData);
return Status;
}
/*----------------------------------------------------------------------------------------*/
/**
* PCIE slot reset control
*
*
*
* @param[in] FcnData Function data
* @param[in] ResetInfo Reset information
* @retval Status Agesa status
*/
AGESA_STATUS
AgesaPcieSlotResetControl (
IN UINTN FcnData,
IN PCIe_SLOT_RESET_INFO *ResetInfo
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_GNB_PCIE_SLOT_RESET, (UINT32) FcnData, ResetInfo);
return Status;
}
/*----------------------------------------------------------------------------------------*/
/**
* Get VBIOS image
*
*
*
* @param[in] FcnData Function data
* @param[in] VbiosImageInfo VBIOS image info
* @retval Status Agesa status
*/
AGESA_STATUS
AgesaGetVbiosImage (
IN UINTN FcnData,
IN OUT GFX_VBIOS_IMAGE_INFO *VbiosImageInfo
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_GNB_GFX_GET_VBIOS_IMAGE, (UINT32) FcnData, VbiosImageInfo);
return Status;
}
/*----------------------------------------------------------------------------------------*/
/**
* OEM callout function for FCH data override
*
*
* @param[in] FchData FCH data pointer
* @retval Status This feature is not supported
*/
AGESA_STATUS
AgesaFchOemCallout (
IN VOID *FchData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout(AGESA_FCH_OEM_CALLOUT, (UINTN)FchData, ((FCH_DATA_BLOCK *)FchData)->StdHeader);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Optional call to the host environment interface to change the external Vref for 2D Training.
*
* @param[in] SocketIdModuleId - (SocketID << 8) | ModuleId
* @param[in,out] MemData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaExternal2dTrainVrefChange (
IN UINTN SocketIdModuleId,
IN OUT MEM_DATA_STRUCT *MemData
)
{
AGESA_STATUS Status = AGESA_UNSUPPORTED;
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call to the host environment interface to change an external Voltage
*
* @param[in] SocketIdModuleId - (SocketID << 8) | ModuleId
* @param[in,out] *AdjustValue - Pointer to VOLTAGE_ADJUST structure
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaExternalVoltageAdjust (
IN UINTN SocketIdModuleId,
IN OUT VOLTAGE_ADJUST *AdjustValue
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_EXTERNAL_VOLTAGE_ADJUST, (UINT32)SocketIdModuleId, AdjustValue);
return Status;
}

421
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@ -1,421 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Hob Transfer functions.
*
* Contains code that copy Heap to temp memory or main memory.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Legacy/Proc
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuRegisters.h"
#include "GeneralServices.h"
#include "cpuServices.h"
#include "cpuCacheInit.h"
#include "cpuFamilyTranslation.h"
#include "heapManager.h"
#include "cpuLateInit.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE LEGACY_PROC_HOBTRANSFER_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
UINT64
HeapGetBaseAddressInTempMem (
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* P U B L I C F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
extern BUILD_OPT_CFG UserOptions;
/* -----------------------------------------------------------------------------*/
/**
*
* CopyHeapToTempRamAtPost
*
* This function copies BSP heap content to RAM
*
* @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
*
* @retval AGESA_STATUS
*
*/
AGESA_STATUS
CopyHeapToTempRamAtPost (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 *BaseAddressInCache;
UINT8 *BaseAddressInTempMem;
UINT8 *Source;
UINT8 *Destination;
UINT8 AlignTo16ByteInCache;
UINT8 AlignTo16ByteInTempMem;
UINT8 Ignored;
UINT32 SizeOfNodeData;
UINT32 TotalSize;
UINT32 HeapRamFixMtrr;
UINT32 HeapRamVariableMtrr;
UINT32 HeapInCacheOffset;
UINT64 MsrData;
UINT64 VariableMtrrBase;
UINT64 VariableMtrrMask;
UINTN AmdHeapRamAddress;
AGESA_STATUS IgnoredStatus;
BUFFER_NODE *HeapInCache;
BUFFER_NODE *HeapInTempMem;
HEAP_MANAGER *HeapManagerInCache;
HEAP_MANAGER *HeapManagerInTempMem;
CACHE_INFO *CacheInfoPtr;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
AmdHeapRamAddress = (UINTN) UserOptions.CfgHeapDramAddress;
//
//If the user define address above 1M, Mem Init has already set
//whole available memory as WB cacheable.
//
if (AmdHeapRamAddress < 0x100000) {
// Region below 1MB
// Fixed MTRR region
// turn on modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
if (AmdHeapRamAddress >= 0xC0000) {
//
// 0xC0000 ~ 0xFFFFF
//
HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX4k_C0000 + (((AmdHeapRamAddress >> 16) & 0x3) * 2));
MsrData = AMD_MTRR_FIX4K_UC_DRAM;
LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader);
LibAmdMsrWrite ((HeapRamFixMtrr + 1), &MsrData, StdHeader);
} else if (AmdHeapRamAddress >= 0x80000) {
//
// 0x80000~0xBFFFF
//
HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX16k_80000 + ((AmdHeapRamAddress >> 17) & 0x1));
MsrData = AMD_MTRR_FIX16K_UC_DRAM;
LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader);
} else {
//
// 0x0 ~ 0x7FFFF
//
LibAmdMsrRead (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
MsrData = MsrData & (~(0xFF << (8 * ((AmdHeapRamAddress >> 16) & 0x7))));
MsrData = MsrData | (AMD_MTRR_FIX64K_UC_DRAM << (8 * ((AmdHeapRamAddress >> 16) & 0x7)));
LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
}
// Turn on MTRR enable bit and turn off modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x40000;
MsrData &= 0xFFFFFFFFFFF7FFFF;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
} else {
// Region above 1MB
// Variable MTRR region
// Get family specific cache Info
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader);
// Find an empty MTRRphysBase/MTRRphysMask
for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE;
HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0;
HeapRamVariableMtrr--) {
LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
if ((VariableMtrrBase == 0) && (VariableMtrrMask == 0)) {
break;
}
}
if (HeapRamVariableMtrr < AMD_MTRR_VARIABLE_BASE0) {
// All variable MTRR is used.
ASSERT (FALSE);
}
// Set variable MTRR base and mask
// If the address ranges of two or more MTRRs overlap
// and if at least one of the memory types is UC, the UC memory type is used.
VariableMtrrBase = (UINT64) (AmdHeapRamAddress & CacheInfoPtr->HeapBaseMask);
VariableMtrrMask = CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK;
LibAmdMsrWrite (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
LibAmdMsrWrite ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
}
// Copying Heap content
if (IsBsp (StdHeader, &IgnoredStatus)) {
TotalSize = sizeof (HEAP_MANAGER);
SizeOfNodeData = 0;
AlignTo16ByteInTempMem = 0;
BaseAddressInCache = (UINT8 *)(UINTN) StdHeader->HeapBasePtr;
HeapManagerInCache = (HEAP_MANAGER *) BaseAddressInCache;
HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset;
HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset);
BaseAddressInTempMem = (UINT8 *) (UINTN) UserOptions.CfgHeapDramAddress;
HeapManagerInTempMem = (HEAP_MANAGER *) BaseAddressInTempMem;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
// copy heap from cache to temp memory.
// only heap with persist great than HEAP_LOCAL_CACHE will be copied.
// Note: Only copy heap with persist greater than HEAP_LOCAL_CACHE.
while (HeapInCacheOffset != AMD_HEAP_INVALID_HEAP_OFFSET) {
if (HeapInCache->Persist > HEAP_LOCAL_CACHE) {
AlignTo16ByteInCache = HeapInCache->PadSize;
AlignTo16ByteInTempMem = (UINT8) ((0x10 - (((UINTN) (VOID *) HeapInTempMem + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF);
SizeOfNodeData = HeapInCache->BufferSize - AlignTo16ByteInCache;
TotalSize = (UINT32) (TotalSize + sizeof (BUFFER_NODE) + SizeOfNodeData + AlignTo16ByteInTempMem);
Source = (UINT8 *) HeapInCache + sizeof (BUFFER_NODE) + AlignTo16ByteInCache;
Destination = (UINT8 *) HeapInTempMem + sizeof (BUFFER_NODE) + AlignTo16ByteInTempMem;
LibAmdMemCopy (HeapInTempMem, HeapInCache, sizeof (BUFFER_NODE), StdHeader);
LibAmdMemCopy (Destination, Source, SizeOfNodeData, StdHeader);
HeapInTempMem->OffsetOfNextNode = TotalSize;
HeapInTempMem->BufferSize = SizeOfNodeData + AlignTo16ByteInTempMem;
HeapInTempMem->PadSize = AlignTo16ByteInTempMem;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
}
HeapInCacheOffset = HeapInCache->OffsetOfNextNode;
HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset);
}
// initialize heap manager
if (TotalSize == sizeof (HEAP_MANAGER)) {
// heap is empty
HeapManagerInTempMem->UsedSize = sizeof (HEAP_MANAGER);
HeapManagerInTempMem->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET;
HeapManagerInTempMem->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER);
} else {
// heap is NOT empty
HeapManagerInTempMem->UsedSize = TotalSize;
HeapManagerInTempMem->FirstActiveBufferOffset = sizeof (HEAP_MANAGER);
HeapManagerInTempMem->FirstFreeSpaceOffset = TotalSize;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize - SizeOfNodeData - AlignTo16ByteInTempMem - sizeof (BUFFER_NODE));
HeapInTempMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
}
// heap signature
HeapManagerInCache->Signature = 0x00000000;
HeapManagerInTempMem->Signature = HEAP_SIGNATURE_VALID;
// Free space node
HeapInTempMem->BufferSize = (UINT32) (AMD_HEAP_SIZE_PER_CORE - TotalSize);
HeapInTempMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
}
StdHeader->HeapStatus = HEAP_TEMP_MEM;
StdHeader->HeapBasePtr = HeapGetBaseAddressInTempMem (StdHeader);
return AGESA_SUCCESS;
}
/* -----------------------------------------------------------------------------*/
/**
*
* CopyHeapToMainRamAtPost
*
* This function copies Temp Ram heap content to Main Ram
*
* @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
*
* @retval AGESA_STATUS
*
*/
AGESA_STATUS
CopyHeapToMainRamAtPost (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 *BaseAddressInTempMem;
UINT8 *BaseAddressInMainMem;
UINT8 *Source;
UINT8 *Destination;
UINT8 AlignTo16ByteInTempMem;
UINT8 AlignTo16ByteInMainMem;
UINT8 Ignored;
UINT32 SizeOfNodeData;
UINT32 TotalSize;
UINT32 HeapInTempMemOffset;
UINT32 HeapRamVariableMtrr;
UINT64 VariableMtrrBase;
UINT64 VariableMtrrMask;
AGESA_STATUS IgnoredStatus;
BUFFER_NODE *HeapInTempMem;
BUFFER_NODE *HeapInMainMem;
HEAP_MANAGER *HeapManagerInTempMem;
HEAP_MANAGER *HeapManagerInMainMem;
AGESA_BUFFER_PARAMS AgesaBuffer;
CACHE_INFO *CacheInfoPtr;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
if (IsBsp (StdHeader, &IgnoredStatus)) {
TotalSize = sizeof (HEAP_MANAGER);
SizeOfNodeData = 0;
AlignTo16ByteInMainMem = 0;
BaseAddressInTempMem = (UINT8 *)(UINTN) StdHeader->HeapBasePtr;
HeapManagerInTempMem = (HEAP_MANAGER *)(UINTN) StdHeader->HeapBasePtr;
HeapInTempMemOffset = HeapManagerInTempMem->FirstActiveBufferOffset;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset);
AgesaBuffer.StdHeader = *StdHeader;
AgesaBuffer.BufferHandle = AMD_HEAP_IN_MAIN_MEMORY_HANDLE;
AgesaBuffer.BufferLength = AMD_HEAP_SIZE_PER_CORE;
if (AgesaAllocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) {
return AGESA_ERROR;
}
BaseAddressInMainMem = (UINT8 *) AgesaBuffer.BufferPointer;
HeapManagerInMainMem = (HEAP_MANAGER *) BaseAddressInMainMem;
HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize);
LibAmdMemFill (BaseAddressInMainMem, 0x00, AMD_HEAP_SIZE_PER_CORE, StdHeader);
// copy heap from temp memory to main memory.
// only heap with persist great than HEAP_TEMP_MEM will be copied.
// Note: Only copy heap buffers with persist greater than HEAP_TEMP_MEM.
while (HeapInTempMemOffset != AMD_HEAP_INVALID_HEAP_OFFSET) {
if (HeapInTempMem->Persist > HEAP_TEMP_MEM) {
AlignTo16ByteInTempMem = HeapInTempMem->PadSize;
AlignTo16ByteInMainMem = (UINT8) ((0x10 - (((UINTN) (VOID *) HeapInMainMem + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF);
SizeOfNodeData = HeapInTempMem->BufferSize - AlignTo16ByteInTempMem;
TotalSize = (UINT32) (TotalSize + sizeof (BUFFER_NODE) + SizeOfNodeData + AlignTo16ByteInMainMem);
Source = (UINT8 *) HeapInTempMem + sizeof (BUFFER_NODE) + AlignTo16ByteInTempMem;
Destination = (UINT8 *) HeapInMainMem + sizeof (BUFFER_NODE) + AlignTo16ByteInMainMem;
LibAmdMemCopy (HeapInMainMem, HeapInTempMem, sizeof (BUFFER_NODE), StdHeader);
LibAmdMemCopy (Destination, Source, SizeOfNodeData, StdHeader);
HeapInMainMem->OffsetOfNextNode = TotalSize;
HeapInMainMem->BufferSize = SizeOfNodeData + AlignTo16ByteInMainMem;
HeapInMainMem->PadSize = AlignTo16ByteInMainMem;
HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize);
}
HeapInTempMemOffset = HeapInTempMem->OffsetOfNextNode;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset);
}
// initialize heap manager
if (TotalSize == sizeof (HEAP_MANAGER)) {
// heap is empty
HeapManagerInMainMem->UsedSize = sizeof (HEAP_MANAGER);
HeapManagerInMainMem->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET;
HeapManagerInMainMem->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER);
} else {
// heap is NOT empty
HeapManagerInMainMem->UsedSize = TotalSize;
HeapManagerInMainMem->FirstActiveBufferOffset = sizeof (HEAP_MANAGER);
HeapManagerInMainMem->FirstFreeSpaceOffset = TotalSize;
HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize - SizeOfNodeData - AlignTo16ByteInMainMem - sizeof (BUFFER_NODE));
HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize);
}
// heap signature
HeapManagerInTempMem->Signature = 0x00000000;
HeapManagerInMainMem->Signature = HEAP_SIGNATURE_VALID;
// Free space node
HeapInMainMem->BufferSize = AMD_HEAP_SIZE_PER_CORE - TotalSize;
HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
}
// if address of heap in temp memory is above 1M, then we must used one variable MTRR.
if ( (UINTN) StdHeader->HeapBasePtr >= 0x100000) {
// Find out which variable MTRR was used in CopyHeapToTempRamAtPost.
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader);
for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE;
HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0;
HeapRamVariableMtrr--) {
LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
if ((VariableMtrrBase == (UINT64) (UINTN) (StdHeader->HeapBasePtr & CacheInfoPtr->HeapBaseMask)) &&
(VariableMtrrMask == (UINT64) (CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK))) {
break;
}
}
if (HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0) {
// Clear variable MTRR which set in CopyHeapToTempRamAtPost.
VariableMtrrBase = 0;
VariableMtrrMask = 0;
LibAmdMsrWrite (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
LibAmdMsrWrite ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
}
}
return AGESA_SUCCESS;
}
/* -----------------------------------------------------------------------------*/
/**
*
* HeapGetBaseAddressInTempMem
*
* This function gets heap base address in HEAP_TEMP_MEM phase
*
* @param[in] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
*
* @retval UINT64 - Heap base address in HEAP_TEMP_MEM phase
*
*/
UINT64
HeapGetBaseAddressInTempMem (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return UserOptions.CfgHeapDramAddress;
}

54
src/vendorcode/amd/agesa/f16kb/Makefile.inc
View File

@ -1,54 +0,0 @@
#*****************************************************************************
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# * Neither the name of Advanced Micro Devices, Inc. nor the names of
# its contributors may be used to endorse or promote products derived
# from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#*****************************************************************************
# AGESA V5 Files
AGESA_ROOT = src/vendorcode/amd/agesa/f16kb
AGESA_AUTOINCLUDES := $(shell find $(AGESA_ROOT)/Proc -type d -exec echo -n "-I"{}" " \;)
AGESA_INC = -I$(src)/vendorcode/amd/include
AGESA_INC += -I$(AGESA_ROOT)
AGESA_INC += -I$(AGESA_ROOT)/../common
AGESA_INC += -I$(AGESA_ROOT)/Include
AGESA_INC += -I$(src)/mainboard/$(MAINBOARDDIR) # OptionsIds.h
BUILDOPTS_INCLUDES = -I$(AGESA_ROOT)/Config $(AGESA_INC) $(AGESA_AUTOINCLUDES)
# These are invalid, coreboot proper should not require
# use of AGESA internal header files.
CPPFLAGS_x86_ANY =
CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/Fch # FchPlatform.h
CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/Fch/Common # FchCommonCfg.h
CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/Common # AmdFch.h
CPPFLAGS_x86_32 += $(AGESA_INC) $(CPPFLAGS_x86_ANY)
CPPFLAGS_x86_64 += $(AGESA_INC) $(CPPFLAGS_x86_ANY)
#######################################################################
subdirs-y += Legacy/Proc
subdirs-y += $(dir $(shell cd $(dir); find Proc -name Makefile.inc))

198
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbC6State.c
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@ -1,198 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_16 Kabini C6 C-state feature support functions.
*
* Provides the functions necessary to initialize the C6 feature.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F16/KB
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuRegisters.h"
#include "cpuFeatures.h"
#include "cpuC6State.h"
#include "cpuApicUtilities.h"
#include "cpuF16PowerMgmt.h"
#include "F16KbPowerMgmt.h"
#include "cpuServices.h"
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
CODE_GROUP (G3_DXE)
RDATA_GROUP (G3_DXE)
#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBC6STATE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
BOOLEAN
STATIC
F16KbIsC6Supported (
IN C6_FAMILY_SERVICES *C6Services,
IN UINT32 Socket,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
STATIC
F16KbInitializeC6 (
IN C6_FAMILY_SERVICES *C6Services,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Is C6 supported on this CPU
*
* @param[in] C6Services Pointer to this CPU's C6 family services.
* @param[in] Socket This core's zero-based socket number.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @retval TRUE C6 state is supported.
* @retval FALSE C6 state is not supported.
*
*/
BOOLEAN
STATIC
F16KbIsC6Supported (
IN C6_FAMILY_SERVICES *C6Services,
IN UINT32 Socket,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader));
}
/*---------------------------------------------------------------------------------------*/
/**
* Enable C6 on a family 16h Kabini CPU.
*
* @param[in] C6Services Pointer to this CPU's C6 family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @return AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F16KbInitializeC6 (
IN C6_FAMILY_SERVICES *C6Services,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
CSTATE_CTRL1_REGISTER CstateCtrl1;
POPUP_PSTATE_REGISTER PopDownPstate;
CLK_PWR_TIMING_CTRL2_REGISTER ClkPwrTimingCtrl2;
if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
// Initialize F4x118
PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
// Set C-state Action Field 0
// bits[8] PwrGateEnCstAct0 = 0x1
// bits[9] PwrOffEnCstAct0 = 0x1
CstateCtrl1.PwrGateEnCstAct0 = 1;
CstateCtrl1.PwrOffEnCstAct0 = 1;
// Set C-state Action Field 1
// bits[24] PwrGateEnCstAct1 = 0x1
// bits[25] PwrOffEnCstAct1 = 0x1
CstateCtrl1.PwrGateEnCstAct1 = 1;
CstateCtrl1.PwrOffEnCstAct1 = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
// Initialize F3xA8[PopDownPstate] = F3xDC[HwPstateMaxVal]
PciAddress.AddressValue = CPTC2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader);
PciAddress.AddressValue = POPUP_PSTATE_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PopDownPstate, StdHeader);
PopDownPstate.PopDownPstate = ClkPwrTimingCtrl2.HwPstateMaxVal;
LibAmdPciWrite (AccessWidth32, PciAddress, &PopDownPstate, StdHeader);
} else if ((EntryPoint & (CPU_FEAT_AFTER_RESUME_MTRR_SYNC | CPU_FEAT_BEFORE_RELINQUISH_AP)) != 0) {
// Initialize F4x118
PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
// Set C-state Action Field 0
// bits[1] CacheFlushEnCstAct0 = 0x1
CstateCtrl1.CacheFlushEnCstAct0 = 1;
// Set C-state Action Field 1
// bits[17] CacheFlushEnCstAct1 = 0x1
CstateCtrl1.CacheFlushEnCstAct1 = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
}
return AGESA_SUCCESS;
}
CONST C6_FAMILY_SERVICES ROMDATA F16KbC6Support =
{
0,
F16KbIsC6Supported,
F16KbInitializeC6,
ReloadMicrocodePatchAfterMemInit
};

150
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCacheFlushOnHalt.c
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@ -1,150 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD CPU Cache Flush On Halt Function for Family 16h Kabini.
*
* Contains code to initialize Cache Flush On Halt feature for Family 16h Kabini.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x16/KB
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*----------------------------------------------------------------------------
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuRegisters.h"
#include "cpuServices.h"
#include "cpuFamilyTranslation.h"
#include "cpuPostInit.h"
#include "cpuF16PowerMgmt.h"
#include "F16KbPowerMgmt.h"
#include "cpuFeatures.h"
#include "Filecode.h"
CODE_GROUP (G3_DXE)
RDATA_GROUP (G3_DXE)
#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBCACHEFLUSHONHALT_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* TYPEDEFS AND STRUCTURES
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* PROTOTYPES OF LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
VOID
SetF16KbCacheFlushOnHaltRegister (
IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* P U B L I C F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/* -----------------------------------------------------------------------------*/
/**
* Enable Cpu Cache Flush On Halt Function
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*/
VOID
SetF16KbCacheFlushOnHaltRegister (
IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
CSTATE_CTRL1_REGISTER CstateCtrl1;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
// Set F4x118
PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
// Set C-state Action Field 0
// bits[11] NbClkGate0 = 0x1
// bits[12] SelfRefr0 = 0x1
CstateCtrl1.NbClkGate0 = 1;
CstateCtrl1.SelfRefr0 = 1;
// Set C-state Action Field 1
// bits[27] NbClkGate1 = 0x1
// bits[28] SelfRefr1 = 0x1
CstateCtrl1.NbClkGate1 = 1;
CstateCtrl1.SelfRefr1 = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
//Override the default setting
IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, NULL, StdHeader);
}
}
CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F16KbCacheFlushOnHalt =
{
0,
SetF16KbCacheFlushOnHaltRegister
};

261
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.c
View File

@ -1,261 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_16 Kabini after warm reset sequence for core P-states
*
* Performs the "Core Minimum P-State Transition Sequence After Warm Reset"
* as described in the BKDG.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x16/KB
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuF16PowerMgmt.h"
#include "F16KbPowerMgmt.h"
#include "cpuRegisters.h"
#include "GeneralServices.h"
#include "cpuApicUtilities.h"
#include "cpuFamilyTranslation.h"
#include "F16KbCoreAfterReset.h"
#include "Filecode.h"
CODE_GROUP (G3_DXE)
RDATA_GROUP (G3_DXE)
#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBCOREAFTERRESET_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
STATIC
F16KbPmCoreAfterResetPhase1OnCore (
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
STATIC
F16KbPmCoreAfterResetPhase2OnCore (
IN VOID *HwPsMaxVal,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Family 16h Kabini core 0 entry point for performing the necessary steps for core
* P-states after a warm reset has occurred.
*
* The steps are as follows:
* 1. Write 0 to MSRC001_0062[PstateCmd] on all cores in the processor.
* 2. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from
* MSRC001_00[6B:64] indexed by MSRC001_0071[CurPstateLimit].
* 3. Write MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] on all
* cores in the processor.
* 4. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from
* MSRC001_00[6B:64] indexed by MSRC001_0061[PstateMaxVal].
* 5. If MSRC001_0071[CurPstateLimit] != MSRC001_0071[CurPstate], wait for
* MSRC001_0071[CurCpuVid] = [CpuVid] from MSRC001_00[6B:64] indexed by
* MSRC001_0061[PstateMaxVal].
* 6. Wait for MSRC001_0063[CurPstate] = MSRC001_0062[PstateCmd].
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParamsPtr Service parameters
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F16KbPmCoreAfterReset (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Core;
UINT32 HwPsMaxVal;
PCI_ADDR PciAddress;
AP_TASK TaskPtr;
IDS_HDT_CONSOLE (CPU_TRACE, " F16KbPmCoreAfterReset\n");
GetCurrentCore (&Core, StdHeader);
ASSERT (Core == 0);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, FUNC_3, CPTC2_REG);
LibAmdPciRead (AccessWidth32, PciAddress, &HwPsMaxVal, StdHeader);
HwPsMaxVal = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &HwPsMaxVal)->HwPstateMaxVal;
// Launch each local core to perform steps 1 through 4.
TaskPtr.FuncAddress.PfApTask = F16KbPmCoreAfterResetPhase1OnCore;
TaskPtr.DataTransfer.DataSizeInDwords = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
// Launch each local core to perform steps 5 through 7.
TaskPtr.FuncAddress.PfApTaskI = F16KbPmCoreAfterResetPhase2OnCore;
TaskPtr.DataTransfer.DataSizeInDwords = 1;
TaskPtr.DataTransfer.DataPtr = &HwPsMaxVal;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
}
/*---------------------------------------------------------------------------------------
* L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Support routine for F16KbPmCoreAfterReset to perform MSR initialization on all
* cores of a family 16h socket.
*
* This function implements steps 1 - 3 on each core.
*
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
F16KbPmCoreAfterResetPhase1OnCore (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
BOOLEAN SkipStep3;
UINT64 CofvidSts;
UINT64 LocalMsrRegister;
UINT64 PstateCtrl;
IDS_HDT_CONSOLE (CPU_TRACE, " F16KbPmCoreAfterResetPhase1OnCore\n");
// 1. If MSRC001_0071[CurPstate] = MSRC001_0071[CurPstateLimit], then skip step 3 for that core
LibAmdMsrRead (MSR_COFVID_STS, &CofvidSts, StdHeader);
if (((COFVID_STS_MSR *) &CofvidSts)->CurPstate == ((COFVID_STS_MSR *) &CofvidSts)->CurPstateLimit) {
SkipStep3 = TRUE;
} else {
SkipStep3 = FALSE;
}
// 2. Write 0 to MSRC001_0062[PstateCmd] on all cores in the processor.
PstateCtrl = 0;
LibAmdMsrWrite (MSR_PSTATE_CTL, &PstateCtrl, StdHeader);
// 3. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from
// MSRC001_00[6B:64] indexed by MSRC001_0071[CurPstateLimit].
if (!SkipStep3) {
do {
LibAmdMsrRead (MSR_COFVID_STS, &CofvidSts, StdHeader);
LibAmdMsrRead ((UINT32) (MSR_PSTATE_0 + (UINT32) (((COFVID_STS_MSR *) &CofvidSts)->CurPstateLimit)), &LocalMsrRegister, StdHeader);
} while ((((COFVID_STS_MSR *) &CofvidSts)->CurCpuFid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuFid) ||
(((COFVID_STS_MSR *) &CofvidSts)->CurCpuDid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuDid));
}
// 4. Write MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] on all
// cores in the processor.
LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader);
((PSTATE_CTRL_MSR *) &PstateCtrl)->PstateCmd = ((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal;
LibAmdMsrWrite (MSR_PSTATE_CTL, &PstateCtrl, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
* Support routine for F16KbPmCoreAfterReset to perform MSR initialization on all
* cores of a family 16h socket.
*
* This function implements steps 4 - 6 on each core.
*
* @param[in] HwPsMaxVal Index of the highest enabled HW P-state.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
F16KbPmCoreAfterResetPhase2OnCore (
IN VOID *HwPsMaxVal,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 TargetPsMsr;
UINT64 LocalMsrRegister;
UINT64 PstateCtrl;
IDS_HDT_CONSOLE (CPU_TRACE, " F16KbPmCoreAfterResetPhase2OnCore\n");
// 4. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from
// MSRC001_00[6B:64] indexed by D18F3xDC[PstateMaxVal].
LibAmdMsrRead ((*(UINT32 *) HwPsMaxVal) + MSR_PSTATE_0, &TargetPsMsr, StdHeader);
do {
LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
} while ((((COFVID_STS_MSR *) &LocalMsrRegister)->CurCpuFid != ((PSTATE_MSR *) &TargetPsMsr)->CpuFid) ||
(((COFVID_STS_MSR *) &LocalMsrRegister)->CurCpuDid != ((PSTATE_MSR *) &TargetPsMsr)->CpuDid));
// 5. If MSRC001_0071[CurPstateLimit] != MSRC001_0071[CurPstate], wait for
// MSRC001_0071[CurCpuVid] = [CpuVid] from MSRC001_00[6B:64] indexed by
// MSRC001_0061[PstateMaxVal].
if (((COFVID_STS_MSR *) &LocalMsrRegister)->CurPstateLimit != ((COFVID_STS_MSR *) &LocalMsrRegister)->CurPstate) {
do {
LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
} while (GetF16KbCurCpuVid (&LocalMsrRegister) != GetF16KbCpuVid (&TargetPsMsr));
}
// 6. Wait for MSRC001_0063[CurPstate] = MSRC001_0062[PstateCmd].
LibAmdMsrRead (MSR_PSTATE_CTL, &PstateCtrl, StdHeader);
do {
LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader);
} while (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate != ((PSTATE_CTRL_MSR *) &PstateCtrl)->PstateCmd);
}

78
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.h
View File

@ -1,78 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_16 Kabini after warm reset sequence for core P-states
*
* Contains code that provide power management functionality
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x16/KB
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _F16_KB_CORE_AFTER_RESET_H_
#define _F16_KB_CORE_AFTER_RESET_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
VOID
F16KbPmCoreAfterReset (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _F16_KB_CORE_AFTER_RESET_H_

195
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c
View File

@ -1,195 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_16 CPB Initialization
*
* Enables core performance boost.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/0x16/KB
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "GeneralServices.h"
#include "cpuFamilyTranslation.h"
#include "cpuF16PowerMgmt.h"
#include "F16KbPowerMgmt.h"
#include "cpuFeatures.h"
#include "cpuCpb.h"
#include "Filecode.h"
CODE_GROUP (G3_DXE)
RDATA_GROUP (G3_DXE)
#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBCPB_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
BOOLEAN
STATIC
F16KbIsCpbSupported (
IN CPB_FAMILY_SERVICES *CpbServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
STATIC
F16KbInitializeCpb (
IN CPB_FAMILY_SERVICES *CpbServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN UINT64 EntryPoint,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*---------------------------------------------------------------------------------------*/
/**
* BSC entry point for checking whether or not CPB is supported.
*
* @param[in] CpbServices The current CPU's family services.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] Socket Zero based socket number to check.
* @param[in] StdHeader Config handle for library and services.
*
* @retval TRUE CPB is supported.
* @retval FALSE CPB is not supported.
*
*/
BOOLEAN
STATIC
F16KbIsCpbSupported (
IN CPB_FAMILY_SERVICES *CpbServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrData;
BOOLEAN CpbSupported;
CPB_CTRL_REGISTER CpbControl;
PCI_ADDR PciAddress;
CpbSupported = FALSE;
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
if (CpbControl.NumBoostStates != 0) {
LibAmdMsrRead (MSR_PSTATE_0, &MsrData, StdHeader);
if (((PSTATE_MSR *) &MsrData)->PsEnable == 1) {
CpbSupported = TRUE;
}
}
return CpbSupported;
}
/*---------------------------------------------------------------------------------------*/
/**
* BSC entry point for enabling Core Performance Boost.
*
* Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
*
* @param[in] CpbServices The current CPU's family services.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] EntryPoint Current CPU feature dispatch point.
* @param[in] Socket Zero based socket number to check.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F16KbInitializeCpb (
IN CPB_FAMILY_SERVICES *CpbServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN UINT64 EntryPoint,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPB_CTRL_REGISTER CpbControl;
PCI_ADDR PciAddress;
F16_PSTATE_MSR PstateMsrData;
UINT32 Pbx;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
if ((CpbControl.BoostSrc == 0) && (CpbControl.NumBoostStates != 0)) {
// If any boosted P-state is still enabled, set BoostSrc = 1.
for (Pbx = 0; Pbx < CpbControl.NumBoostStates; Pbx++) {
LibAmdMsrRead (PS_REG_BASE + Pbx, (UINT64 *)&PstateMsrData, StdHeader);
if (PstateMsrData.PsEnable == 1) {
CpbControl.BoostSrc = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader);
break;
}
}
}
}
return AGESA_SUCCESS;
}
CONST CPB_FAMILY_SERVICES ROMDATA F16KbCpbSupport =
{
0,
F16KbIsCpbSupported,
F16KbInitializeCpb
};

369
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c
View File

@ -1,369 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD DMI Record Creation API, and related functions for Family16h Kabini.
*
* Contains code that produce the DMI related information.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x16/KB
* @e \$Revision: 87400 $ @e \$Date: 2013-02-01 12:14:44 -0600 (Fri, 01 Feb 2013) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuRegisters.h"
#include "cpuFamilyTranslation.h"
#include "cpuPstateTables.h"
#include "cpuLateInit.h"
#include "cpuF16Dmi.h"
#include "cpuF16PowerMgmt.h"
#include "F16KbPowerMgmt.h"
#include "cpuServices.h"
#include "Filecode.h"
CODE_GROUP (G3_DXE)
RDATA_GROUP (G3_DXE)
#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBDMI_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable;
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* Processor Family Table
*
*-------------------------------------------------------------------------------------*/
CONST CHAR8 ROMDATA str_A6[] = "AMD A6-";
CONST CHAR8 ROMDATA str_A4[] = "AMD A4-";
CONST CHAR8 ROMDATA str_E2[] = "AMD E2-";
CONST CHAR8 ROMDATA str_E1[] = "AMD E1-";
CONST CHAR8 ROMDATA str_GX[] = "AMD GX-";
/*---------------------------------------------------------------------------------------
* Processor Family Table
*
* 047h = "E-Series"
* 048h = "A-Series"
* 049h = "GX-Series"
*-------------------------------------------------------------------------------------*/
CONST CPU_T4_PROC_FAMILY ROMDATA F16KbFT3T4ProcFamily[] =
{
{str_A6, 0x48},
{str_A4, 0x48},
{str_E2, 0x47},
{str_E1, 0x47},
{str_GX, 0x49},
};
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
DmiF16KbGetInfo (
IN OUT CPU_TYPE_INFO *CpuInfoPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
DmiF16KbGetT4ProcFamily (
IN OUT UINT8 *T4ProcFamily,
IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable,
IN CPU_TYPE_INFO *CpuInfo,
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT8
DmiF16KbGetVoltage (
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
DmiF16KbGetMemInfo (
IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT16
DmiF16KbGetExtClock (
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/* -----------------------------------------------------------------------------*/
/**
*
* DmiF16KbGetInfo
*
* Get CPU type information
*
* @param[in,out] CpuInfoPtr Pointer to CPU_TYPE_INFO struct.
* @param[in] StdHeader Standard Head Pointer
*
*/
VOID
DmiF16KbGetInfo (
IN OUT CPU_TYPE_INFO *CpuInfoPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPUID_DATA CpuId;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader);
CpuInfoPtr->ExtendedFamily = (UINT8) (CpuId.EAX_Reg >> 20) & 0xFF; // bit 27:20
CpuInfoPtr->ExtendedModel = (UINT8) (CpuId.EAX_Reg >> 16) & 0xF; // bit 19:16
CpuInfoPtr->BaseFamily = (UINT8) (CpuId.EAX_Reg >> 8) & 0xF; // bit 11:8
CpuInfoPtr->BaseModel = (UINT8) (CpuId.EAX_Reg >> 4) & 0xF; // bit 7:4
CpuInfoPtr->Stepping = (UINT8) (CpuId.EAX_Reg & 0xF); // bit 3:0
CpuInfoPtr->PackageType = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
CpuInfoPtr->TotalCoreNumber = FamilySpecificServices->GetNumberOfPhysicalCores (FamilySpecificServices, StdHeader);
CpuInfoPtr->TotalCoreNumber--;
LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuId, StdHeader);
CpuInfoPtr->EnabledCoreNumber = (UINT8) (CpuId.ECX_Reg & 0xFF); // bit 7:0
switch (CpuInfoPtr->PackageType) {
case KB_SOCKET_FT3:
/// Use 'NONE' for BGA package
CpuInfoPtr->ProcUpgrade = P_UPGRADE_NONE;
break;
default:
CpuInfoPtr->ProcUpgrade = P_UPGRADE_UNKNOWN;
break;
}
// L1 Size & Associativity
LibAmdCpuidRead (AMD_CPUID_TLB_L1Cache, &CpuId, StdHeader);
CpuInfoPtr->CacheInfo.L1CacheSize = (UINT32) (((CpuId.ECX_Reg >> 24) + (CpuId.EDX_Reg >> 24)) * (CpuInfoPtr->TotalCoreNumber + 1));
CpuInfoPtr->CacheInfo.L1CacheAssoc = DMI_ASSOCIATIVE_2_WAY; // Per the BKDG, this is hard-coded to 2-Way.
// L2 Size & Associativity
LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuId, StdHeader);
CpuInfoPtr->CacheInfo.L2CacheSize = (UINT32) (CpuId.ECX_Reg >> 16);
CpuInfoPtr->CacheInfo.L2CacheAssoc = DMI_ASSOCIATIVE_16_WAY; // Per the BKDG, this is hard-coded to 16-Way.
// L3 Size & Associativity
CpuInfoPtr->CacheInfo.L3CacheSize = 0;
CpuInfoPtr->CacheInfo.L3CacheAssoc = DMI_ASSOCIATIVE_UNKNOWN;
}
/* -----------------------------------------------------------------------------*/
/**
*
* DmiF16KbGetT4ProcFamily
*
* Get type 4 processor family information
*
* @param[in,out] T4ProcFamily Pointer to type 4 processor family information.
* @param[in] *CpuDmiProcFamilyTable Pointer to DMI family special service
* @param[in] *CpuInfo Pointer to CPU_TYPE_INFO struct
* @param[in] StdHeader Standard Head Pointer
*
*/
VOID
DmiF16KbGetT4ProcFamily (
IN OUT UINT8 *T4ProcFamily,
IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable,
IN CPU_TYPE_INFO *CpuInfo,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CHAR8 NameString[49];
CONST CHAR8 *DmiString;
CONST VOID *DmiStringTable;
UINT8 NumberOfDmiString;
UINT8 i;
// Get name string from MSR_C001_00[30:35]
GetNameString (NameString, StdHeader);
// Get DMI String
DmiStringTable = NULL;
switch (CpuInfo->PackageType) {
case KB_SOCKET_FT3:
DmiStringTable = (CONST VOID *) &F16KbFT3T4ProcFamily[0];
NumberOfDmiString = sizeof (F16KbFT3T4ProcFamily) / sizeof (CPU_T4_PROC_FAMILY);
break;
default:
DmiStringTable = NULL;
NumberOfDmiString = 0;
break;
}
// Find out which DMI string matches current processor's name string
*T4ProcFamily = P_FAMILY_UNKNOWN;
if ((DmiStringTable != NULL) && (NumberOfDmiString != 0)) {
for (i = 0; i < NumberOfDmiString; i++) {
DmiString = (((CPU_T4_PROC_FAMILY *) DmiStringTable)[i]).Stringstart;
if (IsSourceStrContainTargetStr (NameString, DmiString, StdHeader)) {
*T4ProcFamily = (((CPU_T4_PROC_FAMILY *) DmiStringTable)[i]).T4ProcFamilySetting;
break;
}
}
}
}
/* -----------------------------------------------------------------------------*/
/**
*
* DmiF16KbGetVoltage
*
* Get the voltage value according to SMBIOS SPEC's requirement.
*
* @param[in] StdHeader Standard Head Pointer
*
* @retval Voltage - CPU Voltage.
*
*/
UINT8
DmiF16KbGetVoltage (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 MaxVid;
UINT8 Voltage;
UINT8 NumberBoostStates;
UINT64 MsrData;
PCI_ADDR TempAddr;
CPB_CTRL_REGISTER CpbCtrl;
// Voltage = 0x80 + (voltage at boot time * 10)
TempAddr.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, TempAddr, &CpbCtrl, StdHeader); // F4x15C
NumberBoostStates = (UINT8) CpbCtrl.NumBoostStates;
LibAmdMsrRead ((MSR_PSTATE_0 + NumberBoostStates), &MsrData, StdHeader);
MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid);
if ((MaxVid >= 0xF8)) {
Voltage = 0;
} else {
Voltage = (UINT8) ((155000L - (625 * MaxVid) + 5000) / 10000);
}
Voltage += 0x80;
return (Voltage);
}
/* -----------------------------------------------------------------------------*/
/**
*
* DmiF16KbGetMemInfo
*
* Get memory information.
*
* @param[in,out] CpuGetMemInfoPtr Pointer to CPU_GET_MEM_INFO struct.
* @param[in] StdHeader Standard Head Pointer
*
*/
VOID
DmiF16KbGetMemInfo (
IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 PciData;
PCI_ADDR PciAddress;
CpuGetMemInfoPtr->EccCapable = FALSE;
PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_2, 0x90);
LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
// Check if F2x90[DimmEccEn] is set
if ((PciData & 0x00080000) != 0) {
CpuGetMemInfoPtr->EccCapable = TRUE;
}
}
/* -----------------------------------------------------------------------------*/
/**
*
* DmiF16KbGetExtClock
*
* Get the external clock Speed
*
* @param[in] StdHeader Standard Head Pointer
*
* @retval ExtClock - CPU external clock Speed.
*
*/
UINT16
DmiF16KbGetExtClock (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return (EXTERNAL_CLOCK_100MHZ);
}
/* -----------------------------------------------------------------------------*/
CONST PROC_FAMILY_TABLE ROMDATA ProcFamily16KbDmiTable =
{
// This table is for Processor family 16h Kabini
AMD_FAMILY_16_KB, // ID for Family 16h Kabini
DmiF16KbGetInfo, // Transfer vectors for family
DmiF16KbGetT4ProcFamily, // Get type 4 processor family information
DmiF16KbGetVoltage, // specific routines (above)
DmiF16GetMaxSpeed,
DmiF16KbGetExtClock,
DmiF16KbGetMemInfo, // Get memory information
0,
NULL
};
/*---------------------------------------------------------------------------------------
* L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------
*/

120
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbEquivalenceTable.c
View File

@ -1,120 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_16 Kabini Equivalence Table related data
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x16/KB
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
#include "amdlib.h"
#include "cpuRegisters.h"
CODE_GROUP (G2_PEI)
RDATA_GROUP (G2_PEI)
#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBEQUIVALENCETABLE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
GetF16KbMicrocodeEquivalenceTable (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **KbEquivalenceTablePtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
STATIC CONST UINT16 ROMDATA stu1[] =
{
0x7001, 0x7001,
0x7000, 0x7000
};
/*---------------------------------------------------------------------------------------*/
/**
* Returns the appropriate microcode patch equivalent ID table.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] KbEquivalenceTablePtr Points to the first entry in the table.
* @param[out] NumberOfElements Number of valid entries in the table.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF16KbMicrocodeEquivalenceTable (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **KbEquivalenceTablePtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrDeCfg;
LibAmdMsrRead (0xC0011029, &MsrDeCfg, StdHeader);
if ((MsrDeCfg & BIT12) == 0) {
} else {
*NumberOfElements = ((sizeof (stu1) / sizeof (UINT16)) / 2);
*KbEquivalenceTablePtr = stu1;
}
}

178
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbHtc.c
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@ -1,178 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_16 Kabini thermal initialization
*
* Performs processor thermal initialization.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x16/KB
* @e \$Revision: 85817 $ @e \$Date: 2013-01-11 16:58:12 -0600 (Fri, 11 Jan 2013) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuRegisters.h"
#include "GeneralServices.h"
#include "CommonReturns.h"
#include "cpuFeatures.h"
#include "cpuHtc.h"
#include "cpuF16PowerMgmt.h"
#include "F16KbPowerMgmt.h"
#include "Gnb.h"
#include "GnbPcie.h"
#include "GnbRegistersKB.h"
#include "GnbRegisterAccKB.h"
#include "GnbHandleLib.h"
#include "Filecode.h"
CODE_GROUP (G2_PEI)
RDATA_GROUP (G2_PEI)
#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBHTC_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
AGESA_STATUS
STATIC
F16KbInitializeHtc (
IN HTC_FAMILY_SERVICES *HtcServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------*/
/**
* Main entry point for initializing the Thermal Control
* safety net feature.
*
* This must be run by all Family 16h Kabini core 0s in the system.
*
* @param[in] HtcServices The current CPU's family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F16KbInitializeHtc (
IN HTC_FAMILY_SERVICES *HtcServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 HtcTempLimit;
NB_CAPS_REGISTER NbCaps;
HTC_REGISTER HtcReg;
CLK_PWR_TIMING_CTRL2_REGISTER Cptc2;
POPUP_PSTATE_REGISTER PopUpPstate;
PCI_ADDR PciAddress;
UINT32 D0F0xBC_xC0107097;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader);
if (NbCaps.HtcCapable == 1) {
// Enable HTC
PciAddress.Address.Register = HTC_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader);
GnbRegisterReadKB (GnbGetHandle (StdHeader), 0x4, 0xC0107097, &D0F0xBC_xC0107097, 0, StdHeader);
HtcReg.HtcTmpLmt = (D0F0xBC_xC0107097 >> 3) & 0x7F;
if (HtcReg.HtcTmpLmt != 0) {
// Enable HTC
HtcReg.HtcEn = 1;
PciAddress.Address.Register = CPTC2_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2, StdHeader);
if (HtcReg.HtcPstateLimit > Cptc2.HwPstateMaxVal) {
// F3xDC[HwPstateMaxVal] = F3x64[HtcPstateLimit]
Cptc2.HwPstateMaxVal = HtcReg.HtcPstateLimit;
LibAmdPciWrite (AccessWidth32, PciAddress, &Cptc2, StdHeader);
// F3xA8[PopDownPstate] = F3xDC[HwPstateMaxVal]
PciAddress.Address.Register = POPUP_PSTATE_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PopUpPstate, StdHeader);
PopUpPstate.PopDownPstate = Cptc2.HwPstateMaxVal;
LibAmdPciWrite (AccessWidth32, PciAddress, &PopUpPstate, StdHeader);
}
if ((PlatformConfig->HtcTemperatureLimit >= 520) && (PlatformConfig->LhtcTemperatureLimit != 0)) {
HtcTempLimit = ((PlatformConfig->HtcTemperatureLimit - 520) / 5);
if (HtcTempLimit < HtcReg.HtcTmpLmt) {
HtcReg.HtcTmpLmt = HtcTempLimit;
}
}
} else {
// Disable HTC
HtcReg.HtcEn = 0;
}
PciAddress.Address.Register = HTC_REG;
IDS_OPTION_HOOK (IDS_HTC_CTRL, &HtcReg, StdHeader);
LibAmdPciWrite (AccessWidth32, PciAddress, &HtcReg, StdHeader);
}
}
return AGESA_SUCCESS;
}
CONST HTC_FAMILY_SERVICES ROMDATA F16KbHtcSupport =
{
0,
(PF_HTC_IS_SUPPORTED) CommonReturnTrue,
F16KbInitializeHtc
};

514
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c
View File

@ -1,514 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD F16Kb Microcode patch.
*
* F16Kb Microcode Patch rev 07000110 for 7001 or equivalent.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x16/KB
* @e \$Revision: 334098 $ @e \$Date: 2018-02-09 14:21:15 -0400 (Fri, 09 Feb 2018) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2018, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "Ids.h"
#include "cpuRegisters.h"
#include "cpuEarlyInit.h"
CODE_GROUP (G3_DXE)
RDATA_GROUP (G3_DXE)
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
// Encrypt Patch code 07000110 for 7001 and equivalent
CONST UINT8 ROMDATA CpuF16KbId7001MicrocodePatch [IDS_PAD_4K] =
{
0x18, 0x20, 0x09, 0x02, 0x10, 0x01, 0x00, 0x07,
0x03, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x01, 0x70, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa,
0x8d, 0xf8, 0xbc, 0xa3, 0x4b, 0xbd, 0x3d, 0x48,
0xdf, 0x1a, 0xc9, 0xae, 0x9f, 0x15, 0xac, 0x70,
0xbb, 0xa6, 0x17, 0x65, 0xed, 0x9c, 0xd1, 0xba,
0x03, 0x77, 0x30, 0x74, 0x56, 0x31, 0x78, 0x9c,
0xcd, 0xe5, 0x2c, 0xac, 0x05, 0xc5, 0xa4, 0x7e,
0x03, 0x17, 0x55, 0xc2, 0x19, 0x65, 0x4d, 0x55,
0x30, 0xde, 0xad, 0x51, 0x79, 0x99, 0xd5, 0x29,
0xbf, 0x74, 0x24, 0xc6, 0xbb, 0x98, 0xd2, 0x1d,
0x15, 0x37, 0xd1, 0x5b, 0xb7, 0xef, 0x76, 0xba,
0x8a, 0xff, 0xa8, 0x01, 0x38, 0xe6, 0x6a, 0x4c,
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0xce, 0x4c, 0xc3, 0xf1, 0xc2, 0x15, 0x24, 0x25,
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0x86, 0x17, 0xed, 0x78, 0x3e, 0x5d, 0xac, 0xd1,
0x13, 0xfa, 0x01, 0x58, 0x35, 0xe9, 0x66, 0x16,
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0xd1, 0x75, 0xbf, 0x2f, 0xb2, 0x9a, 0x7c, 0xd8,
0x84, 0x66, 0x1a, 0x07, 0x00, 0xe0, 0x04, 0xbf,
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0xff, 0xfa, 0xad, 0xb0, 0xd8, 0x41, 0x65, 0xf5,
0xd5, 0x0d, 0x12, 0x15, 0xbf, 0x40, 0x5b, 0xed,
0xeb, 0x81, 0x2a, 0x1f, 0x48, 0x00, 0x5b, 0xf7,
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0xdb, 0x45, 0x30, 0xc5, 0x89, 0x32, 0x98, 0xf9,
0xa7, 0x18, 0x27, 0xf1, 0x0b, 0xc7, 0x6d, 0xeb,
0x7f, 0x39, 0xd2, 0x25, 0x99, 0x6d, 0x3a, 0x1b,
0x24, 0xa4, 0xc5, 0x7c, 0xdf, 0x33, 0x3d, 0x7c,
0x43, 0x40, 0x5b, 0x8d, 0xd1, 0xec, 0x0c, 0xca,
0x76, 0xd9, 0x1a, 0x32, 0xee, 0x45, 0xee, 0xb6,
0x30, 0x21, 0xf8, 0x66, 0xb5, 0xbf, 0xfb, 0x66,
0x13, 0x9c, 0xf0, 0xcf, 0xae, 0xca, 0x54, 0xbc,
0xf1, 0xce, 0x76, 0x57, 0x8d, 0xf5, 0xee, 0x02,
0x14, 0xc0, 0x62, 0x3f, 0xa1, 0xad, 0x9d, 0xbb,
0x83, 0x3d, 0x8f, 0xf2, 0xe9, 0x41, 0x42, 0xca,
0x04, 0xf9, 0xf7, 0x4f, 0xf7, 0xc6, 0x77, 0xf0,
0x0e, 0x8c, 0xea, 0xb6, 0x6c, 0x47, 0xae, 0xd1,
0x1b, 0x2c, 0x89, 0xbf, 0x4b, 0x61, 0xdc, 0x2d,
0x06, 0x6d, 0x79, 0x5c, 0x5e, 0x82, 0xc0, 0x4f,
0x54, 0x5d, 0x68, 0x55, 0x5b, 0x1c, 0x75, 0xb6,
0xcc, 0x4b, 0xb6, 0x3e, 0x2b, 0xec, 0x30, 0xa7,
0x62, 0xc1, 0xdd, 0xd4, 0x52, 0xd8, 0x81, 0xe9,
0xbb, 0xd6, 0x60, 0xc8, 0x51, 0xdb, 0x56, 0xa1,
0x90, 0x42, 0xbe, 0xd3, 0xe3, 0xb5, 0x38, 0x38,
0xad, 0x41, 0x34, 0x2f, 0xf5, 0xdc, 0x13, 0x97,
0x88, 0x24, 0xa2, 0x81, 0xc0, 0x4a, 0x65, 0x51,
0x36, 0x52, 0x81, 0x96, 0x13, 0x55, 0x7a, 0x07,
0x8d, 0x6a, 0xb5, 0xcb, 0xf1, 0x93, 0xf1, 0x2f,
0x7a, 0x00, 0x3c, 0xa9, 0xc4, 0xfb, 0x77, 0xf9,
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0xe2, 0x13, 0xe7, 0x13, 0x93, 0x07, 0x66, 0x04,
0x60, 0x04, 0xd7, 0x19, 0x04, 0x07, 0xda, 0x09,
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0x27, 0x0d, 0x56, 0x06, 0xf4, 0x10, 0x34, 0x1a,
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0x52, 0xa0, 0x06, 0x00, 0x67, 0xd9, 0x3a, 0x00,
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0xe0, 0x1f, 0xe0, 0xac, 0xff, 0xbf, 0x07, 0x00,
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0x17, 0xac, 0x06, 0x00, 0x9d, 0xf1, 0xef, 0x2b,
0xe1, 0x1f, 0xe0, 0xe7, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0x16, 0xac, 0x06, 0x00,
0xf9, 0xff, 0xff, 0x2d, 0xe1, 0x9f, 0xaf, 0xfe,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0x6b, 0xb8, 0x06, 0x00, 0xf5, 0xff, 0xff, 0x28,
0xe1, 0x9f, 0xaf, 0xfe, 0x90, 0xff, 0xff, 0x29,
0xe1, 0x1f, 0xe0, 0xe7, 0xff, 0xbf, 0x07, 0x00,
0xdf, 0xff, 0xff, 0x2e, 0xe0, 0x1f, 0xab, 0xfa,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x9d, 0x4b, 0xe1,
0x50, 0xa0, 0x06, 0x00, 0xd6, 0xff, 0xff, 0x00,
0xe1, 0xcf, 0x43, 0xd7, 0x70, 0x5c, 0x39, 0x00,
0xc0, 0x1f, 0xd0, 0xeb, 0xff, 0xbf, 0x07, 0x00,
0xa3, 0xdb, 0x38, 0x00, 0xc1, 0xdf, 0xd9, 0xeb,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xd7, 0xb8, 0x06, 0x00, 0x00, 0xff, 0xff, 0x3c,
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0xff, 0xdd, 0x7f, 0x2c, 0xe0, 0x0f, 0x6b, 0xff,
0x4b, 0xd8, 0x38, 0x00, 0xa0, 0x1f, 0xc0, 0xe7,
0x91, 0xbb, 0x06, 0x00, 0x2b, 0xce, 0x38, 0x00,
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0xff, 0x81, 0x7f, 0x29, 0xe1, 0x4f, 0x2a, 0xca,
0xff, 0x81, 0x7f, 0x2d, 0xe1, 0x4f, 0x2b, 0xca,
0xfa, 0xb8, 0x06, 0x00, 0xfb, 0xff, 0xff, 0x2d,
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0x78, 0xff, 0xff, 0x29, 0xe1, 0x1f, 0xe0, 0xe7,
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0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00,
0x19, 0x19, 0xfe, 0x00, 0xe1, 0xcf, 0x03, 0xd7,
0xfd, 0xef, 0xff, 0x00, 0xe1, 0x98, 0x8b, 0xfe,
0x4d, 0xa0, 0x06, 0x00, 0x6f, 0xfa, 0xff, 0x2d,
0xe1, 0x1f, 0xe0, 0xe7, 0x19, 0x19, 0xfe, 0x00,
0xe1, 0xd7, 0xc3, 0xd6, 0xff, 0xbf, 0x07, 0x00,
0xad, 0xff, 0xff, 0x00, 0xe1, 0xd7, 0xc3, 0xd6,
0xf2, 0xff, 0xff, 0x00, 0xe1, 0x1b, 0x8b, 0xfe,
0x18, 0xa0, 0x06, 0x00, 0x62, 0x18, 0xfe, 0x00,
0xe1, 0xd7, 0xc3, 0xd6, 0xfe, 0xff, 0xff, 0x2f,
0xe1, 0x1f, 0xeb, 0xfb, 0xff, 0xbf, 0x07, 0x00,
0xef, 0x5f, 0x3f, 0x00, 0xa0, 0x9f, 0xc9, 0xe7,
0x67, 0xfa, 0xff, 0x2f, 0xe1, 0x1f, 0xe0, 0xe7,
0x4a, 0xa0, 0x06, 0x00, 0xff, 0xcd, 0x78, 0x00,
0xa0, 0xdf, 0xcb, 0xe7, 0xff, 0xcd, 0x7f, 0x2a,
0xe0, 0x1f, 0xe0, 0xe7, 0xff, 0xbf, 0x07, 0x00,
0xfc, 0xff, 0xff, 0x2f, 0xe1, 0x1f, 0xe0, 0xe7,
0xff, 0x81, 0x7f, 0x27, 0xe1, 0x1f, 0xe0, 0xe7,
0x3a, 0x20, 0x06, 0x00, 0xf4, 0x5c, 0x39, 0x00,
0xc0, 0x1f, 0xd0, 0xeb, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0x26, 0x40, 0x06, 0x00,
0xfc, 0xff, 0xff, 0x2f, 0xe1, 0x1f, 0xe0, 0xe7,
0xff, 0x81, 0x7f, 0x27, 0xe1, 0x1f, 0xe0, 0xe7,
0x3a, 0x20, 0x06, 0x00, 0xf4, 0x52, 0x39, 0x00,
0xc0, 0x1f, 0xd0, 0xeb, 0xff, 0xfe, 0xff, 0x2f,
0xe1, 0x5f, 0x6a, 0xf1, 0x21, 0x40, 0x06, 0x00,
0x1f, 0xff, 0xff, 0x2e, 0xe1, 0x1f, 0xe0, 0xe7,
0xf5, 0x5f, 0x3f, 0xae, 0xc1, 0x5f, 0xda, 0xeb,
0x1d, 0xa0, 0x06, 0x00, 0x00, 0xff, 0xff, 0x80,
0xe1, 0xdb, 0x8b, 0xfe, 0xa4, 0x0e, 0xfe, 0x00,
0xe1, 0xd7, 0x83, 0xd6, 0xff, 0xbf, 0x07, 0x00,
0x9b, 0x80, 0x38, 0x00, 0x81, 0x1b, 0x80, 0xff,
0xc8, 0x11, 0xfe, 0x00, 0xe1, 0xd7, 0xc3, 0xd6,
0x93, 0x5f, 0x06, 0x00, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00,
0x47, 0xff, 0xff, 0x2d, 0xe1, 0x1f, 0xe0, 0xe7,
0x2c, 0x19, 0xfe, 0x00, 0xe1, 0xd7, 0xc3, 0xd6,
0x03, 0x24, 0x06, 0x00, 0xb6, 0xff, 0xff, 0x00,
0xe1, 0x98, 0x8f, 0xfe, 0xb7, 0xff, 0xff, 0x00,
0xe1, 0xd7, 0xc3, 0xd6, 0xca, 0x45, 0x06, 0x00,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0xbf, 0x07, 0x00, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0xbf, 0x07, 0x00, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
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0xff, 0xbf, 0x07, 0x00, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0xbf, 0x07, 0x00, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00,
0x76, 0x5e, 0x39, 0x00, 0xc0, 0x1f, 0xd0, 0xeb,
0xf5, 0xff, 0xff, 0x2e, 0xe1, 0x1f, 0xe0, 0xac,
0xff, 0xbf, 0x07, 0x00, 0xff, 0xdd, 0x7f, 0x2f,
0xe0, 0xdf, 0xab, 0xff, 0x76, 0x5e, 0x39, 0x00,
0xa0, 0x1f, 0xc0, 0xe7, 0xff, 0xbf, 0x07, 0x00,
0x30, 0x5e, 0x39, 0x00, 0xc0, 0x1f, 0xd0, 0xeb,
0xdf, 0xff, 0xff, 0x2f, 0xe0, 0xdf, 0xab, 0xfa,
0xff, 0xbf, 0x07, 0x00, 0xee, 0xff, 0xff, 0x00,
0xe1, 0xdd, 0x0b, 0xf9, 0xf7, 0xff, 0xff, 0x2f,
0xe1, 0x0f, 0x20, 0xcb, 0x93, 0xbf, 0x06, 0x00,
0x6f, 0xfa, 0xff, 0x2e, 0xe1, 0x1f, 0xe0, 0xe7,
0xff, 0xdf, 0x78, 0x00, 0xa1, 0x9f, 0xcb, 0xe7,
0xff, 0xbf, 0x07, 0x00, 0xff, 0xd1, 0x7f, 0x28,
0xe0, 0x1f, 0x6b, 0xf1, 0x67, 0xd1, 0x3a, 0x00,
0xa0, 0x9f, 0xcb, 0xe7, 0x33, 0xa1, 0x06, 0x00,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0x32, 0xa1, 0x06, 0x00, 0xf8, 0xff, 0xff, 0x00,
0xe1, 0x9d, 0x0b, 0xf9, 0xfe, 0xff, 0xff, 0x00,
0xe1, 0xcf, 0x43, 0xd7, 0xff, 0xbf, 0x07, 0x00,
0x2b, 0xce, 0x38, 0x00, 0xa0, 0x1f, 0xc0, 0xe7,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0x94, 0x5b, 0x02, 0x00, 0x57, 0xdc, 0x38, 0x00,
0xc0, 0xdf, 0xdb, 0xeb, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0x98, 0x5b, 0x06, 0x00,
0xfe, 0xef, 0xff, 0x00, 0xe1, 0x98, 0x8b, 0xfe,
0x47, 0xff, 0xff, 0x2d, 0xe1, 0x1f, 0xe0, 0xe7,
0x2b, 0xb2, 0x06, 0x00, 0x41, 0x19, 0xfe, 0x00,
0xe1, 0xd7, 0xc3, 0xd6, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00,
0xff, 0xff, 0x7f, 0x3f, 0xe1, 0x17, 0xe0, 0xca,
0xff, 0xf9, 0x7f, 0x3c, 0xe1, 0x17, 0xe0, 0xca,
0xff, 0xbf, 0x07, 0x00, 0xff, 0x81, 0x7a, 0x2c,
0xa0, 0x9f, 0xcb, 0xe7, 0xf7, 0xdf, 0x3a, 0x2c,
0xc0, 0x9f, 0xdb, 0xeb, 0xff, 0xbf, 0x07, 0x00,
0xff, 0xff, 0xff, 0x00, 0xe1, 0xdd, 0x0b, 0xf9,
0xfe, 0xff, 0xff, 0x2d, 0xe1, 0x4b, 0x6b, 0xcb,
0xff, 0xbf, 0x07, 0x00, 0xff, 0x5b, 0x7f, 0x00,
0xa0, 0x9f, 0xc9, 0xe7, 0xe7, 0xff, 0xff, 0x26,
0xe0, 0x9f, 0xe9, 0xff, 0xff, 0xbf, 0x07, 0x00,
0xf4, 0xff, 0xff, 0x00, 0xe1, 0xd7, 0xc3, 0xd6,
0x77, 0x5e, 0x3f, 0x00, 0xa0, 0x9f, 0xc9, 0xe7,
0xff, 0xbf, 0x07, 0x00, 0xff, 0xff, 0xbf, 0x2d,
0xe0, 0x1f, 0xe0, 0xe7, 0x0f, 0xff, 0xfe, 0xff,
0xff, 0xff, 0xcf, 0xbf, 0xff, 0xbf, 0x07, 0x00,
0xff, 0xdb, 0x7f, 0x2d, 0xe0, 0xdf, 0x6b, 0xf1,
0xcc, 0xff, 0xff, 0x2b, 0xe0, 0x1f, 0xe0, 0xac,
0xff, 0xbf, 0x07, 0x00, 0xe0, 0xff, 0xff, 0x28,
0xe1, 0x1f, 0xe0, 0xac, 0xff, 0xd7, 0x7f, 0x2d,
0xe0, 0x5f, 0xab, 0xff, 0xff, 0xbf, 0x07, 0x00,
0xf7, 0xdb, 0x3a, 0x2c, 0xa0, 0x9f, 0xcb, 0xe7,
0xff, 0xd1, 0x7a, 0x2c, 0xa0, 0x9f, 0xcb, 0xe7,
0xff, 0xbf, 0x07, 0x00, 0x00, 0x00, 0xfe, 0x2b,
0xe0, 0x1f, 0xe0, 0xe7, 0x00, 0x00, 0xfe, 0x2d,
0xe0, 0x1f, 0xe0, 0xe7, 0x45, 0x9d, 0x06, 0x00,
0x00, 0x00, 0xbf, 0x2a, 0xe0, 0x1f, 0xe0, 0xe7,
0x00, 0x80, 0xff, 0x7f, 0x80, 0x3e, 0xce, 0xbf,
0xff, 0xbf, 0x07, 0x00, 0xff, 0x9f, 0xbf, 0x2a,
0xe0, 0x1f, 0xe0, 0xe7, 0xff, 0x5d, 0xff, 0xff,
0xff, 0xff, 0xcf, 0xbf, 0x45, 0x3d, 0x06, 0x00,
0xb0, 0xff, 0xff, 0x2b, 0xe0, 0x1f, 0xe0, 0xe7,
0xc0, 0xff, 0xff, 0x2a, 0xe0, 0x1f, 0xe0, 0xac,
0x45, 0x3d, 0x06, 0x00, 0x67, 0xfa, 0xff, 0x2f,
0xe1, 0x1f, 0xe0, 0xe7, 0xff, 0xd5, 0x78, 0x00,
0xc0, 0xdf, 0xdb, 0xeb, 0xff, 0xbf, 0x07, 0x00,
0x5f, 0x5e, 0x3f, 0x00, 0xc0, 0x9f, 0xda, 0xeb,
0xdf, 0xfb, 0xff, 0x2c, 0xe1, 0x1f, 0xe0, 0xe7,
0xff, 0xbf, 0x07, 0x00, 0xf7, 0xdf, 0x3a, 0x2c,
0xa0, 0x9f, 0xcb, 0xe7, 0xff, 0xd1, 0x7a, 0x2c,
0xa0, 0x9f, 0xcb, 0xe7, 0xff, 0xbf, 0x07, 0x00,
0xf7, 0x5f, 0x3f, 0x00, 0xc0, 0x9f, 0xda, 0xeb,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0x43, 0x5a, 0x06, 0x00, 0xcf, 0x53, 0x39, 0x00,
0xc0, 0xdf, 0xdb, 0xeb, 0xfe, 0xff, 0xff, 0x27,
0xe1, 0xdf, 0xe9, 0xfa, 0xff, 0xbf, 0x07, 0x00,
0x89, 0xff, 0xff, 0xc0, 0xe1, 0x5b, 0x8a, 0xfe,
0xf2, 0xff, 0xff, 0x00, 0xe1, 0xd7, 0x83, 0xd6,
0xff, 0xbf, 0x07, 0x00, 0xe9, 0xff, 0xff, 0x00,
0xe1, 0x5d, 0x0a, 0xf9, 0xf3, 0xff, 0xff, 0x00,
0xe1, 0xcf, 0x03, 0xd7, 0xff, 0xbf, 0x07, 0x00,
0xff, 0xff, 0xbf, 0x29, 0xe0, 0x5f, 0x6a, 0xf1,
0xff, 0xff, 0xff, 0xff, 0xbf, 0xff, 0xcf, 0xbf,
0xff, 0xbf, 0x07, 0x00, 0xfe, 0xff, 0xff, 0x27,
0xe1, 0xdf, 0xa9, 0xff, 0xcb, 0x5b, 0x39, 0x00,
0xc0, 0xdf, 0xdb, 0xeb, 0xff, 0xbf, 0x07, 0x00,
0xcf, 0x53, 0x39, 0x00, 0xa0, 0xdf, 0xcb, 0xe7,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0xbf, 0x03, 0x00, 0xcb, 0x59, 0x39, 0x00,
0xc0, 0xdf, 0xdb, 0xeb, 0xff, 0xdb, 0x7f, 0x00,
0xe0, 0x1d, 0x8b, 0xfe, 0xff, 0xbf, 0x03, 0x00,
0xf8, 0xff, 0xff, 0x00, 0xe1, 0xcf, 0x03, 0xd7,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1b, 0x8b, 0xfe,
0xff, 0xbf, 0x07, 0x00, 0xf9, 0xff, 0xff, 0x00,
0xe1, 0xd7, 0x83, 0xd6, 0xdf, 0xff, 0xff, 0x2d,
0xe0, 0x5f, 0xab, 0xfa, 0xff, 0xbf, 0x07, 0x00,
0xdf, 0xff, 0xff, 0x2c, 0xe0, 0x1f, 0xab, 0xfa,
0xff, 0xd9, 0x7f, 0x00, 0xe1, 0x5b, 0x8b, 0xfe,
0xff, 0xbf, 0x07, 0x00, 0xfb, 0xff, 0xff, 0x00,
0xe1, 0xd7, 0x83, 0xd6, 0xfe, 0xff, 0xff, 0xac,
0xe1, 0x1b, 0xeb, 0xff, 0xff, 0xbf, 0x07, 0x00,
0xdf, 0xff, 0xff, 0x2c, 0xe0, 0x1f, 0xeb, 0xfa,
0x00, 0x00, 0xfe, 0x2c, 0xe0, 0x17, 0xeb, 0xca,
0xff, 0xbf, 0x07, 0x00, 0xcb, 0x59, 0x39, 0x00,
0xa0, 0xdf, 0xcb, 0xe7, 0xfd, 0xff, 0xff, 0x00,
0xe1, 0xd7, 0x83, 0xd6, 0xff, 0xbf, 0x07, 0x00,
0xe9, 0xff, 0xff, 0x2d, 0xe1, 0x1f, 0xe0, 0xac,
0xff, 0xdb, 0x7f, 0x29, 0xe0, 0x5f, 0xaa, 0xff,
0x35, 0xa0, 0x06, 0x00, 0xcf, 0x53, 0x39, 0x00,
0xa0, 0xdf, 0xcb, 0xe7, 0xff, 0xdb, 0x7f, 0x29,
0xe0, 0x5f, 0x6a, 0xf1, 0x2b, 0xa0, 0x06, 0x00,
0xfe, 0xff, 0xff, 0x2f, 0xe1, 0xdd, 0xab, 0xfe,
0x7e, 0x11, 0xfe, 0x00, 0xe1, 0xcf, 0x43, 0xd7,
0x3a, 0x40, 0x06, 0x00, 0xfe, 0xff, 0xff, 0x27,
0xe1, 0xdd, 0xe9, 0xfa, 0xcf, 0x59, 0x39, 0x00,
0xc0, 0xdf, 0xdb, 0xeb, 0xff, 0xbf, 0x07, 0x00,
0xff, 0xff, 0xbf, 0x2c, 0xe0, 0x0f, 0x6b, 0xdf,
0xff, 0xff, 0xff, 0xff, 0xbf, 0xff, 0xcf, 0xbf,
0xff, 0xbf, 0x07, 0x00, 0xcf, 0x59, 0x39, 0x00,
0xa0, 0xdf, 0xcb, 0xe7, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0x2a, 0xa0, 0x06, 0x00,
0xfe, 0xff, 0xff, 0x2f, 0xe1, 0xdd, 0xab, 0xfe,
0x82, 0x11, 0xfe, 0x00, 0xe1, 0xcf, 0x43, 0xd7,
0xff, 0xbf, 0x07, 0x00, 0xff, 0xfe, 0xff, 0x2f,
0xe1, 0x9f, 0x6b, 0xf1, 0xf4, 0x5e, 0x39, 0x00,
0xa0, 0x1f, 0xc0, 0xe7, 0xfd, 0xbf, 0x07, 0x00,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0x9b,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0xbf, 0x03, 0x00, 0xf4, 0x5c, 0x39, 0x00,
0xa0, 0x1f, 0xc0, 0xe7, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xfd, 0xbf, 0x07, 0x00,
0xfc, 0xff, 0xff, 0x2f, 0xe1, 0x1f, 0xe0, 0xe7,
0xe3, 0xff, 0xff, 0x27, 0xe1, 0xdf, 0xe9, 0xfa,
0x2a, 0x20, 0x06, 0x00, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xc5, 0x43, 0x06, 0x00,
0xf4, 0x5e, 0x39, 0x00, 0xa0, 0x1f, 0xc0, 0xe7,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0x9b,
0xff, 0xbf, 0x03, 0x00, 0xf4, 0x52, 0x39, 0x00,
0xa0, 0x1f, 0xc0, 0xe7, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xfd, 0xbf, 0x07, 0x00,
0xfc, 0xff, 0xff, 0x2f, 0xe1, 0x1f, 0xe0, 0xe7,
0xe3, 0xff, 0xff, 0x27, 0xe1, 0xdf, 0xe9, 0xfa,
0x2a, 0x20, 0x06, 0x00, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xd5, 0x52, 0x06, 0x00,
0xfd, 0x5f, 0x3f, 0x2e, 0xc0, 0x5f, 0xda, 0xeb,
0xfe, 0xff, 0xff, 0x00, 0xe0, 0xdb, 0xcb, 0xff,
0xff, 0xbf, 0x07, 0x00, 0xec, 0x0e, 0xfe, 0x00,
0xe1, 0xd7, 0x83, 0xd6, 0xf7, 0xff, 0xff, 0x2e,
0xe1, 0x9d, 0xab, 0xfe, 0x1d, 0xa0, 0x06, 0x00,
0x13, 0xff, 0xff, 0x2a, 0xe1, 0x1f, 0xe0, 0xe7,
0x05, 0x0f, 0xfe, 0x00, 0xe1, 0xcf, 0x43, 0xd7,
0xff, 0xbf, 0x07, 0x00, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x5b, 0x8b, 0xfe, 0x6f, 0xfa, 0xff, 0x2e,
0xe1, 0x1f, 0xe0, 0xe7, 0x4b, 0xa0, 0x06, 0x00,
0xff, 0xf9, 0x78, 0x00, 0xc1, 0x9f, 0xdb, 0xeb,
0xfd, 0xff, 0x38, 0x00, 0xc1, 0x9f, 0xdb, 0xeb,
0xd7, 0xb8, 0x06, 0x00, 0xee, 0xff, 0xff, 0x00,
0xe1, 0xda, 0x8b, 0xfe, 0xff, 0xef, 0xff, 0x3c,
0xe1, 0x17, 0xe0, 0xca, 0xc8, 0x58, 0x06, 0x00,
0x9b, 0x80, 0x38, 0x00, 0xc1, 0x1d, 0xc0, 0xf3,
0xff, 0x81, 0x7f, 0x00, 0xe0, 0x0c, 0x0b, 0xf9,
0xff, 0xbf, 0x07, 0x00, 0x15, 0x12, 0xfe, 0x00,
0xe1, 0xd7, 0x83, 0xd6, 0xff, 0xff, 0xff, 0x00,
0xe1, 0xcf, 0x43, 0xd7, 0x93, 0x5f, 0x06, 0x00,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xc3, 0x21, 0x06, 0x00, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0x9b, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xfd, 0xbf, 0x07, 0x00,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0x93, 0x5f, 0x06, 0x00, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0xbf, 0x07, 0x00, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0xbf, 0x07, 0x00, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0xbf, 0x07, 0x00, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0xbf, 0x07, 0x00, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0xbf, 0x07, 0x00, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0xbf, 0x07, 0x00, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0xbf, 0x07, 0x00, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0xbf, 0x07, 0x00, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0x81, 0x7f, 0x00, 0xe1, 0x1f, 0xc0, 0xbf,
0xff, 0xbf, 0x07, 0x00, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0x81, 0x7f, 0x00,
0xe1, 0x1f, 0xc0, 0xbf, 0xff, 0xbf, 0x07, 0x00,
0x18, 0xa0, 0xba, 0x3a, 0x3f, 0x95, 0x1c, 0x69,
0x42, 0xac, 0xed, 0xda, 0x47, 0xb4, 0xfd, 0xc8,
0x19, 0xf5, 0x85, 0x69, 0x6a, 0x82, 0x3b, 0xce,
0x6e, 0x7d, 0x01, 0x4e, 0x1e, 0x5b, 0x92, 0x6c,
0xed, 0x73, 0x65, 0xe1, 0xdf, 0xfb, 0x8e, 0x8b,
0x5d, 0x35, 0x65, 0x6f, 0xe8, 0x1a, 0xdf, 0xc7,
0xeb, 0xd3, 0xd6, 0x0c, 0xee, 0xfe, 0x34, 0x1f,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00
};
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/

175
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c
View File

@ -1,175 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Initialize the Family 16h Kabini specific way of running early initialization.
*
* Returns the table of initialization steps to perform at
* AmdInitEarly.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x16/KB
* @e \$Revision: 86705 $ @e \$Date: 2013-01-24 17:34:21 -0600 (Thu, 24 Jan 2013) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
#include "cpuEarlyInit.h"
#include "cpuFeatures.h"
CODE_GROUP (G2_PEI)
RDATA_GROUP (G2_PEI)
#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBINITEARLYTABLE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
extern CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F16KbEarlyInitBeforeApLaunchOnCoreTable[];
extern CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F16KbEarlyInitAfterApLaunchOnCoreTable[];
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
GetF16KbEarlyInitBeforeApLaunchOnCoreTable (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
GetF16KbEarlyInitAfterApLaunchOnCoreTable (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
F16KbLoadMicrocodePatchAtEarly (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*------------------------------------------------------------------------------------*/
/**
* Initializer routine that may be invoked at AmdCpuEarly (Before AP launch) to return the steps that a
* processor that uses the standard initialization steps should take.
*
* @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}.
*
* @param[in] FamilyServices The current Family Specific Services.
* @param[out] Table Table of appropriate init steps for the executing core.
* @param[in] EarlyParams Service Interface structure to initialize.
* @param[in] StdHeader Opaque handle to standard config header.
*
*/
VOID
GetF16KbEarlyInitBeforeApLaunchOnCoreTable (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
*Table = F16KbEarlyInitBeforeApLaunchOnCoreTable;
}
/*------------------------------------------------------------------------------------*/
/**
* Initializer routine that may be invoked at AmdCpuEarly (After AP launch) to return the steps that a
* processor that uses the standard initialization steps should take.
*
* @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}.
*
* @param[in] FamilyServices The current Family Specific Services.
* @param[out] Table Table of appropriate init steps for the executing core.
* @param[in] EarlyParams Service Interface structure to initialize.
* @param[in] StdHeader Opaque handle to standard config header.
*
*/
VOID
GetF16KbEarlyInitAfterApLaunchOnCoreTable (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
*Table = F16KbEarlyInitAfterApLaunchOnCoreTable;
}
/*---------------------------------------------------------------------------------------*/
/**
* Update microcode patch in current processor for Family16h KB.
*
* This function acts as a wrapper for calling the LoadMicrocodePatch
* routine at AmdInitEarly.
*
* @param[in] FamilyServices The current Family Specific Services.
* @param[in] EarlyParams Service parameters.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F16KbLoadMicrocodePatchAtEarly (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
if (!IsFeatureEnabled (C6Cstate, &EarlyParams->PlatformConfig, StdHeader)) {
AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader);
LoadMicrocodePatch (StdHeader);
}
}

371
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbIoCstate.c
View File

@ -1,371 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_16 Kabini IO C-state feature support functions.
*
* Provides the functions necessary to initialize the IO C-state feature.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x16/KB
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuFeatures.h"
#include "cpuIoCstate.h"
#include "cpuF16PowerMgmt.h"
#include "F16KbPowerMgmt.h"
#include "cpuLateInit.h"
#include "cpuRegisters.h"
#include "cpuServices.h"
#include "cpuApicUtilities.h"
#include "cpuFamilyTranslation.h"
#include "CommonReturns.h"
#include "Filecode.h"
CODE_GROUP (G3_DXE)
RDATA_GROUP (G3_DXE)
#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBIOCSTATE_FILECODE
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
STATIC
F16KbInitializeIoCstateOnCore (
IN VOID *CstateBaseMsr,
IN AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
F16KbIsCsdObjGenerated (
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable;
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Enable IO Cstate on a family 16h Kabini CPU.
* Implement BIOS Requirements for Initialization of C-states
*
* @param[in] IoCstateServices Pointer to this CPU's IO Cstate family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @return AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F16KbInitializeIoCstate (
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 LocalMsrRegister;
AP_TASK TaskPtr;
PCI_ADDR PciAddress;
CSTATE_POLICY_CTRL1_REGISTER CstatePolicyCtrl1;
if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
// Initialize F4x128
// bit[4:2] HaltCstateIndex = 0
PciAddress.AddressValue = CSTATE_POLICY_CTRL1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader);
CstatePolicyCtrl1.HaltCstateIndex = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader);
// Initialize MSRC001_0073[CstateAddr] on each core to a region of
// the IO address map with 8 consecutive available addresses.
LocalMsrRegister = 0;
IDS_HDT_CONSOLE (CPU_TRACE, " Init IO C-state Base at 0x%x\n", PlatformConfig->CStateIoBaseAddress);
((CSTATE_ADDRESS_MSR *) &LocalMsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
TaskPtr.FuncAddress.PfApTaskI = F16KbInitializeIoCstateOnCore;
TaskPtr.DataTransfer.DataSizeInDwords = 2;
TaskPtr.DataTransfer.DataPtr = &LocalMsrRegister;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
}
return AGESA_SUCCESS;
}
/*---------------------------------------------------------------------------------------*/
/**
* Enable CState on a family 16h Kabini core.
*
* @param[in] CstateBaseMsr MSR value to write to C001_0073 as determined by core 0.
* @param[in] StdHeader Config Handle for library, services.
*
*/
VOID
STATIC
F16KbInitializeIoCstateOnCore (
IN VOID *CstateBaseMsr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
// Initialize MSRC001_0073[CstateAddr] on each core
LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
* Returns the size of CST object
*
* @param[in] IoCstateServices IO Cstate services.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data
* @param[in] StdHeader Config Handle for library, services.
*
* @retval CstObjSize Size of CST Object
*
*/
UINT32
STATIC
F16KbGetAcpiCstObj (
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
BOOLEAN GenerateCsdObj;
UINT32 CStateAcpiObjSize;
IO_CSTATE_FAMILY_SERVICES *FamilyServices;
ACPI_CST_GET_INPUT CstGetInput;
CstGetInput.IoCstateServices = IoCstateServices;
CstGetInput.PlatformConfig = PlatformConfig;
CstGetInput.CStateAcpiObjSizePtr = &CStateAcpiObjSize;
IDS_SKIP_HOOK (IDS_CST_SIZE, &CstGetInput, StdHeader) {
CStateAcpiObjSize = CST_HEADER_SIZE + CST_BODY_SIZE;
// If CSD Object is generated, add the size of CSD Object to the total size of
// CState ACPI Object size
GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL);
GenerateCsdObj = FamilyServices->IsCsdObjGenerated (FamilyServices, StdHeader);
if (GenerateCsdObj) {
CStateAcpiObjSize += CSD_HEADER_SIZE + CSD_BODY_SIZE;
}
}
return CStateAcpiObjSize;
}
/*---------------------------------------------------------------------------------------*/
/**
* Routine to generate the C-State ACPI objects
*
* @param[in] IoCstateServices IO Cstate services.
* @param[in] LocalApicId Local Apic Id for each core.
* @param[in, out] **PstateAcpiBufferPtr Pointer to the Acpi Buffer Pointer.
* @param[in] StdHeader Config Handle for library, services.
*
*/
VOID
STATIC
F16KbCreateAcpiCstObj (
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
IN UINT8 LocalApicId,
IN OUT VOID **PstateAcpiBufferPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrData;
BOOLEAN GenerateCsdObj;
CST_HEADER_STRUCT *CstHeaderPtr;
CST_BODY_STRUCT *CstBodyPtr;
CSD_HEADER_STRUCT *CsdHeaderPtr;
CSD_BODY_STRUCT *CsdBodyPtr;
IO_CSTATE_FAMILY_SERVICES *FamilyServices;
ACPI_CST_CREATE_INPUT CstInput;
CstInput.IoCstateServices = IoCstateServices;
CstInput.LocalApicId = LocalApicId;
CstInput.PstateAcpiBufferPtr = PstateAcpiBufferPtr;
IDS_SKIP_HOOK (IDS_CST_CREATE, &CstInput, StdHeader) {
// Read from MSR C0010073 to obtain CstateAddr
LibAmdMsrRead (MSR_CSTATE_ADDRESS, &MsrData, StdHeader);
// Typecast the pointer
CstHeaderPtr = (CST_HEADER_STRUCT *) *PstateAcpiBufferPtr;
// Set CST Header
CstHeaderPtr->NameOpcode = NAME_OPCODE;
CstHeaderPtr->CstName_a__ = CST_NAME__;
CstHeaderPtr->CstName_a_C = CST_NAME_C;
CstHeaderPtr->CstName_a_S = CST_NAME_S;
CstHeaderPtr->CstName_a_T = CST_NAME_T;
// Typecast the pointer
CstHeaderPtr++;
CstBodyPtr = (CST_BODY_STRUCT *) CstHeaderPtr;
// Set CST Body
CstBodyPtr->PkgOpcode = PACKAGE_OPCODE;
CstBodyPtr->PkgLength = CST_LENGTH;
CstBodyPtr->PkgElements = CST_NUM_OF_ELEMENTS;
CstBodyPtr->BytePrefix = BYTE_PREFIX_OPCODE;
CstBodyPtr->Count = CST_COUNT;
CstBodyPtr->PkgOpcode2 = PACKAGE_OPCODE;
CstBodyPtr->PkgLength2 = CST_PKG_LENGTH;
CstBodyPtr->PkgElements2 = CST_PKG_ELEMENTS;
CstBodyPtr->BufferOpcode = BUFFER_OPCODE;
CstBodyPtr->BufferLength = CST_SUBPKG_LENGTH;
CstBodyPtr->BufferElements = CST_SUBPKG_ELEMENTS;
CstBodyPtr->BufferOpcode2 = BUFFER_OPCODE;
CstBodyPtr->GdrOpcode = GENERIC_REG_DESCRIPTION;
CstBodyPtr->GdrLength = CST_GDR_LENGTH;
CstBodyPtr->AddrSpaceId = GDR_ASI_SYSTEM_IO;
CstBodyPtr->RegBitWidth = 0x08;
CstBodyPtr->RegBitOffset = 0x00;
CstBodyPtr->AddressSize = GDR_ASZ_BYTE_ACCESS;
CstBodyPtr->RegisterAddr = ((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr + 1;
CstBodyPtr->EndTag = 0x0079;
CstBodyPtr->BytePrefix2 = BYTE_PREFIX_OPCODE;
CstBodyPtr->Type = CST_C2_TYPE;
CstBodyPtr->WordPrefix = WORD_PREFIX_OPCODE;
CstBodyPtr->Latency = 400;
CstBodyPtr->DWordPrefix = DWORD_PREFIX_OPCODE;
CstBodyPtr->Power = 0;
CstBodyPtr++;
//Update the pointer
*PstateAcpiBufferPtr = CstBodyPtr;
// Check whether CSD object should be generated
GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL);
GenerateCsdObj = FamilyServices->IsCsdObjGenerated (FamilyServices, StdHeader);
if (GenerateCsdObj) {
CsdHeaderPtr = (CSD_HEADER_STRUCT *) *PstateAcpiBufferPtr;
// Set CSD Header
CsdHeaderPtr->NameOpcode = NAME_OPCODE;
CsdHeaderPtr->CsdName_a__ = CST_NAME__;
CsdHeaderPtr->CsdName_a_C = CST_NAME_C;
CsdHeaderPtr->CsdName_a_S = CST_NAME_S;
CsdHeaderPtr->CsdName_a_D = CSD_NAME_D;
CsdHeaderPtr++;
CsdBodyPtr = (CSD_BODY_STRUCT *) CsdHeaderPtr;
// Set CSD Body
CsdBodyPtr->PkgOpcode = PACKAGE_OPCODE;
CsdBodyPtr->PkgLength = CSD_BODY_SIZE - 1;
CsdBodyPtr->PkgElements = 1;
CsdBodyPtr->PkgOpcode2 = PACKAGE_OPCODE;
CsdBodyPtr->PkgLength2 = CSD_BODY_SIZE - 4; // CSD_BODY_SIZE - Package() - Package Opcode
CsdBodyPtr->PkgElements2 = 6;
CsdBodyPtr->BytePrefix = BYTE_PREFIX_OPCODE;
CsdBodyPtr->NumEntries = 6;
CsdBodyPtr->BytePrefix2 = BYTE_PREFIX_OPCODE;
CsdBodyPtr->Revision = 0;
CsdBodyPtr->DWordPrefix = DWORD_PREFIX_OPCODE;
CsdBodyPtr->Domain = (LocalApicId & 0xFE) >> 1;
CsdBodyPtr->DWordPrefix2 = DWORD_PREFIX_OPCODE;
CsdBodyPtr->CoordType = CSD_COORD_TYPE_HW_ALL;
CsdBodyPtr->DWordPrefix3 = DWORD_PREFIX_OPCODE;
CsdBodyPtr->NumProcessors = 0x2;
CsdBodyPtr->DWordPrefix4 = DWORD_PREFIX_OPCODE;
CsdBodyPtr->Index = 0x0;
CsdBodyPtr++;
// Update the pointer
*PstateAcpiBufferPtr = CsdBodyPtr;
}
}
}
/*---------------------------------------------------------------------------------------*/
/**
* Routine to check whether CSD object should be created.
*
* @param[in] IoCstateServices IO Cstate services.
* @param[in] StdHeader Config Handle for library, services.
*
* @retval TRUE CSD Object should be created.
* @retval FALSE CSD Object should not be created.
*
*/
BOOLEAN
F16KbIsCsdObjGenerated (
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
// CSD Object should only be created when there are two cores per compute unit
if (GetComputeUnitMapping (StdHeader) == EvenCoresMapping) {
return TRUE;
}
return FALSE;
}
CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F16KbIoCstateSupport =
{
0,
(PF_IO_CSTATE_IS_SUPPORTED) CommonReturnTrue,
F16KbInitializeIoCstate,
F16KbGetAcpiCstObj,
F16KbCreateAcpiCstObj,
F16KbIsCsdObjGenerated
};

107
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbLogicalIdTables.c
View File

@ -1,107 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_16 Kabini Logical ID Table
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x16/KB
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Filecode.h"
CODE_GROUP (G3_DXE)
RDATA_GROUP (G3_DXE)
#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBLOGICALIDTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
GetF16KbLogicalIdAndRev (
OUT CONST CPU_LOGICAL_ID_XLAT **KbIdPtr,
OUT UINT8 *NumberOfElements,
OUT UINT64 *LogicalFamily,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF16KbLogicalIdAndRevArray[] =
{
{
0x7001,
AMD_F16_KB_A1
},
{
0x7000,
AMD_F16_KB_A0
},
};
VOID
GetF16KbLogicalIdAndRev (
OUT CONST CPU_LOGICAL_ID_XLAT **KbIdPtr,
OUT UINT8 *NumberOfElements,
OUT UINT64 *LogicalFamily,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
*NumberOfElements = (sizeof (CpuF16KbLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
*KbIdPtr = CpuF16KbLogicalIdAndRevArray;
*LogicalFamily = AMD_FAMILY_16_KB;
}

111
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatchTables.c
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@ -1,111 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_16 Kabini microcode patches
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x16/KB
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuEarlyInit.h"
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
CODE_GROUP (G3_DXE)
RDATA_GROUP (G3_DXE)
#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBMICROCODEPATCHTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
extern CONST UINT8 ROMDATA *CpuF16KbMicroCodePatchArray[];
extern CONST UINT8 ROMDATA CpuF16KbNumberOfMicrocodePatches;
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
GetF16KbMicroCodePatchesStruct (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **KbUcodePtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Returns a table containing the appropriate microcode patches.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] KbUcodePtr Points to the first entry in the table.
* @param[out] NumberOfElements Number of valid entries in the table.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF16KbMicroCodePatchesStruct (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **KbUcodePtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
*NumberOfElements = CpuF16KbNumberOfMicrocodePatches;
*KbUcodePtr = &CpuF16KbMicroCodePatchArray[0];
}

264
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMsrTables.c
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@ -1,264 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_16 KB MSR tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x16/KB
* @e \$Revision: 87267 $ @e \$Date: 2013-01-31 09:34:00 -0600 (Thu, 31 Jan 2013) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuRegisters.h"
#include "F16KbPowerMgmt.h"
#include "Table.h"
#include "Filecode.h"
CODE_GROUP (G3_DXE)
RDATA_GROUP (G3_DXE)
#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBMSRTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
NbMcaLock (
IN UINT32 Data,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
// M S R T a b l e s
// ----------------------
STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F16KbMsrRegisters[] =
{
// MSR_TOM2 (0xC001001D)
// bits[39:23] TOP_MEM2 = 0x0
{
MsrRegister,
{
AMD_FAMILY_16, // CpuFamily
AMD_F16_KB_ALL // CpuRevision
},
{AMD_PF_ALL}, // PlatformFeatures
{{
MSR_TOM2, // Address
0x0000000000000000, // RegData
0xFFFFFFFFFF800000, // RegMask
}}
},
// MSR_SYS_CFG (0xC0010010)
// bits[21] MtrrTom2En = 0x1
{
MsrRegister,
{
AMD_FAMILY_16, // CpuFamily
AMD_F16_KB_ALL // CpuRevision
},
{AMD_PF_ALL}, // PlatformFeatures
{{
MSR_SYS_CFG, // Address
(1 << 21), // RegData
(1 << 21), // RegMask
}}
},
// MC4_MISC_1 (0xC0000408)
// Clear to 0
{
MsrRegister,
{
AMD_FAMILY_16, // CpuFamily
AMD_F16_KB_ALL // CpuRevision
},
{AMD_PF_ALL}, // PlatformFeatures
{{
0xC0000408, // Address
0x0000000000000000, // RegData
0xFF0FFFFFFFFFFFFF, // RegMask
}}
},
// MSR_LS_CFG (C0011020)
// bits[26] = 0x1
{
MsrRegister,
{
AMD_FAMILY_16, // CpuFamily
AMD_F16_KB_ALL // CpuRevision
},
{AMD_PF_ALL}, // PlatformFeatures
{{
MSR_LS_CFG, // Address
0x0000000004000000, // RegData
0x0000000004000000, // RegMask
}}
},
// MSR_IC_CFG (C0011021)
// bits[26] DIS_WIDEREAD_PWR_SAVE = 0x1
{
MsrRegister,
{
AMD_FAMILY_16, // CpuFamily
AMD_F16_KB_ALL // CpuRevision
},
{AMD_PF_ALL}, // PlatformFeatures
{{
MSR_IC_CFG, // Address
0x0000000004000000, // RegData
0x0000000004000000, // RegMask
}}
},
// Processor Feedback Constants 0 (C0011090)
// bits[15:8] RefCountScale = 0x64
// bits[7:0] ActualCountScale = 0xA5
{
MsrRegister,
{
AMD_FAMILY_16, // CpuFamily
AMD_F16_KB_ALL // CpuRevision
},
{AMD_PF_ALL}, // PlatformFeatures
{{
0xC0011090, // Address
0x00000000000064A5, // RegData
0x000000000000FFFF, // RegMask
}}
},
// MSR_L2I_CFG (C00110A0)
// bits[56:45] L2ScrubberInterval = 0x100
// bits[44] PbDisObeysThrottleNb = 0x1
// bits[43:40] ThrottleNbInterface = 0x0
// bits[19] McaToMstCoreEn = 0x1
{
MsrRegister,
{
AMD_FAMILY_16, // CpuFamily
AMD_F16_KB_ALL // CpuRevision
},
{AMD_PF_ALL}, // PlatformFeatures
{{
MSR_L2I_CFG, // Address
0x0020100000080000, // RegData
0x01FFFF0000080000, // RegMask
}}
},
};
// MSR with Special Programming Requirements Table
// ----------------------
STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F16KbMsrWorkarounds[] =
{
// MSR_0000_0413
{
FamSpecificWorkaround,
{
AMD_FAMILY_16, // CpuFamily
AMD_F16_KB_ALL // CpuRevision
},
{AMD_PF_ALL}, // PlatformFeatures
{{
NbMcaLock, // Function call
0x00000000, // Data
}}
},
};
CONST REGISTER_TABLE ROMDATA F16KbMsrRegisterTable = {
AllCores,
PERFORM_TP_AFTER_AP_LAUNCH,
(sizeof (F16KbMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
(TABLE_ENTRY_FIELDS *) &F16KbMsrRegisters,
};
CONST REGISTER_TABLE ROMDATA F16KbMsrWorkaroundTable = {
AllCores,
PERFORM_TP_AFTER_AP_LAUNCH,
(sizeof (F16KbMsrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)),
(TABLE_ENTRY_FIELDS *) F16KbMsrWorkarounds,
};
/*---------------------------------------------------------------------------------------*/
/**
* MSR special programming requirements for MSR_0000_0413
*
*
* @param[in] Data The table data value, for example to indicate which CPU and Platform types matched.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
NbMcaLock (
IN UINT32 Data,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
MC4_MISC0_MSR Mc4Misc0;
LibAmdMsrRead (MSR_MC4_MISC, (UINT64 *) &Mc4Misc0, StdHeader);
if (Mc4Misc0.IntType == 0x2) {
Mc4Misc0.Locked = 1;
} else {
Mc4Misc0.Locked = 0;
}
LibAmdMsrWrite (MSR_MC4_MISC, (UINT64 *) &Mc4Misc0, StdHeader);
return;
}

365
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbNbAfterReset.c
View File

@ -1,365 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_16 Kabini after warm reset sequence for NB P-states
*
* Performs the "NB COF and VID Transition Sequence After Warm Reset"
* as described in the BKDG.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x16/KB
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuF16PowerMgmt.h"
#include "F16KbPowerMgmt.h"
#include "cpuRegisters.h"
#include "cpuApicUtilities.h"
#include "cpuFamilyTranslation.h"
#include "GeneralServices.h"
#include "cpuServices.h"
#include "F16KbNbAfterReset.h"
#include "Gnb.h"
#include "GnbPcie.h"
#include "GnbHandleLib.h"
#include "GnbRegisterAccKB.h"
#include "GnbRegistersKB.h"
#include "Filecode.h"
CODE_GROUP (G3_DXE)
RDATA_GROUP (G3_DXE)
#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBNBAFTERRESET_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
STATIC
F16KbPmNbAfterResetOnCore (
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
STATIC
TransitionToNbLow (
IN PCI_ADDR PciAddress,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
STATIC
TransitionToNbHigh (
IN PCI_ADDR PciAddress,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
STATIC
WaitForNbTransitionToComplete (
IN PCI_ADDR PciAddress,
IN UINT32 PstateIndex,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Family 16h Kabini core 0 entry point for performing the necessary steps after
* a warm reset has occurred.
*
* The steps are as follows:
*
* 1. Temp1=D18F5x170[SwNbPstateLoDis].
* 2. Temp2=D18F5x170[NbPstateDisOnP0].
* 3. Temp3=D18F5x170[NbPstateThreshold].
* 4. Temp4=D18F5x170[NbPstateGnbSlowDis].
* 5. If MSRC001_0070[NbPstate]=0, go to step 6. If MSRC001_0070[NbPstate]=1, go to step 11.
* 6. Write 1 to D18F5x170[NbPstateGnbSlowDis].
* 7. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
* 8. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, CurNb-
* Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
* 9. Set D18F5x170[SwNbPstateLoDis]=1.
* 10. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, CurNb-
* Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. Go to step 15.
* 11. Write 1 to D18F5x170[SwNbPstateLoDis].
* 12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, CurNb-
* Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi].
* 13. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
* 14. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, CurNb-
* Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
* 15. Set D18F5x170[SwNbPstateLoDis]=Temp1, D18F5x170[NbPstateDisOnP0]=Temp2, D18F5x170[NbP-
* stateThreshold]=Temp3, and D18F5x170[NbPstateGnbSlowDis]=Temp4.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParamsPtr Service parameters
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F16KbPmNbAfterReset (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Socket;
UINT32 Module;
UINT32 Core;
UINT32 TaskedCore;
UINT32 Ignored;
AP_TASK TaskPtr;
AGESA_STATUS IgnoredSts;
IDS_HDT_CONSOLE (CPU_TRACE, " F16KbPmNbAfterReset\n");
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
ASSERT (Core == 0);
// Launch one core per node.
TaskPtr.FuncAddress.PfApTask = F16KbPmNbAfterResetOnCore;
TaskPtr.DataTransfer.DataSizeInDwords = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetGivenModuleCoreRange (Socket, Module, &TaskedCore, &Ignored, StdHeader)) {
if (TaskedCore != 0) {
ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) TaskedCore, &TaskPtr, StdHeader);
}
}
}
ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr);
}
/*---------------------------------------------------------------------------------------
* L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Support routine for F16KbPmNbAfterReset to perform MSR initialization on one
* core of each die in a family 16h socket.
*
* This function implements steps 1 - 15 on each core.
*
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
F16KbPmNbAfterResetOnCore (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 NbPsCtrlOnEntry;
UINT32 NbPsCtrlOnExit;
UINT64 LocalMsrRegister;
PCI_ADDR PciAddress;
IDS_HDT_CONSOLE (CPU_TRACE, " F16KbPmNbAfterResetOnCore\n");
// 1. Temp1 = D18F5x170[SwNbPstateLoDis].
// 2. Temp2 = D18F5x170[NbPstateDisOnP0].
// 3. Temp3 = D18F5x170[NbPstateThreshold].
// 4. Temp4 = D18F5x170[NbPstateGnbSlowDis].
PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnEntry, StdHeader);
// Check if NB P-states were disabled, and if so, prevent any changes from occurring.
if (((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->SwNbPstateLoDis == 0) {
// 5. If MSRC001_0070[NbPstate] = 1, go to step 11
LibAmdMsrRead (MSR_COFVID_CTL, &LocalMsrRegister, StdHeader);
if (((COFVID_CTRL_MSR *) &LocalMsrRegister)->NbPstate == 0) {
// 6. Write 1 to D18F5x170[NbPstateGnbSlowDis].
PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader);
((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateGnbSlowDis = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader);
// 7. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
// 8. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid,
// CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
TransitionToNbLow (PciAddress, StdHeader);
// 9. Set D18F5x170[SwNbPstateLoDis] = 1.
// 10. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid,
// CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi].
// Go to step 15.
TransitionToNbHigh (PciAddress, StdHeader);
} else {
// 11. Set D18F5x170[SwNbPstateLoDis] = 1.
// 12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid,
// CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi].
TransitionToNbHigh (PciAddress, StdHeader);
// 13. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
// 14. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid,
// CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
TransitionToNbLow (PciAddress, StdHeader);
}
// 15. Set D18F5x170[SwNbPstateLoDis]=Temp1, D18F5x170[NbPstateDisOnP0]=Temp2, D18F5x170[NbP-
// stateThreshold]=Temp3, and D18F5x170[NbPstateGnbSlowDis]=Temp4.
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader);
((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->SwNbPstateLoDis = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->SwNbPstateLoDis;
((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateDisOnP0 = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateDisOnP0;
((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateThreshold = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateThreshold;
((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateGnbSlowDis = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateGnbSlowDis;
LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader);
}
}
/*---------------------------------------------------------------------------------------*/
/**
* Support routine for F16KbPmNbAfterResetOnCore to transition to the low NB P-state.
*
* This function implements steps 7, 8, 13, and 14 as needed.
*
* @param[in] PciAddress Segment, bus, device number of the node to transition.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
TransitionToNbLow (
IN PCI_ADDR PciAddress,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
NB_PSTATE_CTRL_REGISTER NbPsCtrl;
IDS_HDT_CONSOLE (CPU_TRACE, " TransitionToNbLow\n");
// 7/13. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
NbPsCtrl.SwNbPstateLoDis = 0;
NbPsCtrl.NbPstateDisOnP0 = 0;
NbPsCtrl.NbPstateThreshold = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
// 8/14. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid,
// CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
WaitForNbTransitionToComplete (PciAddress, NbPsCtrl.NbPstateLo, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
* Support routine for F16KbPmNbAfterResetOnCore to transition to the high NB P-state.
*
* This function implements steps 9, 10, 11, and 12 as needed.
*
* @param[in] PciAddress Segment, bus, device number of the node to transition.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
TransitionToNbHigh (
IN PCI_ADDR PciAddress,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
NB_PSTATE_CTRL_REGISTER NbPsCtrl;
IDS_HDT_CONSOLE (CPU_TRACE, " TransitionToNbHigh\n");
// 9/10. Set D18F5x170[SwNbPstateLoDis] = 1.
PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
NbPsCtrl.SwNbPstateLoDis = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
// 11/12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid,
// CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi].
WaitForNbTransitionToComplete (PciAddress, NbPsCtrl.NbPstateHi, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
* Support routine for F16KbPmAfterResetCore to wait for NB FID and DID to
* match a specific P-state.
*
* This function implements steps 8, 10, 12, and 14 as needed.
*
* @param[in] PciAddress Segment, bus, device number of the node to transition.
* @param[in] PstateIndex P-state settings to match.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
WaitForNbTransitionToComplete (
IN PCI_ADDR PciAddress,
IN UINT32 PstateIndex,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
NB_PSTATE_REGISTER TargetNbPs;
NB_PSTATE_STS_REGISTER NbPsSts;
IDS_HDT_CONSOLE (CPU_TRACE, " WaitForNbTransitionToComplete\n");
PciAddress.Address.Function = FUNC_5;
PciAddress.Address.Register = NB_PSTATE_0 + (PstateIndex << 2);
LibAmdPciRead (AccessWidth32, PciAddress, &TargetNbPs, StdHeader);
PciAddress.Address.Register = NB_PSTATE_STATUS;
do {
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsSts, StdHeader);
} while ((NbPsSts.CurNbPstate != PstateIndex ||
(NbPsSts.CurNbFid != TargetNbPs.NbFid)) ||
(NbPsSts.CurNbDid != TargetNbPs.NbDid));
}

78
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbNbAfterReset.h
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@ -1,78 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_16 Kabini after warm reset sequence for NB P-states
*
* Contains code that provide power management functionality
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x16/KB
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _CPU_F16_KB_NB_AFTER_RESET_H_
#define _CPU_F16_KB_NB_AFTER_RESET_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
VOID
F16KbPmNbAfterReset (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _CPU_F16_KB_NB_AFTER_RESET_H_

1130
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPciTables.c
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500
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerCheck.c
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@ -1,500 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_16 P-State power check
*
* Performs the "Processor-Systemboard Power Delivery Compatibility Check" as
* described in the BKDG.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x16
* @e \$Revision: 86879 $ @e \$Date: 2013-01-28 11:11:12 -0600 (Mon, 28 Jan 2013) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuF16PowerMgmt.h"
#include "cpuRegisters.h"
#include "cpuFamilyTranslation.h"
#include "F16KbPowerCheck.h"
#include "cpuServices.h"
#include "GeneralServices.h"
#include "cpuFeatures.h"
#include "cpuApicUtilities.h"
#include "Filecode.h"
CODE_GROUP (G3_DXE)
RDATA_GROUP (G3_DXE)
#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBPOWERCHECK_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
STATIC
F16KbPmPwrCheckErrorHandler (
IN VOID *ErrorData,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
STATIC
F16KbPmPwrChkCopyPstate (
IN UINT8 Dest,
IN UINT8 Src,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
STATIC
F16KbTransitionPstateCore (
IN VOID *StateNumber,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Family 16h Kabini core 0 entry point for performing the family 16h Processor-
* Systemboard Power Delivery Check.
*
* The steps are as follows:
* 1. Starting with P0, loop through all P-states until a passing state is
* found. A passing state is one in which the current required by the
* CPU is less than the maximum amount of current that the system can
* provide to the CPU. If P0 is under the limit, no further action is
* necessary.
* 2. If at least one P-State is under the limit & at least one P-State is
* over the limit, the BIOS must:
* a. If the processor's current P-State is disabled by the power check,
* then the BIOS must request a transition to an enabled P-state
* using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate]
* to reflect the new value.
* b. Copy the contents of the enabled P-state MSRs to the highest
* performance P-state locations.
* c. Request a P-state transition to the P-state MSR containing the
* COF/VID values currently applied.
* d. If a subset of boosted P-states are disabled, then copy the contents
* of the highest performance boosted P-state still enabled to the
* boosted P-states that have been disabled.
* e. If all boosted P-states are disabled, then program D18F4x15C[BoostSrc]
* to zero.
* f. Adjust the following P-state parameters affected by the P-state
* MSR copy by subtracting the number of P-states that are disabled
* by the power check.
* 1. F3x64[HtcPstateLimit]
* 2. F3x68[SwPstateLimit]
* 3. F3xDC[PstateMaxVal]
* 3. If all P-States are over the limit, the BIOS must:
* a. If the processor's current P-State is !=F3xDC[PstateMaxVal], then
* write F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for
* MSRC001_0063[CurPstate] to reflect the new value.
* b. If MSRC001_0061[PstateMaxVal]!=000b, copy the contents of the P-state
* MSR pointed to by F3xDC[PstateMaxVal] to the software P0 MSR.
* Write 000b to MSRC001_0062[PstateCmd] and wait for MSRC001_0063
* [CurPstate] to reflect the new value.
* c. Adjust the following P-state parameters to zero:
* 1. F3x64[HtcPstateLimit]
* 2. F3x68[SwPstateLimit]
* 3. F3xDC[PstateMaxVal]
* d. Program D18F4x15C[BoostSrc] to zero.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParams Service parameters
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F16KbPmPwrCheck (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 DisPsNum;
UINT8 PsMaxVal;
UINT8 Pstate;
UINT32 ProcIddMax;
UINT32 LocalPciRegister;
UINT32 PstateLimit;
UINT32 SwPstateAdjust;
PCI_ADDR PciAddress;
UINT64 LocalMsrRegister;
PWRCHK_ERROR_DATA ErrorData;
ErrorData.SocketNumber = 0;
// get the Max P-state value
for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) {
LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &LocalMsrRegister, StdHeader);
if (((F16_PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
break;
}
}
ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1);
// Starting with P0, loop through all P-states until a passing state is
// found. A passing state is one in which the current required by the
// CPU is less than the maximum amount of current that the system can
// provide to the CPU. If P0 is under the limit, no further action is
// necessary.
DisPsNum = 0;
for (Pstate = 0; Pstate < ErrorData.HwPstateNumber; Pstate++) {
if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) {
if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].MaximumCurrentLimit) {
// Add to event log the Pstate that exceeded the current limit
PutEventLog (AGESA_WARNING,
CPU_EVENT_PM_PSTATE_OVERCURRENT,
0, Pstate, 0, 0, StdHeader);
DisPsNum++;
} else {
break;
}
}
}
ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisPsNum);
if (ErrorData.AllowablePstateNumber == 0) {
PutEventLog (AGESA_FATAL,
CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT,
0, 0, 0, 0, StdHeader);
}
if (DisPsNum != 0) {
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F4x15C
ErrorData.NumberOfBoostStates = (UINT8) ((F16_CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates;
if (DisPsNum >= ErrorData.NumberOfBoostStates) {
// If all boosted P-states are disabled, then program D18F4x15C[BoostSrc] to zero.
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((F16_CPB_CTRL_REGISTER *) (&LocalPciRegister))->BoostSrc = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
// Update the result of isFeatureEnabled in heap.
UpdateFeatureStatusInHeap (CoreBoost, FALSE, StdHeader);
ErrorData.NumberOfSwPstatesDisabled = DisPsNum - ErrorData.NumberOfBoostStates;
} else {
ErrorData.NumberOfSwPstatesDisabled = 0;
}
PciAddress.AddressValue = HTC_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x64
ErrorData.HtcPstate = (UINT8) (((HTC_REGISTER *) (&LocalPciRegister))->HtcPstateLimit);
F16KbPmPwrCheckErrorHandler (&ErrorData, StdHeader);
// Final Step
// F3x64[HtcPstatelimit] -= disPsNum
// F3x68[SwPstateLimit] -= disPsNum
// F3xDC[HwPstateMaxVal] -= disPsNum
if (ErrorData.NumberOfSwPstatesDisabled != 0) {
PstateLimit = ((HTC_REGISTER *) &LocalPciRegister)->HtcPstateLimit;
if (PstateLimit > PsMaxVal) {
SwPstateAdjust = PstateLimit - PsMaxVal;
} else {
SwPstateAdjust = 0;
}
if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) {
PstateLimit -= ErrorData.NumberOfSwPstatesDisabled;
} else {
PstateLimit = ErrorData.NumberOfBoostStates;
}
if (PstateLimit <= ErrorData.NumberOfBoostStates) {
PstateLimit = ErrorData.NumberOfBoostStates + SwPstateAdjust;
}
((HTC_REGISTER *) (&LocalPciRegister))->HtcPstateLimit = PstateLimit;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
PciAddress.Address.Register = SW_PS_LIMIT_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x68
PstateLimit = ((SW_PS_LIMIT_REGISTER *) &LocalPciRegister)->SwPstateLimit;
if (PstateLimit > PsMaxVal) {
SwPstateAdjust = PstateLimit - PsMaxVal;
} else {
SwPstateAdjust = 0;
}
if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) {
PstateLimit -= ErrorData.NumberOfSwPstatesDisabled;
} else {
PstateLimit = ErrorData.NumberOfBoostStates;
}
if (PstateLimit <= ErrorData.NumberOfBoostStates) {
PstateLimit = ErrorData.NumberOfBoostStates + SwPstateAdjust;
}
((SW_PS_LIMIT_REGISTER *) (&LocalPciRegister))->SwPstateLimit = PstateLimit;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
PciAddress.Address.Register = CPTC2_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xDC
PstateLimit = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->HwPstateMaxVal;
if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) {
PstateLimit -= ErrorData.NumberOfSwPstatesDisabled;
} else {
PstateLimit = ErrorData.NumberOfBoostStates;
}
if (PstateLimit < ErrorData.NumberOfBoostStates) {
PstateLimit = ErrorData.NumberOfBoostStates;
}
((CLK_PWR_TIMING_CTRL2_REGISTER *) (&LocalPciRegister))->HwPstateMaxVal = PstateLimit;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
}
}
/*---------------------------------------------------------------------------------------*/
/**
* Error handler called if any p-states were determined to be out
* of range for the mother board.
*
* This function implements steps 2a-c and 3a-c on each core.
*
* @param[in] ErrorData Details about the error condition.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
F16KbPmPwrCheckErrorHandler (
IN VOID *ErrorData,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 i;
UINT8 HwPsMaxVal;
UINT8 SwPsMaxVal;
UINT8 HwDisPsNum;
UINT8 CurrentSwPs;
UINT8 ShiftIndex;
UINT8 PsDisableCount;
UINT8 NewSwP0;
UINT8 StateNumber;
UINT8 Core;
UINT32 ActiveCores;
UINT64 LocalMsrRegister;
BOOLEAN DisableAllBoostPstates;
AP_TASK ApTask;
AGESA_STATUS IgnoreStatus;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
if (IsBsp (StdHeader, &IgnoreStatus)) {
// P-state MSRs are shared, so only BSC needs to perform this
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
GetActiveCoresInCurrentSocket (&ActiveCores, StdHeader);
HwPsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1);
HwDisPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber -
((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber);
LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader);
CurrentSwPs = (UINT8) (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate);
LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader);
SwPsMaxVal = (UINT8) (((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal);
PsDisableCount = 0;
if (((PWRCHK_ERROR_DATA *) ErrorData)->HtcPstate > HwPsMaxVal) {
ShiftIndex = ((PWRCHK_ERROR_DATA *) ErrorData)->HtcPstate;
} else {
ShiftIndex = HwPsMaxVal;
}
DisableAllBoostPstates = FALSE;
// Prepare ApTask
ApTask.FuncAddress.PfApTaskI = F16KbTransitionPstateCore;
ApTask.DataTransfer.DataSizeInDwords = 1;
ApTask.DataTransfer.DataPtr = &StateNumber;
ApTask.DataTransfer.DataTransferFlags = 0;
ApTask.ExeFlags = 0;
if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) {
// All P-States are over the limit.
// Step 1
// Transition to Pstate Max if not there already
if (CurrentSwPs != SwPsMaxVal) {
StateNumber = SwPsMaxVal;
for (Core = 1; Core < (UINT8) ActiveCores; ++Core) {
ApUtilRunCodeOnSocketCore (0, Core, &ApTask, StdHeader);
}
ApUtilTaskOnExecutingCore (&ApTask, StdHeader, (VOID *) NULL);
}
// Step 2
// If Pstate Max is not P0, copy Pstate max contents to P0 and switch
// to P0.
for (i = 0; i <= (ShiftIndex - HwPsMaxVal); i++) {
F16KbPmPwrChkCopyPstate ((((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates + i), (HwPsMaxVal + i), StdHeader);
}
StateNumber = 0;
for (Core = 1; Core < (UINT8) ActiveCores; ++Core) {
ApUtilRunCodeOnSocketCore (0, Core, &ApTask, StdHeader);
}
ApUtilTaskOnExecutingCore (&ApTask, StdHeader, (VOID *) NULL);
// Disable all SW P-states except P0
PsDisableCount = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled - 1;
// Set a flag to disable all boost P-states
DisableAllBoostPstates = TRUE;
} else {
// At least one P-State is under the limit & at least one P-State is
// over the limit.
if (((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates > HwDisPsNum) {
// A subset of boosted P-states are disabled. Copy the contents of the
// highest performance boosted P-state still enabled to the boosted
// P-states that have been disabled.
for (i = 0; i < HwDisPsNum; i++) {
F16KbPmPwrChkCopyPstate (i, HwDisPsNum, StdHeader);
}
} else {
// Set a flag to disable all boost P-states
DisableAllBoostPstates = TRUE;
if (((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled != 0) {
// Move remaining P-state register(s) up
// Step 1
// Transition to a valid Pstate if current Pstate has been disabled
if (CurrentSwPs < ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled) {
StateNumber = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled;
for (Core = 1; Core < (UINT8) ActiveCores; ++Core) {
ApUtilRunCodeOnSocketCore (0, Core, &ApTask, StdHeader);
}
ApUtilTaskOnExecutingCore (&ApTask, StdHeader, (VOID *) NULL);
CurrentSwPs = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled;
}
// Step 2
// Move enabled Pstates up and disable the remainder
NewSwP0 = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates + ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled;
for (i = 0; i <= (ShiftIndex - NewSwP0); i++) {
F16KbPmPwrChkCopyPstate ((i + ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates), (i + NewSwP0), StdHeader);
}
// Step 3
// Transition to current COF/VID at shifted location
CurrentSwPs = (CurrentSwPs - ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled);
StateNumber = CurrentSwPs;
for (Core = 1; Core < (UINT8) ActiveCores; ++Core) {
ApUtilRunCodeOnSocketCore (0, Core, &ApTask, StdHeader);
}
ApUtilTaskOnExecutingCore (&ApTask, StdHeader, (VOID *) NULL);
// Disable the appropriate number of P-states
PsDisableCount = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled;
}
}
}
// Disable all boost P-states
if (DisableAllBoostPstates) {
for (i = 0; i < ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates; i++) {
FamilySpecificServices->DisablePstate (FamilySpecificServices, i, StdHeader);
}
}
// Disable the appropriate P-states if any, starting from HW Pmin
for (i = 0; i < PsDisableCount; i++) {
FamilySpecificServices->DisablePstate (FamilySpecificServices, (HwPsMaxVal - i), StdHeader);
}
}
}
/*---------------------------------------------------------------------------------------*/
/**
* Copies the contents of one P-State MSR to another.
*
* @param[in] Dest Destination p-state number
* @param[in] Src Source p-state number
* @param[in] StdHeader Config handle for library and services
*
*/
VOID
STATIC
F16KbPmPwrChkCopyPstate (
IN UINT8 Dest,
IN UINT8 Src,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 LocalMsrRegister;
LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader);
LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
* Core-level transition Pstate
*
* Transitions the executing core to the desired P-state.
*
* @param[in] StateNumber The new P-State to make effective.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
F16KbTransitionPstateCore (
IN VOID *StateNumber,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->TransitionPstate (FamilySpecificServices, *((UINT8 *) StateNumber), (BOOLEAN) TRUE, StdHeader);
}

84
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerCheck.h
View File

@ -1,84 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_16 Kabini Power related functions and structures
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x16/KB
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _F16_KB_POWER_CHECK_H_
#define _F16_KB_POWER_CHECK_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/// Power Check Error Data
typedef struct {
UINT8 SocketNumber; ///< Socket Number
UINT8 HwPstateNumber; ///< Number of hardware P-states
UINT8 AllowablePstateNumber; ///< Number of allowable P-states
UINT8 NumberOfBoostStates; ///< Number of boosted P-states
UINT8 NumberOfSwPstatesDisabled; ///< Number of software P-states disabled
UINT8 HtcPstate; ///< HTC Pstate Limit Pstate
} PWRCHK_ERROR_DATA;
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
VOID
F16KbPmPwrCheck (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _F16_KB_POWER_CHECK_H_

535
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerMgmt.h
View File

@ -1,535 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_16 Kabini Power Management related registers defination
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x16/KB
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _CPU_F16_KB_POWERMGMT_H_
#define _CPU_F16_KB_POWERMGMT_H_
/*
* Family 16h Kabini CPU Power Management MSR definitions
*
*/
/* NB Machine Check Misc 4 MSR Register 0x00000413 */
#define MC4_MISC0 0x00000413ul
/// Interrupt Pending and CMP-Halt MSR Register
typedef struct {
UINT64 :24; ///< Reserved
UINT64 BlkPtr:8; ///< Block pointer for additional MISC registers
UINT64 ErrCnt:12; ///< Error counter
UINT64 :4; ///< Reserved
UINT64 Ovrflw:1; ///< Overflow
UINT64 IntType:2; ///< Interrupt type
UINT64 CntEn:1; ///< Counter enable
UINT64 LvtOffset:4; ///< LVT offset
UINT64 :5; ///< Reserved
UINT64 Locked:1; ///< Locked
UINT64 CntP:1; ///< Counter present
UINT64 Valid:1; ///< Valid
} MC4_MISC0_MSR;
/* P-state Registers 0xC00100[6B:64] */
/// P-state MSR
typedef struct {
UINT64 CpuFid:6; ///< CpuFid
UINT64 CpuDid:3; ///< CpuDid
UINT64 CpuVid:8; ///< CpuVid
UINT64 :5; ///< Reserved
UINT64 NbPstate:1; ///< NbPstate
UINT64 :9; ///< Reserved
UINT64 IddValue:8; ///< IddValue
UINT64 IddDiv:2; ///< IddDiv
UINT64 :21; ///< Reserved
UINT64 PsEnable:1; ///< Pstate Enable
} PSTATE_MSR;
#define GetF16KbCpuVid(PstateMsr) (((PSTATE_MSR *) PstateMsr)->CpuVid)
/* VID operation related macros */
#define ConvertVidInuV(Vid) (1550000 - (6250 * Vid)) ///< Convert VID in uV.
/* COFVID Control Register 0xC0010070 */
#define MSR_COFVID_CTL 0xC0010070ul
/// COFVID Control MSR Register
typedef struct {
UINT64 CpuFid:6; ///< CpuFid
UINT64 CpuDid:3; ///< CpuDid
UINT64 CpuVid_6_0:7; ///< CpuVid[6:0]
UINT64 PstateId:3; ///< Pstate ID
UINT64 :1; ///< Reserved
UINT64 CpuVid_7:1; ///< CpuVid[7]
UINT64 :1; ///< Reserved
UINT64 NbPstate:1; ///< Northbridge P-state
UINT64 :1; ///< Reserved
UINT64 NbVid:8; ///< NbVid
UINT64 :32; ///< Reserved
} COFVID_CTRL_MSR;
#define COFVID_CTRL_MSR_CurCpuVid_6_0_OFFSET 9
#define COFVID_CTRL_MSR_CurCpuVid_6_0_WIDTH 7
#define COFVID_CTRL_MSR_CurCpuVid_6_0_MASK 0xfe00
#define COFVID_CTRL_MSR_CurCpuVid_7_OFFSET 20
#define COFVID_CTRL_MSR_CurCpuVid_7_WIDTH 1
#define COFVID_CTRL_MSR_CurCpuVid_7_MASK 0x100000ul
/* SVI VID Encoding */
///< Union structure of VID in SVI1/SVI2 modes
typedef union {
UINT32 RawVid; ///< Raw VID value
struct { ///< SVI2 mode VID structure
UINT32 Vid_6_0:7; ///< Vid[6:0] of SVI2 mode
UINT32 Vid_7:1; ///< Vid[7] of SVI2 mode
} SVI2;
struct { ///< SVI1 mode VID structure
UINT32 Vid_LSB_Ignore:1; ///< Ignored LSB of 8bit VID encoding in SVI1 mode
UINT32 Vid_6_0:1; ///< Vid[6:0] of SVI mode
} SVI1;
} SVI_VID;
#define SetF16KbCpuVid(CofVidStsMsr, NewCpuVid) ( \
((COFVID_CTRL_MSR *) CofVidStsMsr)->CurCpuVid_6_0) = ((SVI_VID *) NewCpuVid)->SVI2.Vid_6_0; \
((COFVID_CTRL_MSR *) CofVidStsMsr)->CurCpuVid_7) = ((SVI_VID *) NewCpuVid)->SVI2.Vid_7; \
)
/* COFVID Status Register 0xC0010071 */
#define MSR_COFVID_STS 0xC0010071ul
/// COFVID Status MSR Register
typedef struct {
UINT64 CurCpuFid:6; ///< Current CpuFid
UINT64 CurCpuDid:3; ///< Current CpuDid
UINT64 CurCpuVid_6_0:7; ///< Current CpuVid[6:0]
UINT64 CurPstate:3; ///< Current Pstate
UINT64 :1; ///< Reserved
UINT64 CurCpuVid_7:1; ///< Current CpuVid[7]
UINT64 :2; ///< Reserved
UINT64 NbPstateDis:1; ///< NbPstate Disable
UINT64 :8;
UINT64 StartupPstate:3; ///< Startup Pstate
UINT64 :14; ///< Reserved
UINT64 MaxCpuCof:6; ///< MaxCpuCof
UINT64 :1; ///< Reserved
UINT64 CurPstateLimit:3; ///< Current Pstate Limit
UINT64 MaxNbCof:5; ///< MaxNbCof
} COFVID_STS_MSR;
#define COFVID_STS_MSR_CurCpuVid_6_0_OFFSET 9
#define COFVID_STS_MSR_CurCpuVid_6_0_WIDTH 7
#define COFVID_STS_MSR_CurCpuVid_6_0_MASK 0xfe00
#define COFVID_STS_MSR_CurCpuVid_7_OFFSET 20
#define COFVID_STS_MSR_CurCpuVid_7_WIDTH 1
#define COFVID_STS_MSR_CurCpuVid_7_MASK 0x100000ul
#define GetF16KbCurCpuVid(CofVidStsMsr) ( \
(((COFVID_STS_MSR *) CofVidStsMsr)->CurCpuVid_7 << COFVID_STS_MSR_CurCpuVid_6_0_WIDTH) \
| ((COFVID_STS_MSR *) CofVidStsMsr)->CurCpuVid_6_0)
/*
* Family 16h Kabini CPU Power Management PCI definitions
*
*/
/* Link Initialization Status D18F0x1A0 */
#define LINK_INIT_STATUS_REG 0x1A0
#define LINK_INIT_STATUS_REG_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_0, LINK_INIT_STATUS_REG))
/// Link Initialization Status
typedef struct {
UINT32 InitComplete0:2; ///< Initialization complete for link 0
UINT32 InitComplete1:2; ///< Initialization complete for link 1
UINT32 :20; ///< Reserved
UINT32 IntNbExtCap:4; ///< Internal NB extneded capability
UINT32 :3; ///< Reserved
UINT32 InitStatusValid:1; ///< Initialization status valid
} LINK_INIT_STATUS_REGISTER;
/* NB Configuration 1 Low F3x88 */
#define NB_CFG1_LOW_REG 0x88
#define NB_CFG1_LOW_REG_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, NB_CFG1_LOW_REG))
/// Power Control Miscellaneous PCI Register
typedef struct {
UINT32 :18; ///< Reserved
UINT32 DisCstateBoostBlockPstateUp:1; ///< DisCstateBoostBlockPstateUp
UINT32 :12; ///< Reserved
UINT32 DisCohLdtCfg:1; ///< Disable coherent link configuration accesses
} NB_CFG1_LOW_REG_REGISTER;
/* Power Control Miscellaneous Register F3xA0 */
#define PW_CTL_MISC_REG 0xA0
#define PW_CTL_MISC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, PW_CTL_MISC_REG))
/// Power Control Miscellaneous PCI Register
typedef struct {
UINT32 PsiVid:7; ///< PSI_L VID threshold VID[6:0]
UINT32 PsiVidEn:1; ///< PSI_L VID enable
UINT32 PsiVid_7:1; ///< PSI_L VID threshold VID[7]
UINT32 :1; ///< Reserved
UINT32 IdleExitEn:1; ///< Idle exit enable
UINT32 PllLockTime:3; ///< PLL synchronization lock time
UINT32 Svi2HighFreqSel:1; ///< SVI2 high frequency select
UINT32 :1; ///< Reserved
UINT32 ConfigId:12; ///< Configuration ID
UINT32 :3; ///< Reserved
UINT32 CofVidProg:1; ///< COF and VID of Pstate programmed
} POWER_CTRL_MISC_REGISTER;
/* Clock Power/Timing Control 0 Register F3xD4 */
#define CPTC0_REG 0xD4
#define CPTC0_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC0_REG))
/// Clock Power Timing Control PCI Register
typedef struct {
UINT32 MaxSwPstateCpuCof:6; ///< Maximum software P-state core COF
UINT32 :2; ///< Reserved
UINT32 ClkRampHystSel:4; ///< Clock Ramp Hysteresis Select
UINT32 ClkRampHystCtl:1; ///< Clock Ramp Hysteresis Control
UINT32 :1; ///< Reserved
UINT32 CacheFlushImmOnAllHalt:1; ///< Cache Flush Immediate on All Halt
UINT32 :5; ///< Reserved
UINT32 PowerStepDown:4; ///< Power Step Down
UINT32 PowerStepUp:4; ///< Power Step Up
UINT32 NbClkDiv:3; ///< NbClkDiv
UINT32 NbClkDivApplyAll:1; ///< NbClkDivApplyAll
} CLK_PWR_TIMING_CTRL_REGISTER;
/* Clock Power/Timing Control 1 Register F3xD8 */
#define CPTC1_REG 0xD8
#define CPTC1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC1_REG))
/// Clock Power Timing Control 1 PCI Register
typedef struct {
UINT32 :4; ///< Reserved
UINT32 VSRampSlamTime:3; ///< Voltage stabilization ramp time
UINT32 :25; ///< Reserved
} CLK_PWR_TIMING_CTRL1_REGISTER;
/* Northbridge Capabilities Register F3xE8 */
#define NB_CAPS_REG 0xE8
#define NB_CAPS_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, NB_CAPS_REG))
/// Northbridge Capabilities PCI Register
typedef struct {
UINT32 :1; ///< Reserved
UINT32 DualNode:1; ///< Dual-node multi-processor capable
UINT32 EightNode:1; ///< Eight-node multi-processor capable
UINT32 Ecc:1; ///< ECC capable
UINT32 Chipkill:1; ///< Chipkill ECC capable
UINT32 :3; ///< Reserved
UINT32 MctCap:1; ///< Memory controller capable
UINT32 SvmCapable:1; ///< SVM capable
UINT32 HtcCapable:1; ///< HTC capable
UINT32 :3; ///< Reserved
UINT32 MultVidPlane:1; ///< Multiple VID plane capable
UINT32 :4; ///< Reserved
UINT32 x2Apic:1; ///< x2Apic capability
UINT32 :4; ///< Reserved
UINT32 MemPstateCap:1; ///< Memory P-state capable
UINT32 :3; ///< Reserved
UINT32 Succor:1; ///< SUCCOR
UINT32 :3; ///< Reserved
} NB_CAPS_REGISTER;
/* Sample and Residency Timers Register D18F4x110 */
#define SAMPLE_RESIDENCY_TIMER_REG 0x110
#define SAMPLE_RESIDENCY_TIMER_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, SAMPLE_RESIDENCY_TIMER_REG))
/// Sample and Residency Timers Register
typedef struct {
UINT32 CSampleTimer:12; ///< CSampleTimer
UINT32 FastCSampleTimer:1; ///< FastCSampleTimer
UINT32 MinResTmr:8; ///< Minimum residency timer
UINT32 :11; ///< Reserved
} SAMPLE_RESIDENCY_TIMER_REGISTER;
/* C-state Control 1 Register D18F4x118 */
#define CSTATE_CTRL1_REG 0x118
#define CSTATE_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL1_REG))
/// C-state Control 1 Register
typedef struct {
UINT32 CpuPrbEnCstAct0:1; ///< Core direct probe enable
UINT32 CacheFlushEnCstAct0:1; ///< Cache flush enable
UINT32 CacheFlushTmrSelCstAct0:2; ///< Cache flush timer select
UINT32 :1; ///< Reserved
UINT32 ClkDivisorCstAct0:3; ///< Clock divisor
UINT32 PwrGateEnCstAct0:1; ///< Power gate enable
UINT32 PwrOffEnCstAct0:1; ///< C-state action field 3
UINT32 NbPwrGate0:1; ///< NB power-gating 0
UINT32 NbClkGate0:1; ///< NB clock-gating 0
UINT32 SelfRefr0:1; ///< Self-refresh 0
UINT32 SelfRefrEarly0:1; ///< Allow early self-refresh 0
UINT32 :2; ///< Reserved
UINT32 CpuPrbEnCstAct1:1; ///< Core direct probe enable
UINT32 CacheFlushEnCstAct1:1; ///< Cache flush eable
UINT32 CacheFlushTmrSelCstAct1:2; ///< Cache flush timer select
UINT32 :1; ///< Reserved
UINT32 ClkDivisorCstAct1:3; ///< Clock divisor
UINT32 PwrGateEnCstAct1:1; ///< Power gate enable
UINT32 PwrOffEnCstAct1:1; ///< C-state action field 3
UINT32 NbPwrGate1:1; ///< NB power-gating 1
UINT32 NbClkGate1:1; ///< NB clock-gating 1
UINT32 SelfRefr1:1; ///< Self-refresh 1
UINT32 SelfRefrEarly1:1; ///< Allow early self-refresh 1
UINT32 :2; ///< Reserved
} CSTATE_CTRL1_REGISTER;
/* C-state Control 2 Register D18F4x11C */
#define CSTATE_CTRL2_REG 0x11C
#define CSTATE_CTRL2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL2_REG))
/// C-state Control 2 Register
typedef struct {
UINT32 CpuPrbEnCstAct2:1; ///< Core direct probe enable
UINT32 CacheFlushEnCstAct2:1; ///< Cache flush eable
UINT32 CacheFlushTmrSelCstAct2:2; ///< Cache flush timer select
UINT32 :1; ///< Reserved
UINT32 ClkDivisorCstAct2:3; ///< Clock divisor
UINT32 PwrGateEnCstAct2:1; ///< Power gate enable
UINT32 PwrOffEnCstAct2:1; ///< C-state action field 3
UINT32 NbPwrGate2:1; ///< NB power-gating 2
UINT32 NbClkGate2:1; ///< NB clock-gating 2
UINT32 SelfRefr2:1; ///< Self-refresh 2
UINT32 SelfRefrEarly2:1; ///< Allow early self-refresh 2
UINT32 :18; ///< Reserved
} CSTATE_CTRL2_REGISTER;
/* Cstate Policy Control 1 Register D18F4x128 */
#define CSTATE_POLICY_CTRL1_REG 0x128
#define CSTATE_POLICY_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_POLICY_CTRL1_REG))
/// Cstate Policy Control 1 Register
typedef struct {
UINT32 :2; ///< Reserved
UINT32 HaltCstateIndex:3; ///< Specifies the IO-based C-state that is invoked by a HLT instruction
UINT32 CacheFlushTmr:7; ///< Cache flush timer
UINT32 :6; ///< Reserved
UINT32 CacheFlushSucMonThreshold:3; ///< Cache flush success monitor threshold
UINT32 CacheFlushSucMonTmrSel:2; ///< Cache flush success monitor timer select
UINT32 CacheFlushSucMonMispredictAct:2; ///< Cache flush success monitor mispredict action
UINT32 :6; ///< Reserved
UINT32 CstateMsgDis:1; ///< C-state messaging disable
} CSTATE_POLICY_CTRL1_REGISTER;
/* Core Performance Boost Control Register D18F4x15C */
/// Core Performance Boost Control Register
typedef struct {
UINT32 BoostSrc:2; ///< Boost source
UINT32 NumBoostStates:3; ///< Number of boosted states
UINT32 :2; ///< Reserved
UINT32 ApmMasterEn:1; ///< APM master enable
UINT32 CstatePowerEn:1; ///< C-state Power Enable
UINT32 :22; ///< Reserved
UINT32 BoostLock:1; ///<
} CPB_CTRL_REGISTER;
/* Northbridge Capabilities 2 F5x84*/
#define NB_CAPS_REG2 0x84
#define NB_CAPS_REG2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_CAPS_REG2))
/// Northbridge Capabilities 2 PCI Register
typedef struct {
UINT32 CmpCap:8; ///< CMP capable
UINT32 :4; ///< Reserved
UINT32 DctEn:4; ///< DCT enabled
UINT32 DdrMaxRate:5; ///< maximum DDR rate
UINT32 :3; ///< Reserved
UINT32 DdrMaxRateEnf:5; ///< enforced maximum DDR rate:
UINT32 :3; ///< Reserved
} NB_CAPS_2_REGISTER;
/* Northbridge Configuration 4 F5x88*/
#define NB_CFG_REG4 0x88
#define NB_CFG_REG4_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_CFG_REG4))
/// Northbridge Configuration 4 PCI Register
typedef struct {
UINT32 CC6PstateWakeUpDis:1; ///< CC6PstateWakeUpDis
UINT32 :17; ///< Reserved
UINT32 EnCstateBoostBlockCC6Exit:1;///< EnCstateBoostBlockCC6Exit
UINT32 :5; ///< Reserved
UINT32 DisHbNpReqBusLock:1; ///< DisHbNpReqBusLock
UINT32 :7; ///< Reserved
} NB_CFG_4_REGISTER;
typedef struct {
UINT32 Bits_19_0:20; ///< Bits[19:0]
UINT32 Bits_31_20:12; ///< Reserved
} pmgmt_str0;
typedef struct {
UINT32 Bits_19_0:20; ///< Bits[19:0]
UINT32 Bits_31_20:12; ///< Reserved
} pmgmt_str1;
/* Northbridge P-state [3:0] F5x1[6C:60] */
/// Northbridge P-state Register
typedef struct {
UINT32 NbPstateEn:1; ///< NB P-state enable
UINT32 NbFid:6; ///< NB frequency ID
UINT32 NbDid:1; ///< NB divisor ID
UINT32 :2; ///< Reserved
UINT32 NbVid_6_0:7; ///< NB VID[6:0]
UINT32 :1; ///< Reserved
UINT32 MemPstate:1; ///< Memory P-State
UINT32 :2; ///< Reserved
UINT32 NbVid_7:1; ///< NB VID[7]
UINT32 NbIddDiv:2; ///< northbridge current divisor
UINT32 NbIddValue:8; ///< northbridge current value
} NB_PSTATE_REGISTER;
#define NB_PSTATE_REGISTER_NbVid_6_0_OFFSET 10
#define NB_PSTATE_REGISTER_NbVid_6_0_WIDTH 7
#define NB_PSTATE_REGISTER_NbVid_6_0_MASK 0x0001FC00ul
#define NB_PSTATE_REGISTER_NbVid_7_OFFSET 21
#define NB_PSTATE_REGISTER_NbVid_7_WIDTH 1
#define NB_PSTATE_REGISTER_NbVid_7_MASK 0x00200000ul
#define GetF16KbNbVid(NbPstateRegister) ( \
(((NB_PSTATE_REGISTER *) NbPstateRegister)->NbVid_7 << NB_PSTATE_REGISTER_NbVid_6_0_WIDTH) \
| ((NB_PSTATE_REGISTER *) NbPstateRegister)->NbVid_6_0)
#define SetF16KbNbVid(NbPstateRegister, NewNbVid) { \
((NB_PSTATE_REGISTER *) NbPstateRegister)->NbVid_6_0 = ((SVI_VID *) NewNbVid)->SVI2.Vid_6_0; \
((NB_PSTATE_REGISTER *) NbPstateRegister)->NbVid_7 = ((SVI_VID *) NewNbVid)->SVI2.Vid_7; \
}
/* Northbridge P-state Status */
#define NB_PSTATE_CTRL 0x170
#define NB_PSTATE_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_CTRL))
/// Northbridge P-state Control Register
typedef struct {
UINT32 NbPstateMaxVal:2; ///< NB P-state maximum value
UINT32 :1; ///< Reserved
UINT32 NbPstateLo:2; ///< NB P-state low
UINT32 :1; ///< Reserved
UINT32 NbPstateHi:2; ///< NB P-state high
UINT32 :1; ///< Reserved
UINT32 NbPstateThreshold:4; ///< NB P-state threshold
UINT32 NbPstateDisOnP0:1; ///< NB P-state disable on P0
UINT32 SwNbPstateLoDis:1; ///< Software NB P-state low disable
UINT32 :8; ///< Reserved
UINT32 NbPstateGnbSlowDis:1; ///< NbPstateGnbSlowDis
UINT32 NbPstateLoRes:3; ///< NB P-state low residency timer
UINT32 NbPstateHiRes:3; ///< NB P-state high residency timer
UINT32 NbPstateFidVidSbcEn:1; ///< NbPstateFidVidSbcEn
UINT32 MemPstateDis:1; ///< Memory P-state disable
} NB_PSTATE_CTRL_REGISTER;
/* Northbridge P-state Status */
#define NB_PSTATE_STATUS 0x174
#define NB_PSTATE_STATUS_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_STATUS))
/// Northbridge P-state Status Register
typedef struct {
UINT32 NbPstateDis:1; ///< Nb pstate disable
UINT32 StartupNbPstate:2; ///< startup northbridge Pstate number
UINT32 CurNbFid:6; ///< Current NB FID
UINT32 CurNbDid:1; ///< Current NB DID
UINT32 :2; ///< Reserved
UINT32 CurNbVid_6_0:7; ///< Current NB VID[6:0]
UINT32 CurNbPstate:2; ///< Current NB Pstate
UINT32 :1; ///< Reserved
UINT32 CurNbPstateLo:1; ///< Current NB Pstate maps to Lo or Hi
UINT32 CurNbVid_7:1; ///< Current NB VID[7]
UINT32 CurMemPstate:1; ///< Current memory P-state
UINT32 :7; ///< Reserved
} NB_PSTATE_STS_REGISTER;
#define NB_PSTATE_STS_REGISTER_CurNbVid_6_0_OFFSET 12
#define NB_PSTATE_STS_REGISTER_CurNbVid_6_0_WIDTH 7
#define NB_PSTATE_STS_REGISTER_CurNbVid_6_0_MASK 0x0007F000ul
#define NB_PSTATE_STS_REGISTER_CurNbVid_7_OFFSET 23
#define NB_PSTATE_STS_REGISTER_CurNbVid_7_WIDTH 1
#define NB_PSTATE_STS_REGISTER_CurNbVid_7_MASK 0x00800000ul
#define GetF16KbCurNbVid(NbPstateStsRegister) ( \
(((NB_PSTATE_STS_REGISTER *) NbPstateStsRegister)->CurNbVid_7 << NB_PSTATE_STS_REGISTER_CurNbVid_6_0_WIDTH) \
| ((NB_PSTATE_STS_REGISTER *) NbPstateStsRegister)->CurNbVid_6_0)
/* Miscellaneous Voltages */
#define MISC_VOLTAGES 0x17C
#define MISC_VOLTAGES_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, MISC_VOLTAGES))
/// Miscellaneous Voltages Register
typedef struct {
UINT32 MaxVid:8; ///< Maximum Voltage
UINT32 :2; ///< Reserved
UINT32 MinVid:8; ///< Minimum Voltage
UINT32 :5; ///< Reserved
UINT32 NbPsi0Vid:8; ///< Northbridge PSI0_L VID threshold
UINT32 NbPsi0VidEn:1; ///< Northbridge PSI0_L VID enable
} MISC_VOLTAGE_REGISTER;
/* Clock Power/Timing Control 5 Register F5x188 */
#define CPTC5_REG 0x188
#define CPTC5_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, CPTC5_REG))
/// Clock Power Timing Control 5 Register
typedef struct {
UINT32 NbOffsetTrim:2; ///< Northbridge offset trim
UINT32 NbLoadLineTrim:3; ///< Northbridge load line trim
UINT32 NbPsi1:1; ///< Northbridge PSI1_L
UINT32 :1; ///< Northbridge telemetry functionality.
UINT32 :25; ///< Reserved
} CLK_PWR_TIMING_CTRL_5_REGISTER;
#endif /* _CPU_F16_KB_POWERMGMT_H_ */

153
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerMgmtSystemTables.c
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@ -1,153 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_16 Models 0x00 - 0x0F Kabini Power Management related initialization table
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x16/KB
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "Ids.h"
#include "cpuRegisters.h"
#include "cpuApicUtilities.h"
#include "cpuFamilyTranslation.h"
#include "cpuPowerMgmtSystemTables.h"
#include "F16KbUtilities.h"
#include "F16KbCoreAfterReset.h"
#include "F16KbNbAfterReset.h"
#include "F16KbPowerCheck.h"
#include "IdsF16KbAllService.h"
#include "Filecode.h"
CODE_GROUP (G2_PEI)
RDATA_GROUP (G2_PEI)
#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBPOWERMGMTSYSTEMTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
GetF16KbSysPmTable (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **SysPmTblPtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/* Family 16h Kabini Only Table */
/* ---------------------- */
CONST SYS_PM_TBL_STEP ROMDATA CpuF16KbSysPmTableArray[] =
{
/// @todo
IDS_INITIAL_F16_KB_PM_STEP
// Step 1 - Configure F3x[84:80]. Handled by PCI register table.
// Step 2 - Disable NB Pstate, if required
// Execute both cold & warm
{
0, // ExeFlags
F16KbNbPstateDis // Function Pointer
},
// Step 3 - Core Minimum P-state Transition Sequence After Warm Reset
// Execute only after warm reset
{
PM_EXEFLAGS_WARM_ONLY, // ExeFlags
F16KbPmCoreAfterReset // Function Pointer
},
// Step 4 - NB P-state COF and VID Synchronization After Warm Reset
// Execute only after warm reset
{
PM_EXEFLAGS_WARM_ONLY, // ExeFlags
F16KbPmNbAfterReset // Function Pointer
},
// Step 5 - Power Check
// Execute only after warm reset
{
0, // ExeFlags
F16KbPmPwrCheck // Function Pointer
},
IDS_F16_KB_PM_CUSTOM_STEP
};
/*---------------------------------------------------------------------------------------*/
/**
* Returns the appropriate table of steps to perform to initialize the power management
* subsystem.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] SysPmTblPtr Points to the first entry in the table.
* @param[out] NumberOfElements Number of valid entries in the table.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF16KbSysPmTable (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **SysPmTblPtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
*NumberOfElements = (sizeof (CpuF16KbSysPmTableArray) / sizeof (SYS_PM_TBL_STEP));
*SysPmTblPtr = CpuF16KbSysPmTableArray;
}

278
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPsi.c
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@ -1,278 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_16 Kabini PSI Initialization
*
* Enables Power Status Indicator (PSI) feature
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x16/KB
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuRegisters.h"
#include "cpuF16PowerMgmt.h"
#include "F16KbPowerMgmt.h"
#include "cpuFeatures.h"
#include "cpuServices.h"
#include "GeneralServices.h"
#include "cpuFamilyTranslation.h"
#include "CommonReturns.h"
#include "cpuPsi.h"
#include "Filecode.h"
CODE_GROUP (G2_PEI)
RDATA_GROUP (G2_PEI)
#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBPSI_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
STATIC
F16KbPmVrmLowPowerModeEnable (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN PCI_ADDR PciAddress,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Entry point for enabling Power Status Indicator
*
* This function must be run after all P-State routines have been executed
*
* @param[in] PsiServices The current CPU's family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F16KbInitializePsi (
IN PSI_FAMILY_SERVICES *PsiServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
// Configure PsiVid
F16KbPmVrmLowPowerModeEnable (FamilySpecificServices, PlatformConfig, PciAddress, StdHeader);
}
return AGESA_SUCCESS;
}
/*---------------------------------------------------------------------------------------*/
/**
* Sets up PSI_L operation.
*
* This function implements the LowPowerThreshold parameter.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] PciAddress Segment, bus, device number of the node to transition.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
F16KbPmVrmLowPowerModeEnable (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN PCI_ADDR PciAddress,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PSTATE_MSR PstateMsr;
CLK_PWR_TIMING_CTRL2_REGISTER ClkPwrTimingCtrl2;
POWER_CTRL_MISC_REGISTER PwrCtrlMisc;
UINT32 CoreVrmLowPowerThreshold;
UINT32 Pstate;
UINT32 HwPstateMaxVal;
UINT32 PstateCurrent;
UINT32 NextPstateCurrent;
UINT32 PreviousVid;
UINT32 CurrentVid;
NB_PSTATE_REGISTER NbPstateReg;
NB_PSTATE_CTRL_REGISTER NbPsCtrl;
MISC_VOLTAGE_REGISTER MiscVoltageReg;
UINT32 NbVrmLowPowerThreshold;
UINT32 NbPstate;
UINT32 NbPstateMaxVal;
UINT32 NbPstateCurrent;
UINT32 NextNbPstateCurrent;
UINT32 PreviousNbVid;
UINT32 CurrentNbVid;
IDS_HDT_CONSOLE (CPU_TRACE, " F16KbPmVrmLowPowerModeEnable\n");
if (PlatformConfig->VrmProperties[CoreVrm].LowPowerThreshold != 0) {
// Set up PSI0_L for VDD
CoreVrmLowPowerThreshold = PlatformConfig->VrmProperties[CoreVrm].LowPowerThreshold;
IDS_HDT_CONSOLE (CPU_TRACE, " Core VRM - LowPowerThreshold: %d\n", CoreVrmLowPowerThreshold);
PreviousVid = 0xFF;
CurrentVid = 0xFF;
PciAddress.AddressValue = CPTC2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader);
HwPstateMaxVal = ClkPwrTimingCtrl2.HwPstateMaxVal;
ASSERT (HwPstateMaxVal < NM_PS_REG);
IDS_HDT_CONSOLE (CPU_TRACE, " HwPstateMaxVal %d\n", HwPstateMaxVal);
// Check P-state from P0 to HwPstateMaxVal
for (Pstate = 0; Pstate <= HwPstateMaxVal; Pstate++) {
FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) Pstate, &PstateCurrent, StdHeader);
LibAmdMsrRead ((UINT32) (Pstate + PS_REG_BASE), (UINT64 *) &PstateMsr, StdHeader);
CurrentVid = (UINT32) PstateMsr.CpuVid;
if (Pstate == HwPstateMaxVal) {
NextPstateCurrent = 0;
} else {
// Check P-state from P1 to HwPstateMaxVal
FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) (Pstate + 1), &NextPstateCurrent, StdHeader);
}
if ((PstateCurrent <= CoreVrmLowPowerThreshold) &&
(NextPstateCurrent <= CoreVrmLowPowerThreshold) &&
(CurrentVid != PreviousVid)) {
// Program PsiVid and PsiVidEn if PSI state is found and stop searching.
PciAddress.AddressValue = PW_CTL_MISC_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PwrCtrlMisc, StdHeader);
PwrCtrlMisc.PsiVid = CurrentVid;
PwrCtrlMisc.PsiVidEn = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &PwrCtrlMisc, StdHeader);
IDS_HDT_CONSOLE (CPU_TRACE, " PsiVid is enabled at P-state %d. PsiVid: %d\n", Pstate, CurrentVid);
break;
} else {
PstateCurrent = NextPstateCurrent;
PreviousVid = CurrentVid;
}
}
}
if (PlatformConfig->VrmProperties[NbVrm].LowPowerThreshold != 0) {
// Set up NBPSI0_L for VDDNB
NbVrmLowPowerThreshold = PlatformConfig->VrmProperties[NbVrm].LowPowerThreshold;
IDS_HDT_CONSOLE (CPU_TRACE, " NB VRM - LowPowerThreshold: %d\n", NbVrmLowPowerThreshold);
PreviousNbVid = 0xFF;
CurrentNbVid = 0xFF;
PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
NbPstateMaxVal = NbPsCtrl.NbPstateMaxVal;
ASSERT (NbPstateMaxVal < NM_NB_PS_REG);
IDS_HDT_CONSOLE (CPU_TRACE, " NbPstateMaxVal %d\n", NbPstateMaxVal);
for (NbPstate = 0; NbPstate <= NbPstateMaxVal; NbPstate++) {
// Check only valid NB P-state
if (FamilySpecificServices->GetNbIddMax (FamilySpecificServices, (UINT8) NbPstate, &NbPstateCurrent, StdHeader) != TRUE) {
continue;
}
PciAddress.Address.Register = (NB_PSTATE_0 + (sizeof (NB_PSTATE_REGISTER) * NbPstate));
LibAmdPciRead (AccessWidth32, PciAddress, &NbPstateReg, StdHeader);
CurrentNbVid = (UINT32) GetF16KbNbVid (&NbPstateReg);
if (NbPstate == NbPstateMaxVal) {
NextNbPstateCurrent = 0;
} else {
// Check only valid NB P-state
if (FamilySpecificServices->GetNbIddMax (FamilySpecificServices, (UINT8) (NbPstate + 1), &NextNbPstateCurrent, StdHeader) != TRUE) {
continue;
}
}
if ((NbPstateCurrent <= NbVrmLowPowerThreshold) &&
(NextNbPstateCurrent <= NbVrmLowPowerThreshold) &&
(CurrentNbVid != PreviousNbVid)) {
// Program NbPsi0Vid and NbPsi0VidEn if PSI state is found and stop searching.
PciAddress.AddressValue = MISC_VOLTAGES_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &MiscVoltageReg, StdHeader);
MiscVoltageReg.NbPsi0Vid = CurrentNbVid;
MiscVoltageReg.NbPsi0VidEn = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &MiscVoltageReg, StdHeader);
IDS_HDT_CONSOLE (CPU_TRACE, " NbPsi0Vid is enabled at NB P-state %d. NbPsi0Vid: %d\n", NbPstate, CurrentNbVid);
break;
} else {
PreviousNbVid = CurrentNbVid;
}
}
}
}
CONST PSI_FAMILY_SERVICES ROMDATA F16KbPsiSupport =
{
0,
(PF_PSI_IS_SUPPORTED) CommonReturnTrue,
F16KbInitializePsi
};

613
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPstate.c
View File

@ -1,613 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_16 Kabini Pstate feature support functions.
*
* Provides the functions necessary to initialize the Pstate feature.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x16/KB
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "GeneralServices.h"
#include "cpuPstateTables.h"
#include "cpuRegisters.h"
#include "Table.h"
#include "cpuFamilyTranslation.h"
#include "cpuFamRegisters.h"
#include "cpuF16Utilities.h"
#include "F16KbUtilities.h"
#include "cpuF16PowerMgmt.h"
#include "F16KbPowerMgmt.h"
#include "CommonReturns.h"
#include "Filecode.h"
CODE_GROUP (G3_DXE)
RDATA_GROUP (G3_DXE)
#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBPSTATE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
STATIC
F16KbGetPowerStepValueInTime (
IN OUT UINT32 *PowerStepPtr
);
VOID
STATIC
F16KbGetPllValueInTime (
IN OUT UINT32 *PllLockTimePtr
);
AGESA_STATUS
F16KbGetPstateTransLatency (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN PSTATE_LEVELING *PStateLevelingBufferStructPtr,
IN PCI_ADDR *PciAddress,
OUT UINT32 *TransitionLatency,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F16KbGetPstateFrequency (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN UINT8 StateNumber,
OUT UINT32 *FrequencyInMHz,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F16KbGetPstatePower (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN UINT8 StateNumber,
OUT UINT32 *PowerInMw,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F16KbGetPstateMaxState (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
OUT UINT32 *MaxPStateNumber,
OUT UINT8 *NumberOfBoostStates,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F16KbGetPstateRegisterInfo (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN UINT32 PState,
OUT BOOLEAN *PStateEnabled,
IN OUT UINT32 *IddVal,
IN OUT UINT32 *IddDiv,
OUT UINT32 *SwPstateNumber,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Family specific call to check if Pstate PSD is dependent.
*
* @param[in] PstateCpuServices Pstate CPU services.
* @param[in,out] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @retval TRUE PSD is dependent.
* @retval FALSE PSD is independent.
*
*/
BOOLEAN
STATIC
F16KbIsPstatePsdDependent (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN OUT PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
IDS_HDT_CONSOLE (CPU_TRACE, " F16KbIsPstatePsdDependent\n");
// Family 16h KB defaults to independent PSD
IDS_HDT_CONSOLE (CPU_TRACE, " P-state PSD is independent.\n");
return FALSE;
}
/*---------------------------------------------------------------------------------------*/
/**
* Family specific call to get Pstate Transition Latency.
*
* Calculate TransitionLatency by power step value and pll value.
*
* @param[in] PstateCpuServices Pstate CPU services.
* @param[in] PStateLevelingBufferStructPtr Pstate row data buffer pointer
* @param[in] PciAddress Pci address
* @param[out] TransitionLatency The transition latency.
* @param[in] StdHeader Header for library and services
*
* @retval AGESA_SUCCESS Always succeeds.
*/
AGESA_STATUS
F16KbGetPstateTransLatency (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN PSTATE_LEVELING *PStateLevelingBufferStructPtr,
IN PCI_ADDR *PciAddress,
OUT UINT32 *TransitionLatency,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 CpuFid;
UINT32 HwP0CpuFid;
UINT32 PowerStepDown;
UINT32 PowerStepUp;
UINT32 PllLockTime;
UINT32 LocalPciRegister;
UINT32 k;
UINT32 PStateMaxValueOnCurrentCore;
UINT32 TransAndBusMastLatency;
UINT64 MsrData;
BOOLEAN CpuFidSameFlag;
IDS_HDT_CONSOLE (CPU_TRACE, " F16KbGetPstateTransLatency\n");
CpuFidSameFlag = TRUE;
HwP0CpuFid = 0;
// Get PStateMaxValue
PciAddress->Address.Register = CPTC2_REG;
PciAddress->Address.Function = FUNC_3;
LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
PStateMaxValueOnCurrentCore = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->HwPstateMaxVal;
//
//Check if MSRC001_00[6B:64][CpuFid] is the same value for all P-states
//
for (k = 0; k <= PStateMaxValueOnCurrentCore; k++) {
LibAmdMsrRead ((MSR_PSTATE_0 + k), &MsrData, StdHeader);
CpuFid = (UINT32) (((PSTATE_MSR *) &MsrData)->CpuFid);
if (k == 0) {
HwP0CpuFid = CpuFid;
}
if (HwP0CpuFid != CpuFid) {
CpuFidSameFlag = FALSE;
break;
}
}
PciAddress->Address.Register = CPTC0_REG;
PciAddress->Address.Function = FUNC_3;
LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
// PowerStepDown - Bits 20:23
PowerStepDown = ((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->PowerStepDown;
// PowerStepUp - Bits 24:27
PowerStepUp = ((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->PowerStepUp;
// Convert the raw numbers in TempVar8_a and TempVar8_b into time
F16KbGetPowerStepValueInTime (&PowerStepDown);
F16KbGetPowerStepValueInTime (&PowerStepUp);
//
//(15 * (F3xD4[PowerStepDown] + F3xD4[PowerStepUp]) /1000) us
//
TransAndBusMastLatency =
(15 * (PowerStepDown + PowerStepUp) + 999) / 1000;
if (!CpuFidSameFlag) {
//
//+ F3xA0[PllLockTime]
//
PciAddress->Address.Register = PW_CTL_MISC_REG;
LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
PllLockTime = ((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->PllLockTime;
F16KbGetPllValueInTime (&PllLockTime);
TransAndBusMastLatency += PllLockTime;
}
*TransitionLatency = TransAndBusMastLatency;
return (AGESA_SUCCESS);
}
/*---------------------------------------------------------------------------------------*/
/**
* Family specific call to calculates the frequency in megahertz of the desired P-state.
*
* @param[in] PstateCpuServices Pstate CPU services.
* @param[in] StateNumber The P-State to analyze.
* @param[out] FrequencyInMHz The P-State's frequency in MegaHertz
* @param[in] StdHeader Header for library and services
*
* @retval AGESA_SUCCESS Always Succeeds.
*/
AGESA_STATUS
F16KbGetPstateFrequency (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN UINT8 StateNumber,
OUT UINT32 *FrequencyInMHz,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 TempValue;
UINT32 CpuDid;
UINT32 CpuFid;
UINT64 LocalMsrRegister;
PCI_ADDR PciAddress;
HTC_REGISTER HtcReg;
CLK_PWR_TIMING_CTRL2_REGISTER ClkPwrTimingCtrl2;
IDS_HDT_CONSOLE (CPU_TRACE, " F16KbGetPstateFrequency - P%d\n", StateNumber);
PciAddress.AddressValue = CPTC2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader);
PciAddress.AddressValue = HTC_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader);
ASSERT ((StateNumber <= ClkPwrTimingCtrl2.HwPstateMaxVal) || ((StateNumber == HtcReg.HtcPstateLimit)));
LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader);
CpuDid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuDid);
CpuFid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuFid);
switch (CpuDid) {
case 0:
TempValue = 1;
break;
case 1:
TempValue = 2;
break;
case 2:
TempValue = 4;
break;
case 3:
TempValue = 8;
break;
case 4:
TempValue = 16;
break;
default:
// CpuDid is set to an undefined value. This is due to either a misfused CPU, or
// an invalid P-state MSR write.
ASSERT (FALSE);
TempValue = 1;
break;
}
*FrequencyInMHz = (100 * (CpuFid + 0x10) / TempValue);
IDS_HDT_CONSOLE (CPU_TRACE, " FrequencyInMHz=%d, CpuFid=%d, CpuDid=%d\n", *FrequencyInMHz, CpuFid, CpuDid);
return (AGESA_SUCCESS);
}
/*---------------------------------------------------------------------------------------*/
/**
* Family specific call to calculates the power in milliWatts of the desired P-state.
*
* @param[in] PstateCpuServices Pstate CPU services.
* @param[in] StateNumber Which P-state to analyze
* @param[out] PowerInMw The Power in milliWatts of that P-State
* @param[in] StdHeader Header for library and services
*
* @retval AGESA_SUCCESS Always succeeds.
*/
AGESA_STATUS
F16KbGetPstatePower (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN UINT8 StateNumber,
OUT UINT32 *PowerInMw,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 CpuVid;
UINT32 IddValue;
UINT32 IddDiv;
UINT32 V_x100000;
UINT32 Power;
UINT64 LocalMsrRegister;
IDS_HDT_CONSOLE (CPU_TRACE, " F16KbGetPstatePower - P%d\n", StateNumber);
ASSERT (StateNumber < NM_PS_REG);
LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader);
ASSERT (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1);
CpuVid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuVid);
IddValue = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->IddValue);
IddDiv = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->IddDiv);
if (CpuVid >= 0xF8) {
V_x100000 = 0;
} else {
V_x100000 = 155000L - (625L * CpuVid);
}
Power = V_x100000 * IddValue;
switch (IddDiv) {
case 0:
*PowerInMw = Power / 100L;
break;
case 1:
*PowerInMw = Power / 1000L;
break;
case 2:
*PowerInMw = Power / 10000L;
break;
default:
// IddDiv is set to an undefined value. This is due to either a misfused CPU, or
// an invalid P-state MSR write.
ASSERT (FALSE);
*PowerInMw = 0;
break;
}
IDS_HDT_CONSOLE (CPU_TRACE, " PowerInMw=%d, CpuVid=%d, IddValue=%d, IddDiv=%d\n", *PowerInMw, CpuVid, IddValue, IddDiv);
return (AGESA_SUCCESS);
}
/*---------------------------------------------------------------------------------------*/
/**
* Family specific call to get CPU pstate max state.
*
* @param[in] PstateCpuServices Pstate CPU services.
* @param[out] MaxPStateNumber The max hw pstate value on the current socket.
* @param[out] NumberOfBoostStates The number of boosted P-states on the current socket.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*/
AGESA_STATUS
F16KbGetPstateMaxState (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
OUT UINT32 *MaxPStateNumber,
OUT UINT8 *NumberOfBoostStates,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 NumBoostStates;
UINT64 MsrValue;
UINT32 LocalPciRegister;
PCI_ADDR PciAddress;
IDS_HDT_CONSOLE (CPU_TRACE, " F16KbGetPstateMaxState\n");
LocalPciRegister = 0;
// For F16 Kabini CPU, skip boosted p-state. The boosted p-state number = F4x15C[NumBoostStates].
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F4x15C
NumBoostStates = ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates;
*NumberOfBoostStates = (UINT8) NumBoostStates;
//
// Read PstateMaxVal [6:4] from MSR C001_0061
// So, we will know the max pstate state in this socket.
//
LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrValue, StdHeader);
*MaxPStateNumber = (UINT32) (((PSTATE_CURLIM_MSR *) &MsrValue)->PstateMaxVal) + NumBoostStates;
IDS_HDT_CONSOLE (CPU_TRACE, " MaxPStateNumber=%d, NumBoostStates=%d\n", *MaxPStateNumber, NumBoostStates);
return (AGESA_SUCCESS);
}
/*---------------------------------------------------------------------------------------*/
/**
* Family specific call to get CPU pstate register information.
*
* @param[in] PstateCpuServices Pstate CPU services.
* @param[in] PState Input Pstate number for query.
* @param[out] PStateEnabled Boolean flag return pstate enable.
* @param[in,out] IddVal Pstate current value.
* @param[in,out] IddDiv Pstate current divisor.
* @param[out] SwPstateNumber Software P-state number.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*/
AGESA_STATUS
F16KbGetPstateRegisterInfo (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN UINT32 PState,
OUT BOOLEAN *PStateEnabled,
IN OUT UINT32 *IddVal,
IN OUT UINT32 *IddDiv,
OUT UINT32 *SwPstateNumber,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 LocalPciRegister;
UINT64 LocalMsrRegister;
PCI_ADDR PciAddress;
IDS_HDT_CONSOLE (CPU_TRACE, " F16KbGetPstateRegisterInfo - P%d\n", PState);
ASSERT (PState < NM_PS_REG);
// For F16 Kabini CPU, skip boosted p-state. The boosted p-state number = F4x15C[NumBoostStates].
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F4x15C
// Read PSTATE MSRs
LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &LocalMsrRegister, StdHeader);
*SwPstateNumber = PState;
if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
// PState enable = bit 63
*PStateEnabled = TRUE;
//
// Check input pstate belongs to Boosted-Pstate, if yes, return *PStateEnabled = FALSE.
//
if (PState < ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates) {
*PStateEnabled = FALSE;
} else {
*SwPstateNumber = PState - ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates;
}
IDS_HDT_CONSOLE (CPU_TRACE, " Pstate %d is enabled. SwPstateNumber=%d\n", PState, *SwPstateNumber);
} else {
*PStateEnabled = FALSE;
}
// Bits 39:32 (high 32 bits [7:0])
*IddVal = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->IddValue;
// Bits 41:40 (high 32 bits [9:8])
*IddDiv = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->IddDiv;
IDS_HDT_CONSOLE (CPU_TRACE, " IddVal=%d, IddDiv=%d\n", *IddVal, *IddDiv);
return (AGESA_SUCCESS);
}
CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F16KbPstateServices =
{
0,
(PF_PSTATE_PSD_IS_NEEDED) CommonReturnTrue,
F16KbIsPstatePsdDependent,
F16KbGetPstateTransLatency,
F16KbGetPstateFrequency,
(PF_CPU_SET_PSTATE_LEVELING_REG) CommonReturnAgesaSuccess,
F16KbGetPstatePower,
F16KbGetPstateMaxState,
F16KbGetPstateRegisterInfo
};
/*---------------------------------------------------------------------------------------
* L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------
*/
/**
*---------------------------------------------------------------------------------------
*
* F16KbGetPowerStepValueInTime
*
* Description:
* Convert power step value in time
*
* Parameters:
* @param[out] *PowerStepPtr
*
* @retval VOID
*
*---------------------------------------------------------------------------------------
**/
VOID
STATIC
F16KbGetPowerStepValueInTime (
IN OUT UINT32 *PowerStepPtr
)
{
UINT32 TempVar_a;
IDS_HDT_CONSOLE (CPU_TRACE, " F16KbGetPowerStepValueInTime\n");
TempVar_a = *PowerStepPtr;
if (TempVar_a < 0x4) {
*PowerStepPtr = 400 - (TempVar_a * 100);
} else if (TempVar_a < 0x9) {
*PowerStepPtr = 130 - (TempVar_a * 10);
} else {
*PowerStepPtr = 90 - (TempVar_a * 5);
}
IDS_HDT_CONSOLE (CPU_TRACE, " PowerStepPtr=%d\n", *PowerStepPtr);
}
/**
*---------------------------------------------------------------------------------------
*
* F16KbGetPllValueInTime
*
* Description:
* Convert PLL Value in time
*
* Parameters:
* @param[out] *PllLockTimePtr
*
* @retval VOID
*
*---------------------------------------------------------------------------------------
**/
VOID
STATIC
F16KbGetPllValueInTime (
IN OUT UINT32 *PllLockTimePtr
)
{
IDS_HDT_CONSOLE (CPU_TRACE, " F16KbGetPllValueInTime\n");
if (*PllLockTimePtr < 4) {
*PllLockTimePtr = *PllLockTimePtr + 1;
} else if (*PllLockTimePtr == 4) {
*PllLockTimePtr = 8;
} else if (*PllLockTimePtr == 5) {
*PllLockTimePtr = 16;
} else
*PllLockTimePtr = 0;
IDS_HDT_CONSOLE (CPU_TRACE, " PllLockTimePtr=%d\n", *PllLockTimePtr);
}

112
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbSharedMsrTable.c
View File

@ -1,112 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_16 Kabini Shared MSR table with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x16/KB
* @e \$Revision: 86705 $ @e \$Date: 2013-01-24 17:34:21 -0600 (Thu, 24 Jan 2013) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuRegisters.h"
#include "Table.h"
#include "Filecode.h"
CODE_GROUP (G3_DXE)
RDATA_GROUP (G3_DXE)
#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBSHAREDMSRTABLE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
// M S R T a b l e s
// ----------------------
STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F16KbSharedMsrRegisters[] =
{
// When there's a entry, change the number of entries below from 0 to (sizeof (F16KbSharedMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS))
{0},
};
// Shared MSRs with Special Programming Requirements Table
// ----------------------
STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F16KbSharedMsrWorkarounds[] =
{
// When there's a entry, change the number of entries below from 0 to (sizeof (F16KbSharedMsrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS))
{0},
};
CONST REGISTER_TABLE ROMDATA F16KbSharedMsrRegisterTable = {
ComputeUnitPrimary,
PERFORM_TP_AFTER_AP_LAUNCH,
0,
//(sizeof (F16KbSharedMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
(TABLE_ENTRY_FIELDS *) &F16KbSharedMsrRegisters,
};
CONST REGISTER_TABLE ROMDATA F16KbSharedMsrWorkaroundTable = {
ComputeUnitPrimary,
PERFORM_TP_AFTER_AP_LAUNCH,
0,
//(sizeof (F16KbSharedMsrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)),
(TABLE_ENTRY_FIELDS *) &F16KbSharedMsrWorkarounds,
};

1017
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.c
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File diff suppressed because it is too large Load Diff

152
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.h
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@ -1,152 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_16 Kabini specific utility functions.
*
* Provides numerous utility functions specific to family 16h Kabini.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x16/KB
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _F16_KB_UTILITES_H_
#define _F16_KB_UTILITES_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
#define FOUR_CORE_COMPUTE_UNIT_BITMAP 0xF
#define FOUR_CORE_COMPUTE_UNIT_BITWIDTH 0x4
#define ALL_CORES_DISABLE_BITMAP 0xFFFFFFFFul
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
UINT8
F16KbGetNumberOfPhysicalCores (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
F16KbGetApMailboxFromHardware (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT AP_MAILBOXES *ApMailboxInfo,
IN AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
F16KbIsNbPstateEnabled (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
F16KbNbPstateDis (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
F16KbGetProcIddMax (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT8 Pstate,
OUT UINT32 *ProcIddMax,
IN AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
F16KbGetNbIddMax (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT8 NbPstate,
OUT UINT32 *NbIddMax,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F16KbGetCurrentNbFrequency (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT UINT32 *FrequencyInMHz,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F16KbGetMinMaxNbFrequency (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN PCI_ADDR *PciAddress,
OUT UINT32 *var3,
OUT UINT32 *MaxFreqInMHz,
IN AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
F16KbGetNbPstateInfo (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN PCI_ADDR *PciAddress,
IN UINT32 NbPstate,
OUT UINT32 *FreqNumeratorInMHz,
OUT UINT32 *FreqDivisor,
OUT UINT32 *VoltageInuV,
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT32
F16KbGetApCoreNumber (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _F16_KB_UTILITES_H_

21
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/Makefile.inc
View File

@ -1,21 +0,0 @@
libagesa-y += F16KbC6State.c
libagesa-y += F16KbCacheFlushOnHalt.c
libagesa-y += F16KbCoreAfterReset.c
libagesa-y += F16KbCpb.c
libagesa-y += F16KbDmi.c
libagesa-y += F16KbEquivalenceTable.c
libagesa-y += F16KbHtc.c
libagesa-y += F16KbId7001MicrocodePatch.c
libagesa-y += F16KbInitEarlyTable.c
libagesa-y += F16KbIoCstate.c
libagesa-y += F16KbLogicalIdTables.c
libagesa-y += F16KbMicrocodePatchTables.c
libagesa-y += F16KbMsrTables.c
libagesa-y += F16KbNbAfterReset.c
libagesa-y += F16KbPciTables.c
libagesa-y += F16KbPowerCheck.c
libagesa-y += F16KbPowerMgmtSystemTables.c
libagesa-y += F16KbPsi.c
libagesa-y += F16KbPstate.c
libagesa-y += F16KbSharedMsrTable.c
libagesa-y += F16KbUtilities.c

9
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/Makefile.inc
View File

@ -1,9 +0,0 @@
libagesa-y += cpuF16Apm.c
libagesa-y += cpuF16BrandId.c
libagesa-y += cpuF16CacheDefaults.c
libagesa-y += cpuF16Dmi.c
libagesa-y += cpuF16MmioMap.c
libagesa-y += cpuF16MsrUnknownTables.c
libagesa-y += cpuF16PciUnknownTables.c
libagesa-y += cpuF16Utilities.c
libagesa-y += cpuF16WheaInitDataTables.c

124
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Apm.c
View File

@ -1,124 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_16 APM Initialization
*
* Enables Application Power Management feature
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x16
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "GeneralServices.h"
#include "cpuServices.h"
#include "cpuRegisters.h"
#include "cpuFamilyTranslation.h"
#include "cpuF16PowerMgmt.h"
#include "CommonReturns.h"
#include "cpuApm.h"
#include "OptionMultiSocket.h"
#include "Filecode.h"
CODE_GROUP (G3_DXE)
RDATA_GROUP (G3_DXE)
#define FILECODE PROC_CPU_FAMILY_0X16_CPUF16APM_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Entry point for enabling Application Power Management
*
* This function must be run after all P-State routines have been executed
*
* @param[in] ApmServices The current CPU's family services.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
STATIC AGESA_STATUS
F16InitializeApm (
IN APM_FAMILY_SERVICES *ApmServices,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
F16_CPB_CTRL_REGISTER CpbControl;
PCI_ADDR PciAddress;
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
if (CpbControl.NumBoostStates == 0) {
CpbControl.ApmMasterEn = 0;
} else {
CpbControl.ApmMasterEn = 1;
}
LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader);
return AGESA_SUCCESS;
}
CONST APM_FAMILY_SERVICES ROMDATA F16ApmSupport =
{
0,
(PF_APM_IS_SUPPORTED) CommonReturnTrue,
F16InitializeApm
};

166
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16BrandId.c
View File

@ -1,166 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD CPU BrandId related functions and structures.
*
* Contains code that provides CPU BrandId information
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x16
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuRegisters.h"
#include "cpuFamilyTranslation.h"
#include "cpuEarlyInit.h"
#include "GeneralServices.h"
#include "Filecode.h"
CODE_GROUP (G3_DXE)
RDATA_GROUP (G3_DXE)
#define FILECODE PROC_CPU_FAMILY_0X16_CPUF16BRANDID_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
#define NAME_STRING_ADDRESS_PORT 0x194
#define NAME_STRING_DATA_PORT 0x198
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/// FAM16_BRAND_STRING_MSR
typedef struct _PROCESSOR_NAME_STRING {
UINT32 lo; ///< lower 32-bits of 64-bit value
UINT32 hi; ///< highest 32-bits of 64-bit value
} PROCESSOR_NAME_STRING;
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
F16SetBrandIdRegistersAtEarly (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
CONST CHAR8 ROMDATA str_Unprogrammed_Sample[48] = "AMD Unprogrammed Engineering Sample";
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Set the Processor Name String register based on F5x194/198
*
* This function copies F5x198_x[B:0] to MSR_C001_00[35:30]
*
* @param[in] FamilyServices The current Family Specific Services.
* @param[in] EarlyParams Service parameters.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F16SetBrandIdRegistersAtEarly (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 PciData;
UINT32 MsrIndex;
UINT64 MsrData;
UINT64 *MsrNameStringPtrPtr;
PCI_ADDR PciAddress;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, FUNC_5, 0);
PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT;
// check if D18F5x198_x0 is 00000000h.
PciData = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
PciAddress.Address.Register = NAME_STRING_DATA_PORT;
LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
if (PciData != 0) {
for (MsrIndex = 0; MsrIndex <= (MSR_CPUID_NAME_STRING5 - MSR_CPUID_NAME_STRING0); MsrIndex++) {
PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT;
PciData = MsrIndex * 2;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
PciAddress.Address.Register = NAME_STRING_DATA_PORT;
LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
((PROCESSOR_NAME_STRING *) (&MsrData))->lo = PciData;
PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT;
PciData = (MsrIndex * 2) + 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
PciAddress.Address.Register = NAME_STRING_DATA_PORT;
LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
((PROCESSOR_NAME_STRING *) (&MsrData))->hi = PciData;
LibAmdMsrWrite ((MsrIndex + MSR_CPUID_NAME_STRING0), &MsrData, StdHeader);
}
} else {
// It is unprogrammed (unfused) parts and use a name string of "AMD Unprogrammed Engineering Sample"
MsrNameStringPtrPtr = (UINT64 *) str_Unprogrammed_Sample;
// Put values into name MSRs, Always write the full 48 bytes
for (MsrIndex = MSR_CPUID_NAME_STRING0; MsrIndex <= MSR_CPUID_NAME_STRING5; MsrIndex++) {
LibAmdMsrWrite (MsrIndex, MsrNameStringPtrPtr, StdHeader);
MsrNameStringPtrPtr++;
}
}
return;
}
/*---------------------------------------------------------------------------------------
* L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------
*/

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