We call this cache as ram everywhere, so let's call it the same in Kconfig

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5756 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/console/Makefile.inc

@@ -7,7 +7,7 @@ smmobj-y += printk.o
 smmobj-y += vtxprintf.o
 
 initobj-y += vtxprintf.o
-initobj-$(CONFIG_USE_DCACHE_RAM) += console.o
+initobj-$(CONFIG_CACHE_AS_RAM) += console.o
 
 driver-$(CONFIG_CONSOLE_SERIAL8250) += uart8250_console.o
 driver-$(CONFIG_USBDEBUG) += usbdebug_console.o

src/cpu/Kconfig

@@ -3,7 +3,7 @@ source src/cpu/intel/Kconfig
 source src/cpu/via/Kconfig
 source src/cpu/x86/Kconfig
 
-config USE_DCACHE_RAM
+config CACHE_AS_RAM
 	bool
 	default !ROMCC
 

src/cpu/amd/model_10xxx/Kconfig

@@ -1,6 +1,6 @@
 config CPU_AMD_MODEL_10XXX
 	bool
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select SSE
 	select SSE2
 

src/cpu/amd/model_fxx/Kconfig

@@ -1,6 +1,6 @@
 config CPU_AMD_MODEL_FXX
 	bool
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select MMX
 	select SSE
 	select SSE2

src/cpu/amd/model_gx2/syspreinit.c

@@ -16,7 +16,7 @@ static void StartTimer1(void)
 void SystemPreInit(void)
 {
 	/* they want a jump ... */
-#ifndef CONFIG_USE_DCACHE_RAM
+#ifndef CONFIG_CACHE_AS_RAM
 	__asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n");
 #endif
 	StartTimer1();

src/cpu/amd/model_lx/syspreinit.c

@@ -39,7 +39,7 @@ void SystemPreInit(void)
 {
 
 	/* they want a jump ... */
-#ifndef CONFIG_USE_DCACHE_RAM
+#ifndef CONFIG_CACHE_AS_RAM
 	__asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n");
 #endif
 	StartTimer1();

src/cpu/intel/socket_FC_PGA370/Kconfig

@@ -23,7 +23,7 @@ config CPU_INTEL_SOCKET_FC_PGA370
 	select CPU_INTEL_MODEL_68X
 	select MMX
 	select SSE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select TINY_BOOTBLOCK
 
 config DCACHE_RAM_BASE

src/cpu/x86/mtrr/earlymtrr.c

@@ -62,7 +62,7 @@ static inline void cache_lbmem(int type)
 	enable_cache();
 }
 
-#if !defined(CONFIG_USE_DCACHE_RAM) || (CONFIG_USE_DCACHE_RAM == 0)
+#if !defined(CONFIG_CACHE_AS_RAM) || (CONFIG_CACHE_AS_RAM == 0)
 /* the fixed and variable MTTRs are power-up with random values,
  * clear them to MTRR_TYPE_UNCACHEABLE for safty.
  */

src/include/assert.h

@@ -20,7 +20,7 @@
 #ifndef __ASSERT_H__
 #define __ASSERT_H__
 
-#if defined(__PRE_RAM__) && !CONFIG_USE_DCACHE_RAM
+#if defined(__PRE_RAM__) && !CONFIG_CACHE_AS_RAM
 
 /* ROMCC versions */
 #define ASSERT(x) {						\

src/include/cpu/x86/bist.h

@@ -4,7 +4,7 @@
 static void report_bist_failure(u32 bist)
 {
 	if (bist != 0) {
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
                 printk(BIOS_EMERG, "BIST failed: %08x", bist);
 #else
 		print_emerg("BIST failed: ");

src/lib/generic_sdram.c

@@ -6,7 +6,7 @@
 
 static inline void print_debug_sdram_8(const char *strval, uint32_t val)
 {
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
         printk(BIOS_DEBUG, "%s%02x\n", strval, val);
 #else
         print_debug(strval); print_debug_hex8(val); print_debug("\n");

src/lib/ramtest.c

@@ -51,7 +51,7 @@ static void ram_fill(unsigned long start, unsigned long stop)
 	/*
 	 * Fill.
 	 */
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
 	printk(BIOS_DEBUG, "DRAM fill: 0x%08lx-0x%08lx\n", start, stop);
 #else
 	print_debug("DRAM fill: ");
@@ -63,7 +63,7 @@ static void ram_fill(unsigned long start, unsigned long stop)
 	for(addr = start; addr < stop ; addr += 4) {
 		/* Display address being filled */
 		if (!(addr & 0xfffff)) {
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
 			printk(BIOS_DEBUG, "%08lx \r", addr);
 #else
 			print_debug_hex32(addr);
@@ -73,7 +73,7 @@ static void ram_fill(unsigned long start, unsigned long stop)
 		write_phys(addr, (u32)addr);
 	};
 	/* Display final address */
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
 	printk(BIOS_DEBUG, "%08lx\nDRAM filled\n", addr);
 #else
 	print_debug_hex32(addr);
@@ -88,7 +88,7 @@ static void ram_verify(unsigned long start, unsigned long stop)
 	/*
 	 * Verify.
 	 */
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
 	printk(BIOS_DEBUG, "DRAM verify: 0x%08lx-0x%08lx\n", start, stop);
 #else
 	print_debug("DRAM verify: ");
@@ -101,7 +101,7 @@ static void ram_verify(unsigned long start, unsigned long stop)
 		unsigned long value;
 		/* Display address being tested */
 		if (!(addr & 0xfffff)) {
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
 			printk(BIOS_DEBUG, "%08lx \r", addr);
 #else
 			print_debug_hex32(addr);
@@ -111,7 +111,7 @@ static void ram_verify(unsigned long start, unsigned long stop)
 		value = read_phys(addr);
 		if (value != addr) {
 			/* Display address with error */
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
 			printk(BIOS_ERR, "Fail: @0x%08lx Read value=0x%08lx\n", addr, value);
 #else
 			print_err("Fail: @0x");
@@ -122,7 +122,7 @@ static void ram_verify(unsigned long start, unsigned long stop)
 #endif
 			i++;
 			if(i>256) {
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
 				printk(BIOS_DEBUG, "Aborting.\n");
 #else
 				print_debug("Aborting.\n");
@@ -132,14 +132,14 @@ static void ram_verify(unsigned long start, unsigned long stop)
 		}
 	}
 	/* Display final address */
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
 	printk(BIOS_DEBUG, "%08lx", addr);
 #else
 	print_debug_hex32(addr);
 #endif
 
 	if (i) {
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
 		printk(BIOS_DEBUG, "\nDRAM did _NOT_ verify!\n");
 #else
 		print_debug("\nDRAM did _NOT_ verify!\n");
@@ -147,7 +147,7 @@ static void ram_verify(unsigned long start, unsigned long stop)
 		die("DRAM ERROR");
 	}
 	else {
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
 		printk(BIOS_DEBUG, "\nDRAM range verified.\n");
 #else
 		print_debug("\nDRAM range verified.\n");
@@ -163,7 +163,7 @@ void ram_check(unsigned long start, unsigned long stop)
 	 * test than a "Is my DRAM faulty?" test.  Not all bits
 	 * are tested.   -Tyson
 	 */
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
 	printk(BIOS_DEBUG, "Testing DRAM : %08lx - %08lx\n", start, stop);
 #else
 	print_debug("Testing DRAM : ");
@@ -176,7 +176,7 @@ void ram_check(unsigned long start, unsigned long stop)
 	/* Make sure we don't read before we wrote */
 	phys_memory_barrier();
 	ram_verify(start, stop);
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
 	printk(BIOS_DEBUG, "Done.\n");
 #else
 	print_debug("Done.\n");

src/lib/usbdebug.c

@@ -22,7 +22,7 @@
 #if !defined(__ROMCC__)
 #include <console/console.h>
 #else
-#if CONFIG_USE_DCACHE_RAM==0
+#if CONFIG_CACHE_AS_RAM==0
 #define printk(BIOS_DEBUG, fmt, arg...)   do {} while(0)
 #endif
 #endif

src/mainboard/amd/db800/Kconfig

@@ -10,7 +10,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
 	select UDELAY_TSC
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select BOARD_ROMSIZE_KB_256
 
 config MAINBOARD_DIR

src/mainboard/amd/dbm690t/Kconfig

@@ -16,7 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_MAINBOARD_RESOURCES
 	select HAVE_BUS_CONFIG
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select BOARD_ROMSIZE_KB_1024

src/mainboard/amd/mahogany/Kconfig

@@ -17,7 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_MAINBOARD_RESOURCES
 	select HAVE_BUS_CONFIG
 	select LIFT_BSP_APIC_ID
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select BOARD_ROMSIZE_KB_1024

src/mainboard/amd/mahogany_fam10/Kconfig

@@ -14,7 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select GENERATE_PIRQ_TABLE
 	select GENERATE_MP_TABLE
 	select HAVE_MAINBOARD_RESOURCES
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select LIFT_BSP_APIC_ID

src/mainboard/amd/norwich/Kconfig

@@ -9,7 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
 	select UDELAY_TSC
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select BOARD_ROMSIZE_KB_256
 
 config MAINBOARD_DIR

src/mainboard/amd/pistachio/Kconfig

@@ -13,7 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select WAIT_BEFORE_CPUS_INIT

src/mainboard/amd/rumba/Kconfig

@@ -25,7 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_AMD_GX2
 	select SOUTHBRIDGE_AMD_CS5536
 	select UDELAY_TSC
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_PIRQ_TABLE
 	select BOARD_ROMSIZE_KB_256
 

src/mainboard/amd/serengeti_cheetah/Kconfig

@@ -14,7 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select LIFT_BSP_APIC_ID
 	#select AP_CODE_IN_CAR

src/mainboard/amd/serengeti_cheetah_fam10/Kconfig

@@ -13,7 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select SERIAL_CPU_INIT

src/mainboard/amd/tilapia_fam10/Kconfig

@@ -14,7 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select GENERATE_PIRQ_TABLE
 	select GENERATE_MP_TABLE
 	select HAVE_MAINBOARD_RESOURCES
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select LIFT_BSP_APIC_ID

src/mainboard/arima/hdama/Kconfig

@@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select HAVE_OPTION_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select BOARD_ROMSIZE_KB_512

src/mainboard/artecgroup/dbe61/Kconfig

@@ -9,7 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
 	select UDELAY_TSC
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select BOARD_ROMSIZE_KB_256
 
 config MAINBOARD_DIR

src/mainboard/asrock/939a785gmh/Kconfig

@@ -18,7 +18,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_BUS_CONFIG
 	select LIFT_BSP_APIC_ID
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select BOARD_ROMSIZE_KB_1024

src/mainboard/asus/a8n_e/Kconfig

@@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select BOARD_ROMSIZE_KB_512
 

src/mainboard/asus/a8v-e_se/Kconfig

@@ -10,7 +10,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select SOUTHBRIDGE_VIA_VT8237R
 	select SOUTHBRIDGE_VIA_K8T890
 	select SUPERIO_WINBOND_W83627EHG
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_OPTION_TABLE
 	select HAVE_ACPI_TABLES
 	select HAVE_MP_TABLE

src/mainboard/asus/m2v-mx_se/Kconfig

@@ -27,7 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select SOUTHBRIDGE_VIA_VT8237R
 	select SOUTHBRIDGE_VIA_K8M890
 	select SUPERIO_ITE_IT8712F
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_OPTION_TABLE
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_512

src/mainboard/broadcom/blast/Kconfig

@@ -13,7 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select BOARD_ROMSIZE_KB_512
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY

src/mainboard/digitallogic/adl855pc/Kconfig

@@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select HAVE_HARD_RESET
 	select BOARD_ROMSIZE_KB_1024
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select TINY_BOOTBLOCK
 
 config MAINBOARD_DIR

src/mainboard/digitallogic/msm800sev/Kconfig

@@ -10,7 +10,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
 	select UDELAY_TSC
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select BOARD_ROMSIZE_KB_256
 
 config MAINBOARD_DIR

src/mainboard/getac/p470/Kconfig

@@ -42,7 +42,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select UDELAY_LAPIC
 	select HAVE_SMI_HANDLER
 	select BOARD_ROMSIZE_KB_1024
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select GFXUMA
 	select TINY_BOOTBLOCK
 

src/mainboard/gigabyte/ga_2761gxdk/Kconfig

@@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_BUS_CONFIG
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select LIFT_BSP_APIC_ID
 	select K8_REV_F_SUPPORT

src/mainboard/gigabyte/m57sli/Kconfig

@@ -13,7 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select LIFT_BSP_APIC_ID
 	select HAVE_ACPI_TABLES

src/mainboard/gigabyte/ma785gmt/Kconfig

@@ -14,7 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select GENERATE_PIRQ_TABLE
 	select GENERATE_MP_TABLE
 	select HAVE_MAINBOARD_RESOURCES
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select LIFT_BSP_APIC_ID

src/mainboard/gigabyte/ma78gm/Kconfig

@@ -14,7 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select GENERATE_PIRQ_TABLE
 	select GENERATE_MP_TABLE
 	select HAVE_MAINBOARD_RESOURCES
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select LIFT_BSP_APIC_ID

src/mainboard/hp/dl145_g3/Kconfig

@@ -13,7 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select LIFT_BSP_APIC_ID
 	select BOARD_ROMSIZE_KB_512

src/mainboard/ibase/mb899/Kconfig

@@ -19,7 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select MMCONF_SUPPORT
 	select HAVE_SMI_HANDLER
 	select BOARD_ROMSIZE_KB_512
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select GFXUMA
 	select TINY_BOOTBLOCK
 

src/mainboard/ibm/e325/Kconfig

@@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select WAIT_BEFORE_CPUS_INIT

src/mainboard/ibm/e326/Kconfig

@@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select WAIT_BEFORE_CPUS_INIT

src/mainboard/iei/pcisa-lx-800-r10/Kconfig

@@ -9,7 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select SUPERIO_WINBOND_W83627HF
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select BOARD_ROMSIZE_KB_256
 
 config MAINBOARD_DIR

src/mainboard/intel/d945gclf/Kconfig

@@ -41,7 +41,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_ACPI_TABLES
 	select HAVE_SMI_HANDLER
 	select BOARD_ROMSIZE_KB_512
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select GFXUMA
 	select TINY_BOOTBLOCK
 

src/mainboard/intel/mtarvon/Kconfig

@@ -7,7 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_INTEL_I3100
 	select SOUTHBRIDGE_INTEL_I3100
 	select SUPERIO_INTEL_I3100
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE

src/mainboard/iwill/dk8_htx/Kconfig

@@ -14,7 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select LIFT_BSP_APIC_ID
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY

src/mainboard/iwill/dk8s2/Kconfig

@@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select HAVE_OPTION_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select WAIT_BEFORE_CPUS_INIT

src/mainboard/iwill/dk8x/Kconfig

@@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select WAIT_BEFORE_CPUS_INIT

src/mainboard/jetway/pa78vm5/Kconfig

@@ -14,7 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select GENERATE_PIRQ_TABLE
 	select GENERATE_MP_TABLE
 	select HAVE_MAINBOARD_RESOURCES
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select LIFT_BSP_APIC_ID

src/mainboard/kontron/986lcd-m/Kconfig

@@ -19,7 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select MMCONF_SUPPORT
 	select HAVE_SMI_HANDLER
 	select BOARD_ROMSIZE_KB_1024
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select GFXUMA
 	select TINY_BOOTBLOCK
 

src/mainboard/kontron/kt690/Kconfig

@@ -16,7 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_MP_TABLE
 	select HAVE_MAINBOARD_RESOURCES
 	select GFXUMA
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_1024

src/mainboard/lanner/em8510/Kconfig

@@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select HAVE_HARD_RESET
 	select BOARD_ROMSIZE_KB_512
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select TINY_BOOTBLOCK
 
 config MAINBOARD_DIR

src/mainboard/lippert/frontrunner/Kconfig

@@ -7,7 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_AMD_GX2
 	select SOUTHBRIDGE_AMD_CS5535
 	select UDELAY_TSC
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_PIRQ_TABLE
 	select BOARD_ROMSIZE_KB_256
 

src/mainboard/lippert/roadrunner-lx/Kconfig

@@ -10,7 +10,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
 	select UDELAY_TSC
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select BOARD_ROMSIZE_KB_512
 
 config MAINBOARD_DIR

src/mainboard/lippert/spacerunner-lx/Kconfig

@@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
 	select UDELAY_TSC
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select BOARD_ROMSIZE_KB_512
 
 config MAINBOARD_DIR

src/mainboard/msi/ms7135/Kconfig

@@ -13,7 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select BOARD_ROMSIZE_KB_512
 
 config MAINBOARD_DIR

src/mainboard/msi/ms7260/Kconfig

@@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select LIFT_BSP_APIC_ID
 	select K8_REV_F_SUPPORT

src/mainboard/msi/ms9185/Kconfig

@@ -13,7 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select LIFT_BSP_APIC_ID
 	select BOARD_ROMSIZE_KB_512

src/mainboard/msi/ms9282/Kconfig

@@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select K8_REV_F_SUPPORT
 	select BOARD_ROMSIZE_KB_512

src/mainboard/msi/ms9652_fam10/Kconfig

@@ -10,7 +10,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_BUS_CONFIG
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_OPTION_TABLE
 	select HAVE_HARD_RESET
 	select BOARD_ROMSIZE_KB_512

src/mainboard/newisys/khepri/Kconfig

@@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select BOARD_ROMSIZE_KB_512
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY

src/mainboard/nvidia/l1_2pvv/Kconfig

@@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_BUS_CONFIG
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select LIFT_BSP_APIC_ID
 	select K8_REV_F_SUPPORT

src/mainboard/olpc/btest/Kconfig

@@ -7,7 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_AMD_GX2
 	select SOUTHBRIDGE_AMD_CS5536
 	select UDELAY_TSC
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_PIRQ_TABLE
 	select BOARD_ROMSIZE_KB_256
 

src/mainboard/olpc/rev_a/Kconfig

@@ -7,7 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_AMD_GX2
 	select SOUTHBRIDGE_AMD_CS5536
 	select UDELAY_TSC
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_PIRQ_TABLE
 	select BOARD_ROMSIZE_KB_256
 

src/mainboard/pcengines/alix1c/Kconfig

@@ -10,7 +10,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
 	select UDELAY_TSC
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select BOARD_ROMSIZE_KB_512
 
 config MAINBOARD_DIR

src/mainboard/pcengines/alix2d3/Kconfig

@@ -9,7 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
 	select UDELAY_TSC
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select BOARD_ROMSIZE_KB_512
 
 config MAINBOARD_DIR

src/mainboard/rca/rm4100/Kconfig

@@ -14,7 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_MAINBOARD_RESOURCES
 	select HAVE_SMI_HANDLER
 	select GFXUMA
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select TINY_BOOTBLOCK
 
 config MAINBOARD_DIR

src/mainboard/sunw/ultra40/Kconfig

@@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_BUS_CONFIG
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select BOARD_ROMSIZE_KB_1024
 

src/mainboard/supermicro/h8dme/Kconfig

@@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_BUS_CONFIG
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	#select AP_CODE_IN_CAR
 	select LIFT_BSP_APIC_ID

src/mainboard/supermicro/h8dmr/Kconfig

@@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_BUS_CONFIG
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select LIFT_BSP_APIC_ID
 	select BOARD_ROMSIZE_KB_1024

src/mainboard/supermicro/h8dmr_fam10/Kconfig

@@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select LIFT_BSP_APIC_ID
 	select AMDMCT

src/mainboard/supermicro/h8qme_fam10/Kconfig

@@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select LIFT_BSP_APIC_ID
 	select AMDMCT

src/mainboard/technexion/tim5690/Kconfig

@@ -14,7 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select HAVE_ACPI_TABLES

src/mainboard/technexion/tim8690/Kconfig

@@ -14,7 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 	select WAIT_BEFORE_CPUS_INIT

src/mainboard/thomson/ip1000/Kconfig

@@ -14,7 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_MAINBOARD_RESOURCES
 	select HAVE_SMI_HANDLER
 	select GFXUMA
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select TINY_BOOTBLOCK
 
 config MAINBOARD_DIR

src/mainboard/traverse/geos/Kconfig

@@ -9,7 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
 	select UDELAY_TSC
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select BOARD_ROMSIZE_KB_1024
 
 config MAINBOARD_DIR

src/mainboard/tyan/s2735/Kconfig

@@ -14,7 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_MP_TABLE
 	select UDELAY_TSC
 	select HAVE_OPTION_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select USE_WATCHDOG_ON_BOOT
 	select BOARD_ROMSIZE_KB_512
 

src/mainboard/tyan/s2912/Kconfig

@@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select LIFT_BSP_APIC_ID
 	select K8_REV_F_SUPPORT

src/mainboard/tyan/s2912_fam10/Kconfig

@@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select LIFT_BSP_APIC_ID
 	select BOARD_ROMSIZE_KB_1024

src/mainboard/tyan/s4880/Kconfig

@@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select BOARD_ROMSIZE_KB_512
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY

src/mainboard/tyan/s4882/Kconfig

@@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_HARD_RESET
 	select BOARD_ROMSIZE_KB_512
 	select SB_HT_CHAIN_UNITID_OFFSET_ONLY

src/mainboard/via/vt8454c/Kconfig

@@ -14,7 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_HARD_RESET
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_512
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select TINY_BOOTBLOCK
 
 config MAINBOARD_DIR

src/mainboard/winent/pl6064/Kconfig

@@ -10,7 +10,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
 	select UDELAY_TSC
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select BOARD_ROMSIZE_KB_512
 
 config MAINBOARD_DIR

src/mainboard/wyse/s50/Kconfig

@@ -25,7 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_AMD_GX2
 	select SOUTHBRIDGE_AMD_CS5536
 	select UDELAY_TSC
-	select USE_DCACHE_RAM
+	select CACHE_AS_RAM
 	select HAVE_PIRQ_TABLE
 	select PIRQ_ROUTE
 	select BOARD_ROMSIZE_KB_256

src/northbridge/intel/e7501/debug.c

@@ -39,7 +39,7 @@ static void dump_pci_device(unsigned dev)
 	for(i = 0; i < 256; i++) {
 		unsigned char val;
 		if ((i & 0x0f) == 0) {
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
                         printk(BIOS_DEBUG, "\n%02x:",i);
 #else
 			print_debug("\n");
@@ -48,7 +48,7 @@ static void dump_pci_device(unsigned dev)
 #endif
 		}
 		val = pci_read_config8(dev, i);
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
 		printk(BIOS_DEBUG, " %02x", val);
 #else
 		print_debug_char(' ');
@@ -101,7 +101,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl)
 		device = ctrl->channel0[i];
 		if (device) {
 			int j;
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
 			printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
 #else
 			print_debug("dimm: ");
@@ -113,7 +113,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl)
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
 					printk(BIOS_DEBUG, "\n%02x: ", j);
 #else
 					print_debug("\n");
@@ -126,7 +126,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl)
 					break;
 				}
 				byte = status & 0xff;
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
 				printk(BIOS_DEBUG, "%02x ", byte);
 #else
 				print_debug_hex8(byte);
@@ -138,7 +138,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl)
 		device = ctrl->channel1[i];
 		if (device) {
 			int j;
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
                         printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
 #else
 			print_debug("dimm: ");
@@ -150,7 +150,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl)
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
                                         printk(BIOS_DEBUG, "\n%02x: ", j);
 #else
 					print_debug("\n");
@@ -163,7 +163,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl)
 					break;
 				}
 				byte = status & 0xff;
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
                                 printk(BIOS_DEBUG, "%02x ", byte);
 #else
 				print_debug_hex8(byte);
@@ -181,7 +181,7 @@ static inline void dump_smbus_registers(void)
         for(device = 1; device < 0x80; device++) {
                 int j;
 		if( smbus_read_byte(device, 0) < 0 ) continue;
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
 		printk(BIOS_DEBUG, "smbus: %02x", device);
 #else
                 print_debug("smbus: ");
@@ -195,7 +195,7 @@ static inline void dump_smbus_registers(void)
 				break;
                         }
                         if ((j & 0xf) == 0) {
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
 				printk(BIOS_DEBUG, "\n%02x: ",j);
 #else
                 	        print_debug("\n");
@@ -204,7 +204,7 @@ static inline void dump_smbus_registers(void)
 #endif
                         }
                         byte = status & 0xff;
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
                         printk(BIOS_DEBUG, "%02x ", byte);
 #else
                         print_debug_hex8(byte);
@@ -219,7 +219,7 @@ static inline void dump_io_resources(unsigned port)
 {
 
 	int i;
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
 	printk(BIOS_DEBUG, "%04x:\n", port);
 #else
         print_debug_hex16(port);
@@ -228,7 +228,7 @@ static inline void dump_io_resources(unsigned port)
         for(i=0;i<256;i++) {
                 uint8_t val;
                 if ((i & 0x0f) == 0) {
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
 			printk(BIOS_DEBUG, "%02x:", i);
 #else
                         print_debug_hex8(i);
@@ -236,7 +236,7 @@ static inline void dump_io_resources(unsigned port)
 #endif
                 }
                 val = inb(port);
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
 		printk(BIOS_DEBUG, " %02x",val);
 #else
                 print_debug_char(' ');
@@ -255,7 +255,7 @@ static inline void dump_mem(unsigned start, unsigned end)
 	print_debug("dump_mem:");
         for(i=start;i<end;i++) {
 		if((i & 0xf)==0) {
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
 			printk(BIOS_DEBUG, "\n%08x:", i);
 #else
 			print_debug("\n");
@@ -263,7 +263,7 @@ static inline void dump_mem(unsigned start, unsigned end)
 			print_debug(":");
 #endif
 		}
-#if CONFIG_USE_DCACHE_RAM
+#if CONFIG_CACHE_AS_RAM
 		printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
 #else
 		print_debug(" ");

src/northbridge/intel/i3100/raminit.c

@@ -1212,7 +1212,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	pci_write_config16(ctrl->f0, MCHSCRB, data16);
 
 	/* The memory is now setup, use it */
-#if CONFIG_USE_DCACHE_RAM == 0
+#if CONFIG_CACHE_AS_RAM == 0
 	cache_lbmem(MTRR_TYPE_WRBACK);
 #endif
 }

src/pc80/Makefile.inc

@@ -4,7 +4,7 @@ obj-y += i8259.o
 obj-$(CONFIG_UDELAY_IO) += udelay_io.o
 obj-y += keyboard.o
 initobj-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.o
-initobj-$(CONFIG_USE_DCACHE_RAM) += serial.o
+initobj-$(CONFIG_CACHE_AS_RAM) += serial.o
 subdirs-y += vga
 
 $(obj)/pc80/mc146818rtc.o : $(OPTION_TABLE_H)

src/pc80/serial.c

@@ -28,7 +28,7 @@
 #define UART_LCS	CONFIG_TTYS0_LCS
 
 
-#if CONFIG_USE_DCACHE_RAM == 0
+#if CONFIG_CACHE_AS_RAM == 0
 
 /* Data */
 #define UART_RBR 0x00
@@ -97,7 +97,7 @@ void uart_init(void)
 }
 
 #else
-/* CONFIG_USE_DCACHE_RAM == 1 */
+/* CONFIG_CACHE_AS_RAM == 1 */
 
 extern void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs);
 void uart_init(void)