sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

White space and comment fixes for cache_as_ram.inc files so it's easier to spot

Browse Source 
differences.  Trivial.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4827 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson
2009-10-23 18:22:27 +00:00
parent 35ed0e7ea3
commit 707fad0508
3 changed files with 274 additions and 273 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/cpu/amd/car/cache_as_ram.inc
View File

@@ -253,7 +253,7 @@ clear_fixed_var_mtrr_out:
#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 0)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 0)) #if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 0)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 0))
/* disable cache */ /* disable cache */
movl %cr0, %eax movl %cr0, %eax
orl $(1 << 30),%eax orl $(0x1 << 30), %eax
movl %eax, %cr0 movl %eax, %cr0
#endif #endif
@@ -317,6 +317,7 @@ fam10_end_part1:
movl $CacheBase, %esi movl $CacheBase, %esi
movl $(CacheSize >> 2), %ecx movl $(CacheSize >> 2), %ecx
rep lodsl rep lodsl
/* Clear the range */ /* Clear the range */
movl $CacheBase, %edi movl $CacheBase, %edi
movl $(CacheSize >> 2), %ecx movl $(CacheSize >> 2), %ecx

3
src/cpu/via/car/cache_as_ram.inc
View File

@@ -52,6 +52,7 @@ CacheAsRam:
/* Clear all MTRRs */ /* Clear all MTRRs */
xorl %edx, %edx xorl %edx, %edx
movl $fixed_mtrr_msr, %esi movl $fixed_mtrr_msr, %esi
clear_fixed_var_mtrr: clear_fixed_var_mtrr:
lodsl (%esi), %eax lodsl (%esi), %eax
testl %eax, %eax testl %eax, %eax
@@ -91,7 +92,6 @@ clear_fixed_var_mtrr_out:
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr wrmsr
movl $MTRRdefType_MSR, %ecx movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx xorl %edx, %edx
/* Enable Variable and Fixed MTRRs */ /* Enable Variable and Fixed MTRRs */
@@ -153,6 +153,7 @@ testok: movb $0x40,%al
/* Restore the BIST result */ /* Restore the BIST result */
movl %ebp, %eax movl %ebp, %eax
/* We need to set ebp ? No need */ /* We need to set ebp ? No need */
movl %esp, %ebp movl %esp, %ebp
pushl %eax /* bist */ pushl %eax /* bist */

13
src/cpu/x86/car/cache_as_ram.inc
View File

@@ -116,9 +116,9 @@ NotHtProcessor:
#endif #endif
/* Clear all MTRRs */ /* Clear all MTRRs */
xorl %edx, %edx xorl %edx, %edx
movl $fixed_mtrr_msr, %esi movl $fixed_mtrr_msr, %esi
clear_fixed_var_mtrr: clear_fixed_var_mtrr:
lodsl (%esi), %eax lodsl (%esi), %eax
testl %eax, %eax testl %eax, %eax
@@ -144,13 +144,13 @@ clear_fixed_var_mtrr_out:
*/ */
xorl \reg, \reg xorl \reg, \reg
.elseif \segs == 1 .elseif \segs == 1
movl $0x06000000, \reg movl $0x06000000, \reg /* WB IO type */
.elseif \segs == 2 .elseif \segs == 2
movl $0x06060000, \reg movl $0x06060000, \reg /* WB IO type */
.elseif \segs == 3 .elseif \segs == 3
movl $0x06060600, \reg movl $0x06060600, \reg /* WB IO type */
.elseif \segs >= 4 .elseif \segs >= 4
movl $0x06060606, \reg movl $0x06060606, \reg /* WB IO type */
.endif .endif
.endm .endm
@@ -292,16 +292,15 @@ clear_fixed_var_mtrr_out:
#endif #endif
lout: lout:
/* Restore the BIST result */ /* Restore the BIST result */
movl %ebp, %eax movl %ebp, %eax
/* We need to set ebp ? No need */ /* We need to set ebp ? No need */
movl %esp, %ebp movl %esp, %ebp
pushl %eax /* bist */ pushl %eax /* bist */
call amd64_main call amd64_main
/* We will not go back */ /* We will not go back */
fixed_mtrr_msr: fixed_mtrr_msr:
.long 0x250, 0x258, 0x259 .long 0x250, 0x258, 0x259
.long 0x268, 0x269, 0x26A .long 0x268, 0x269, 0x26A