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White space and comment fixes for cache_as_ram.inc files so it's easier to spot

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differences.  Trivial.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4827 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson
2009-10-23 18:22:27 +00:00
parent 35ed0e7ea3
commit 707fad0508
3 changed files with 274 additions and 273 deletions
Download Patch File Download Diff File Expand all files Collapse all files

35
src/cpu/amd/car/cache_as_ram.inc
View File

@@ -31,7 +31,7 @@
#define jmp_if_k8(x) comisd %xmm2, %xmm1; jb x #define jmp_if_k8(x) comisd %xmm2, %xmm1; jb x
#define CPUID_MASK 0x0ff00f00 #define CPUID_MASK 0x0ff00f00
#define CPUID_VAL_FAM10_ROTATED 0x0f000010 #define CPUID_VAL_FAM10_ROTATED 0x0f000010
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
@@ -127,13 +127,13 @@ CAR_FAM10_out:
/* Erratum 343, RevGuide for Fam10h, Pub#41322 Rev. 3.33 */ /* Erratum 343, RevGuide for Fam10h, Pub#41322 Rev. 3.33 */
/* read-address has to be stored in the ecx register */ /* read-address has to be stored in the ecx register */
movl $MSR_FAM10, %ecx movl $MSR_FAM10, %ecx
/* execute special read command for msr-register. Result is then in the EDX:EAX-registers (MSBs in EDX) */ /* execute special read command for msr-register. Result is then in the EDX:EAX-registers (MSBs in EDX) */
rdmsr rdmsr
/* Set bit 35 to 1 in EAX */ /* Set bit 35 to 1 in EAX */
bts $35, %eax bts $35, %eax
/* write back the modified register EDX:EAX to the MSR specified in ECX */ /* write back the modified register EDX:EAX to the MSR specified in ECX */
wrmsr wrmsr
@@ -157,13 +157,13 @@ enable_fixed_mtrr_dram_modify:
clear_fixed_var_mtrr: clear_fixed_var_mtrr:
lodsl (%esi), %eax lodsl (%esi), %eax
testl %eax, %eax testl %eax, %eax
jz clear_fixed_var_mtrr_out jz clear_fixed_var_mtrr_out
movl %eax, %ecx movl %eax, %ecx
xorl %eax, %eax xorl %eax, %eax
wrmsr wrmsr
jmp clear_fixed_var_mtrr jmp clear_fixed_var_mtrr
clear_fixed_var_mtrr_out: clear_fixed_var_mtrr_out:
/* 0x06 is the WB IO type for a given 4k segment. /* 0x06 is the WB IO type for a given 4k segment.
@@ -231,15 +231,15 @@ clear_fixed_var_mtrr_out:
#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation. #error Invalid CAR size, is not a multiple of 4k. This is a processor limitation.
#endif #endif
#if CacheSize > 0x8000 #if CacheSize > 0x8000
/* enable caching for 32K-64K using fixed mtrr */ /* enable caching for 32K-64K using fixed mtrr */
movl $0x268, %ecx /* fix4k_c0000*/ movl $0x268, %ecx /* fix4k_c0000*/
simplemask CacheSize, 0x8000 simplemask CacheSize, 0x8000
wrmsr wrmsr
#endif #endif
/* enable caching for 0-32K using fixed mtrr */ /* enable caching for 0-32K using fixed mtrr */
movl $0x269, %ecx /* fix4k_c8000*/ movl $0x269, %ecx /* fix4k_c8000*/
simplemask CacheSize, 0 simplemask CacheSize, 0
wrmsr wrmsr
@@ -253,7 +253,7 @@ clear_fixed_var_mtrr_out:
#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 0)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 0)) #if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 0)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 0))
/* disable cache */ /* disable cache */
movl %cr0, %eax movl %cr0, %eax
orl $(1 << 30),%eax orl $(0x1 << 30), %eax
movl %eax, %cr0 movl %eax, %cr0
#endif #endif
@@ -287,7 +287,7 @@ wbcache_post_fam10_setup:
/* Enable the MTRRs and IORRs in SYSCFG */ /* Enable the MTRRs and IORRs in SYSCFG */
movl $SYSCFG_MSR, %ecx movl $SYSCFG_MSR, %ecx
rdmsr rdmsr
orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
wrmsr wrmsr
#endif #endif
@@ -312,16 +312,17 @@ fam10_end_part1:
outb %al, $0x80 outb %al, $0x80
#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1)) #if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
/* Read the range with lodsl*/ /* Read the range with lodsl*/
cld cld
movl $CacheBase, %esi movl $CacheBase, %esi
movl $(CacheSize >> 2), %ecx movl $(CacheSize >> 2), %ecx
rep lodsl rep lodsl
/* Clear the range */ /* Clear the range */
movl $CacheBase, %edi movl $CacheBase, %edi
movl $(CacheSize >> 2), %ecx movl $(CacheSize >> 2), %ecx
xorl %eax, %eax xorl %eax, %eax
rep stosl rep stosl
#endif /*CONFIG_USE_FAILOVER_IMAGE == 1*/ #endif /*CONFIG_USE_FAILOVER_IMAGE == 1*/
@@ -395,7 +396,7 @@ CAR_FAM10_ap_out:
call cache_as_ram_main call cache_as_ram_main
/* We will not go back */ /* We will not go back */
movb $0xAF, %al /* Should never see this postcode */ movb $0xAF, %al /* Should never see this postcode */
outb %al, $0x80 outb %al, $0x80
fixed_mtrr_msr: fixed_mtrr_msr:

147
src/cpu/via/car/cache_as_ram.inc
View File

@@ -1,6 +1,6 @@
/* /*
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
* Copyright (C) 2005 Eswar Nallusamy, LANL * Copyright (C) 2005 Eswar Nallusamy, LANL
* Copyright (C) 2005 Tyan * Copyright (C) 2005 Tyan
@@ -10,153 +10,154 @@
* Copyright (C) 2007,2008 Carl-Daniel Hailfinger * Copyright (C) 2007,2008 Carl-Daniel Hailfinger
* Copyright (C) 2008 VIA Technologies, Inc. * Copyright (C) 2008 VIA Technologies, Inc.
* (Written by Jason Zhao <jasonzhao@viatech.com.cn> for VIA) * (Written by Jason Zhao <jasonzhao@viatech.com.cn> for VIA)
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License. * the Free Software Foundation; version 2 of the License.
* *
* This program is distributed in the hope that it will be useful, * This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
* *
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase CONFIG_DCACHE_RAM_BASE #define CacheBase CONFIG_DCACHE_RAM_BASE
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
/* Save the BIST result */ /* Save the BIST result */
movl %eax, %ebp movl %eax, %ebp
CacheAsRam: CacheAsRam:
/* disable cache */ /* disable cache */
movl %cr0, %eax movl %cr0, %eax
orl $(0x1<<30),%eax orl $(0x1<<30),%eax
movl %eax,%cr0 movl %eax,%cr0
invd invd
/* Set the default memory type and enable fixed and variable MTRRs */ /* Set the default memory type and enable fixed and variable MTRRs */
movl $MTRRdefType_MSR, %ecx movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx xorl %edx, %edx
/* Enable Variable and Fixed MTRRs */ /* Enable Variable and Fixed MTRRs */
movl $0x00000c00, %eax movl $0x00000c00, %eax
wrmsr wrmsr
/* Clear all MTRRs */ /* Clear all MTRRs */
xorl %edx, %edx xorl %edx, %edx
movl $fixed_mtrr_msr, %esi movl $fixed_mtrr_msr, %esi
clear_fixed_var_mtrr:
lodsl (%esi), %eax
testl %eax, %eax
jz clear_fixed_var_mtrr_out
movl %eax, %ecx clear_fixed_var_mtrr:
xorl %eax, %eax lodsl (%esi), %eax
testl %eax, %eax
jz clear_fixed_var_mtrr_out
movl %eax, %ecx
xorl %eax, %eax
wrmsr wrmsr
jmp clear_fixed_var_mtrr jmp clear_fixed_var_mtrr
clear_fixed_var_mtrr_out: clear_fixed_var_mtrr_out:
/* MTRRPhysBase */ /* MTRRPhysBase */
movl $0x200, %ecx movl $0x200, %ecx
xorl %edx, %edx xorl %edx, %edx
movl $(CacheBase|MTRR_TYPE_WRBACK),%eax movl $(CacheBase|MTRR_TYPE_WRBACK),%eax
wrmsr wrmsr
/* MTRRPhysMask */ /* MTRRPhysMask */
movl $0x201, %ecx movl $0x201, %ecx
/* This assumes we never access addresses above 2^36 in CAR. */ /* This assumes we never access addresses above 2^36 in CAR. */
movl $0x0000000f,%edx movl $0x0000000f,%edx
movl $(~(CacheSize-1)|0x800),%eax movl $(~(CacheSize-1)|0x800),%eax
wrmsr wrmsr
/* enable write base caching so we can do execute in place /* enable write base caching so we can do execute in place
* on the flash rom. * on the flash rom.
*/ */
/* MTRRPhysBase */ /* MTRRPhysBase */
movl $0x202, %ecx movl $0x202, %ecx
xorl %edx, %edx xorl %edx, %edx
movl $(CONFIG_XIP_ROM_BASE|MTRR_TYPE_WRBACK),%eax movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
wrmsr wrmsr
/* MTRRPhysMask */ /* MTRRPhysMask */
movl $0x203, %ecx movl $0x203, %ecx
movl $0x0000000f,%edx movl $0x0000000f, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr wrmsr
movl $MTRRdefType_MSR, %ecx
movl $MTRRdefType_MSR, %ecx xorl %edx, %edx
xorl %edx, %edx
/* Enable Variable and Fixed MTRRs */ /* Enable Variable and Fixed MTRRs */
movl $0x00000800, %eax movl $0x00000800, %eax
wrmsr wrmsr
movl %cr0, %eax movl %cr0, %eax
andl $0x9fffffff,%eax andl $0x9fffffff, %eax
movl %eax, %cr0 movl %eax, %cr0
/* Read the range with lodsl*/ /* Read the range with lodsl*/
cld cld
movl $CacheBase, %esi movl $CacheBase, %esi
movl %esi, %edi movl %esi, %edi
movl $(CacheSize>>2), %ecx movl $(CacheSize>>2), %ecx
rep lodsl rep lodsl
movl $CacheBase, %esi movl $CacheBase, %esi
movl %esi, %edi movl %esi, %edi
movl $(CacheSize>>2), %ecx movl $(CacheSize >> 2), %ecx
/* 0x5c5c5c5c is a memory test pattern. /* 0x5c5c5c5c is a memory test pattern.
* TODO: Check if everything works with the zero pattern as well. */ * TODO: Check if everything works with the zero pattern as well. */
/*xorl %eax, %eax*/ /*xorl %eax, %eax*/
xorl $0x5c5c5c5c,%eax xorl $0x5c5c5c5c,%eax
rep stosl rep stosl
movl CONFIG_XIP_ROM_BASE, %esi movl CONFIG_XIP_ROM_BASE, %esi
movl %esi, %edi movl %esi, %edi
movl $(CONFIG_XIP_ROM_SIZE>>2), %ecx movl $(CONFIG_XIP_ROM_SIZE>>2), %ecx
rep lodsl rep lodsl
/* The key point of this CAR code is C7 cache does not turn into /* The key point of this CAR code is C7 cache does not turn into
* "no fill" mode, which is not compatible with general CAR code. * "no fill" mode, which is not compatible with general CAR code.
*/ */
movl $(CacheBase+CacheSize-4), %eax movl $(CacheBase + CacheSize - 4), %eax
movl %eax, %esp movl %eax, %esp
#ifdef CARTEST #ifdef CARTEST
testok: movb $0x40,%al testok: movb $0x40,%al
outb %al, $0x80 outb %al, $0x80
xorl %edx, %edx xorl %edx, %edx
xorl %eax, %eax xorl %eax, %eax
movl $0x5c5c,%edx movl $0x5c5c,%edx
pushl %edx pushl %edx
pushl %edx pushl %edx
pushl %edx pushl %edx
pushl %edx pushl %edx
pushl %edx pushl %edx
popl %esi popl %esi
popl %esi popl %esi
popl %eax popl %eax
popl %eax popl %eax
popl %eax popl %eax
cmpl %edx,%eax cmpl %edx,%eax
jne stackerr jne stackerr
#endif #endif
/* Restore the BIST result */ /* Restore the BIST result */
movl %ebp, %eax movl %ebp, %eax
/* We need to set ebp ? No need */ /* We need to set ebp ? No need */
movl %esp, %ebp movl %esp, %ebp
pushl %eax /* bist */ pushl %eax /* bist */
call amd64_main call amd64_main
/* We will not go back */ /* We will not go back */
fixed_mtrr_msr: fixed_mtrr_msr:

365
src/cpu/x86/car/cache_as_ram.inc
View File

@@ -1,6 +1,6 @@
/* /*
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
* Copyright (C) 2005 Eswar Nallusamy, LANL * Copyright (C) 2005 Eswar Nallusamy, LANL
* Copyright (C) 2005 Tyan * Copyright (C) 2005 Tyan
@@ -8,16 +8,16 @@
* Copyright (C) 2007 coresystems GmbH * Copyright (C) 2007 coresystems GmbH
* (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH) * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
* Copyright (C) 2007 Carl-Daniel Hailfinger * Copyright (C) 2007 Carl-Daniel Hailfinger
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License. * the Free Software Foundation; version 2 of the License.
* *
* This program is distributed in the hope that it will be useful, * This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. * GNU General Public License for more details.
* *
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
@@ -28,107 +28,107 @@
/* other's is the same as AMD except remove amd specific msr */ /* other's is the same as AMD except remove amd specific msr */
#define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase (0xd0000 - CacheSize) #define CacheBase (0xd0000 - CacheSize)
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
/* Save the BIST result */ /* Save the BIST result */
movl %eax, %ebp movl %eax, %ebp
CacheAsRam: CacheAsRam:
/* hope we can skip the double set for normal part */ /* hope we can skip the double set for normal part */
#if CONFIG_USE_FALLBACK_IMAGE == 1 #if CONFIG_USE_FALLBACK_IMAGE == 1
// Check whether the processor has HT capability // Check whether the processor has HT capability
movl $01, %eax movl $01, %eax
cpuid cpuid
btl $28, %edx btl $28, %edx
jnc NotHtProcessor jnc NotHtProcessor
bswapl %ebx bswapl %ebx
cmpb $01, %bh cmpb $01, %bh
jbe NotHtProcessor jbe NotHtProcessor
// It is a HT processor; Send SIPI to the other logical processor // It is a HT processor; Send SIPI to the other logical processor
// within this processor so that the CAR related common system registers // within this processor so that the CAR related common system registers
// are programmed accordingly // are programmed accordingly
// Use some register that is common to both logical processors // Use some register that is common to both logical processors
// as semaphore. Refer Appendix B, Vol.3 // as semaphore. Refer Appendix B, Vol.3
xorl %eax, %eax xorl %eax, %eax
xorl %edx, %edx xorl %edx, %edx
movl $0x250, %ecx movl $0x250, %ecx
wrmsr wrmsr
// Figure out the logical AP's APIC ID; the following logic will work // Figure out the logical AP's APIC ID; the following logic will work
// only for processors with 2 threads // only for processors with 2 threads
// Refer to Vol 3. Table 7-1 for details about this logic // Refer to Vol 3. Table 7-1 for details about this logic
movl $0xFEE00020, %esi movl $0xFEE00020, %esi
movl (%esi), %ebx movl (%esi), %ebx
andl $0xFF000000, %ebx andl $0xFF000000, %ebx
bswapl %ebx bswapl %ebx
btl $0, %ebx btl $0, %ebx
jnc LogicalAP0 jnc LogicalAP0
andb $0xFE, %bl andb $0xFE, %bl
jmp Send_SIPI jmp Send_SIPI
LogicalAP0: LogicalAP0:
orb $0x01, %bl orb $0x01, %bl
Send_SIPI: Send_SIPI:
bswapl %ebx // ebx - logical AP's APIC ID bswapl %ebx // ebx - logical AP's APIC ID
// Fill up the IPI command registers in the Local APIC mapped to default address // Fill up the IPI command registers in the Local APIC mapped to default address
// and issue SIPI to the other logical processor within this processor die. // and issue SIPI to the other logical processor within this processor die.
Retry_SIPI: Retry_SIPI:
movl %ebx, %eax movl %ebx, %eax
movl $0xFEE00310, %esi movl $0xFEE00310, %esi
movl %eax, (%esi) movl %eax, (%esi)
// SIPI vector - F900:0000 // SIPI vector - F900:0000
movl $0x000006F9, %eax movl $0x000006F9, %eax
movl $0xFEE00300, %esi movl $0xFEE00300, %esi
movl %eax, (%esi) movl %eax, (%esi)
movl $0x30, %ecx movl $0x30, %ecx
SIPI_Delay: SIPI_Delay:
pause pause
decl %ecx decl %ecx
jnz SIPI_Delay jnz SIPI_Delay
movl (%esi), %eax movl (%esi), %eax
andl $0x00001000, %eax andl $0x00001000, %eax
jnz Retry_SIPI jnz Retry_SIPI
// Wait for the Logical AP to complete initialization // Wait for the Logical AP to complete initialization
LogicalAP_SIPINotdone: LogicalAP_SIPINotdone:
movl $0x250, %ecx movl $0x250, %ecx
rdmsr rdmsr
orl %eax, %eax orl %eax, %eax
jz LogicalAP_SIPINotdone jz LogicalAP_SIPINotdone
NotHtProcessor: NotHtProcessor:
#if 1 #if 1
/* Set the default memory type and enable fixed and variable MTRRs */ /* Set the default memory type and enable fixed and variable MTRRs */
movl $MTRRdefType_MSR, %ecx movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx xorl %edx, %edx
/* Enable Variable and Fixed MTRRs */ /* Enable Variable and Fixed MTRRs */
movl $0x00000c00, %eax movl $0x00000c00, %eax
wrmsr wrmsr
#endif #endif
/*Clear all MTRRs */ /* Clear all MTRRs */
xorl %edx, %edx
movl $fixed_mtrr_msr, %esi
xorl %edx, %edx
movl $fixed_mtrr_msr, %esi
clear_fixed_var_mtrr: clear_fixed_var_mtrr:
lodsl (%esi), %eax lodsl (%esi), %eax
testl %eax, %eax testl %eax, %eax
jz clear_fixed_var_mtrr_out jz clear_fixed_var_mtrr_out
movl %eax, %ecx movl %eax, %ecx
xorl %eax, %eax xorl %eax, %eax
wrmsr wrmsr
jmp clear_fixed_var_mtrr jmp clear_fixed_var_mtrr
clear_fixed_var_mtrr_out: clear_fixed_var_mtrr_out:
/* 0x06 is the WB IO type for a given 4k segment. /* 0x06 is the WB IO type for a given 4k segment.
@@ -144,13 +144,13 @@ clear_fixed_var_mtrr_out:
*/ */
xorl \reg, \reg xorl \reg, \reg
.elseif \segs == 1 .elseif \segs == 1
movl $0x06000000, \reg movl $0x06000000, \reg /* WB IO type */
.elseif \segs == 2 .elseif \segs == 2
movl $0x06060000, \reg movl $0x06060000, \reg /* WB IO type */
.elseif \segs == 3 .elseif \segs == 3
movl $0x06060600, \reg movl $0x06060600, \reg /* WB IO type */
.elseif \segs >= 4 .elseif \segs >= 4
movl $0x06060606, \reg movl $0x06060606, \reg /* WB IO type */
.endif .endif
.endm .endm
@@ -179,170 +179,169 @@ clear_fixed_var_mtrr_out:
#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation. #error Invalid CAR size, is not a multiple of 4k. This is a processor limitation.
#endif #endif
#if CacheSize > 0x8000 #if CacheSize > 0x8000
/* enable caching for 32K-64K using fixed mtrr */ /* enable caching for 32K-64K using fixed mtrr */
movl $0x268, %ecx /* fix4k_c0000*/ movl $0x268, %ecx /* fix4k_c0000*/
simplemask CacheSize, 0x8000 simplemask CacheSize, 0x8000
wrmsr wrmsr
#endif #endif
/* enable caching for 0-32K using fixed mtrr */ /* enable caching for 0-32K using fixed mtrr */
movl $0x269, %ecx /* fix4k_c8000*/ movl $0x269, %ecx /* fix4k_c8000*/
simplemask CacheSize, 0 simplemask CacheSize, 0
wrmsr wrmsr
#else #else
/* disable cache */ /* disable cache */
movl %cr0, %eax movl %cr0, %eax
orl $(0x1<<30),%eax orl $(0x1 << 30), %eax
movl %eax, %cr0 movl %eax, %cr0
#endif /* CONFIG_USE_FALLBACK_IMAGE == 1*/ #endif /* CONFIG_USE_FALLBACK_IMAGE == 1*/
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
/* enable write base caching so we can do execute in place /* enable write base caching so we can do execute in place
* on the flash rom. * on the flash rom.
*/ */
movl $0x202, %ecx movl $0x202, %ecx
xorl %edx, %edx xorl %edx, %edx
movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax movl $(CONFIG_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
wrmsr wrmsr
movl $0x203, %ecx movl $0x203, %ecx
movl $0x0000000f, %edx movl $0x0000000f, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr wrmsr
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
/* enable cache */ /* enable cache */
movl %cr0, %eax movl %cr0, %eax
andl $0x9fffffff,%eax andl $0x9fffffff, %eax
movl %eax, %cr0 movl %eax, %cr0
#if CONFIG_USE_FALLBACK_IMAGE == 1 #if CONFIG_USE_FALLBACK_IMAGE == 1
/* Read the range with lodsl*/ /* Read the range with lodsl*/
movl $CacheBase, %esi movl $CacheBase, %esi
cld cld
movl $(CacheSize>>2), %ecx movl $(CacheSize >> 2), %ecx
rep lodsl rep lodsl
/* Clear the range */ /* Clear the range */
movl $CacheBase, %edi movl $CacheBase, %edi
movl $(CacheSize>>2), %ecx movl $(CacheSize >> 2), %ecx
xorl %eax, %eax xorl %eax, %eax
rep stosl rep stosl
#if 0 #if 0
/* check the cache as ram */ /* check the cache as ram */
movl $CacheBase, %esi movl $CacheBase, %esi
movl $(CacheSize>>2), %ecx movl $(CacheSize>>2), %ecx
.xin1: .xin1:
movl %esi, %eax movl %esi, %eax
movl %eax, (%esi) movl %eax, (%esi)
decl %ecx decl %ecx
je .xout1 je .xout1
add $4, %esi add $4, %esi
jmp .xin1 jmp .xin1
.xout1: .xout1:
movl $CacheBase, %esi movl $CacheBase, %esi
// movl $(CacheSize>>2), %ecx // movl $(CacheSize>>2), %ecx
movl $4, %ecx movl $4, %ecx
.xin1x: .xin1x:
movl %esi, %eax movl %esi, %eax
movl $0x4000, %edx movl $0x4000, %edx
movb %ah, %al movb %ah, %al
.testx1: .testx1:
outb %al, $0x80 outb %al, $0x80
decl %edx decl %edx
jnz .testx1 jnz .testx1
movl (%esi), %eax
cmpb 0xff, %al
je .xin2 /* dont show */
movl $0x4000, %edx movl (%esi), %eax
cmpb 0xff, %al
je .xin2 /* dont show */
movl $0x4000, %edx
.testx2: .testx2:
outb %al, $0x80 outb %al, $0x80
decl %edx decl %edx
jnz .testx2 jnz .testx2
.xin2: decl %ecx .xin2: decl %ecx
je .xout1x je .xout1x
add $4, %esi add $4, %esi
jmp .xin1x jmp .xin1x
.xout1x: .xout1x:
#endif #endif
#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/ #endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/
movl $(CacheBase+CacheSize-4), %eax movl $(CacheBase + CacheSize - 4), %eax
movl %eax, %esp movl %eax, %esp
/* Load a different set of data segments */ /* Load a different set of data segments */
#if CONFIG_USE_INIT #if CONFIG_USE_INIT
movw $CACHE_RAM_DATA_SEG, %ax movw $CACHE_RAM_DATA_SEG, %ax
movw %ax, %ds movw %ax, %ds
movw %ax, %es movw %ax, %es
movw %ax, %ss movw %ax, %ss
#endif #endif
lout: lout:
/* Restore the BIST result */ /* Restore the BIST result */
movl %ebp, %eax movl %ebp, %eax
/* We need to set ebp ? No need */ /* We need to set ebp ? No need */
movl %esp, %ebp movl %esp, %ebp
pushl %eax /* bist */ pushl %eax /* bist */
call amd64_main call amd64_main
/* We will not go back */ /* We will not go back */
fixed_mtrr_msr:
fixed_mtrr_msr: .long 0x250, 0x258, 0x259
.long 0x250, 0x258, 0x259 .long 0x268, 0x269, 0x26A
.long 0x268, 0x269, 0x26A .long 0x26B, 0x26C, 0x26D
.long 0x26B, 0x26C, 0x26D .long 0x26E, 0x26F
.long 0x26E, 0x26F var_mtrr_msr:
var_mtrr_msr: .long 0x200, 0x201, 0x202, 0x203
.long 0x200, 0x201, 0x202, 0x203 .long 0x204, 0x205, 0x206, 0x207
.long 0x204, 0x205, 0x206, 0x207 .long 0x208, 0x209, 0x20A, 0x20B
.long 0x208, 0x209, 0x20A, 0x20B .long 0x20C, 0x20D, 0x20E, 0x20F
.long 0x20C, 0x20D, 0x20E, 0x20F .long 0x000 /* NULL, end of table */
.long 0x000 /* NULL, end of table */
#if CONFIG_USE_FALLBACK_IMAGE == 1 #if CONFIG_USE_FALLBACK_IMAGE == 1
.align 0x1000 .align 0x1000
.code16 .code16
.global LogicalAP_SIPI .global LogicalAP_SIPI
LogicalAP_SIPI: LogicalAP_SIPI:
// cr0 register is shared among the logical processors; // cr0 register is shared among the logical processors;
// so clear CD & NW bits so that the BSP's cr0 register // so clear CD & NW bits so that the BSP's cr0 register
// controls the cache behavior // controls the cache behavior
// Note: The cache behavior is determined by "OR" result // Note: The cache behavior is determined by "OR" result
// of the cr0 registers of the logical processors // of the cr0 registers of the logical processors
movl %cr0, %eax movl %cr0, %eax
andl $0x9FFFFFFF, %eax andl $0x9FFFFFFF, %eax
movl %eax, %cr0 movl %eax, %cr0
finit finit
// Set the semaphore to indicate the Logical AP is done // Set the semaphore to indicate the Logical AP is done
// with CAR specific initialization // with CAR specific initialization
movl $0x250, %ecx movl $0x250, %ecx
movl $0x06, %eax movl $0x06, %eax
xorl %edx, %edx xorl %edx, %edx
wrmsr wrmsr
// Halt this AP // Halt this AP
cli cli
Halt_LogicalAP: Halt_LogicalAP:
hlt hlt
jmp Halt_LogicalAP jmp Halt_LogicalAP
.code32 .code32
#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/ #endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/
.CacheAsRam_out: .CacheAsRam_out: