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nb/intel/i945: Fix errors found by checkpatch.pl

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Change-Id: Ic2dd40e73d4a4c091c5ce1f49bbf9ab4d013d7af
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18704
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Arthur Heymans
2017-03-09 11:30:23 +01:00
committed by Martin Roth
parent 219daafa8f
commit 70a8e34853
11 changed files with 450 additions and 400 deletions
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23
src/northbridge/intel/i945/debug.c
View File

@@ -40,7 +40,7 @@ void print_pci_devices(void)
} }
} }
void dump_pci_device(unsigned dev) void dump_pci_device(unsigned int dev)
{ {
int i; int i;
@@ -48,16 +48,14 @@ void dump_pci_device(unsigned dev)
for (i = 0; i <= 255; i++) { for (i = 0; i <= 255; i++) {
unsigned char val; unsigned char val;
if ((i & 0x0f) == 0) { if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "%02x:", i); printk(BIOS_DEBUG, "%02x:", i);
}
val = pci_read_config8(dev, i); val = pci_read_config8(dev, i);
printk(BIOS_DEBUG, " %02x", val); printk(BIOS_DEBUG, " %02x", val);
if ((i & 0x0f) == 0x0f) { if ((i & 0x0f) == 0x0f)
printk(BIOS_DEBUG, "\n"); printk(BIOS_DEBUG, "\n");
} }
} }
}
void dump_pci_devices(void) void dump_pci_devices(void)
{ {
@@ -78,7 +76,7 @@ void dump_pci_devices(void)
void dump_spd_registers(void) void dump_spd_registers(void)
{ {
unsigned device; unsigned int device;
device = DIMM0; device = DIMM0;
while (device <= DIMM3) { while (device <= DIMM3) {
int status = 0; int status = 0;
@@ -86,14 +84,12 @@ void dump_spd_registers(void)
printk(BIOS_DEBUG, "\ndimm %02x", device); printk(BIOS_DEBUG, "\ndimm %02x", device);
for (i = 0; (i < 256); i++) { for (i = 0; (i < 256); i++) {
if ((i % 16) == 0) { if ((i % 16) == 0)
printk(BIOS_DEBUG, "\n%02x: ", i); printk(BIOS_DEBUG, "\n%02x: ", i);
}
status = smbus_read_byte(device, i); status = smbus_read_byte(device, i);
if (status < 0) { if (status < 0)
printk(BIOS_DEBUG, "bad device: %02x\n", -status); printk(BIOS_DEBUG, "bad device: %02x\n", -status);
break; break;
}
printk(BIOS_DEBUG, "%02x ", status); printk(BIOS_DEBUG, "%02x ", status);
} }
device++; device++;
@@ -101,14 +97,13 @@ void dump_spd_registers(void)
} }
} }
void dump_mem(unsigned start, unsigned end) void dump_mem(unsigned int start, unsigned int end)
{ {
unsigned i; unsigned int i;
printk(BIOS_DEBUG, "dump_mem:"); printk(BIOS_DEBUG, "dump_mem:");
for (i = start; i < end; i++) { for (i = start; i < end; i++) {
if ((i & 0xf)==0) { if ((i & 0xf) == 0)
printk(BIOS_DEBUG, "\n%08x:", i); printk(BIOS_DEBUG, "\n%08x:", i);
}
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
} }
printk(BIOS_DEBUG, "\n"); printk(BIOS_DEBUG, "\n");

46
src/northbridge/intel/i945/early_init.c
View File

@@ -160,10 +160,10 @@ static void i945_setup_bars(void)
pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); /* ACPI_CNTL: Enable ACPI BAR */
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); /* Enable GPIOs */ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* GC: Enable GPIOs */
setup_pch_gpios(&mainboard_gpio_map); setup_pch_gpios(&mainboard_gpio_map);
printk(BIOS_DEBUG, " done.\n"); printk(BIOS_DEBUG, " done.\n");
@@ -275,9 +275,8 @@ static void i945_setup_egress_port(void)
} }
/* Is internal graphics enabled? */ /* Is internal graphics enabled? */
if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) { if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1))
MCHBAR32(MMARB1) |= (1 << 17); MCHBAR32(MMARB1) |= (1 << 17);
}
/* Assign Virtual Channel ID 1 to VC1 */ /* Assign Virtual Channel ID 1 to VC1 */
reg32 = EPBAR32(EPVC1RCTL); reg32 = EPBAR32(EPVC1RCTL);
@@ -305,7 +304,8 @@ static void i945_setup_egress_port(void)
printk(BIOS_DEBUG, "Loading port arbitration table ..."); printk(BIOS_DEBUG, "Loading port arbitration table ...");
/* Loop until bit 0 becomes 0 */ /* Loop until bit 0 becomes 0 */
timeout = 0x7fffff; timeout = 0x7fffff;
while ((EPBAR16(EPVC1RSTS) & 1) && --timeout); while ((EPBAR16(EPVC1RSTS) & 1) && --timeout)
;
if (!timeout) if (!timeout)
printk(BIOS_DEBUG, "timeout!\n"); printk(BIOS_DEBUG, "timeout!\n");
else else
@@ -317,7 +317,8 @@ static void i945_setup_egress_port(void)
printk(BIOS_DEBUG, "Wait for VC1 negotiation ..."); printk(BIOS_DEBUG, "Wait for VC1 negotiation ...");
/* Wait for VC1 negotiation pending */ /* Wait for VC1 negotiation pending */
timeout = 0x7fff; timeout = 0x7fff;
while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout); while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout)
;
if (!timeout) if (!timeout)
printk(BIOS_DEBUG, "timeout!\n"); printk(BIOS_DEBUG, "timeout!\n");
else else
@@ -410,7 +411,8 @@ static void i945_setup_dmi_rcrb(void)
printk(BIOS_DEBUG, "Wait for VC1 negotiation ..."); printk(BIOS_DEBUG, "Wait for VC1 negotiation ...");
/* Wait for VC1 negotiation pending */ /* Wait for VC1 negotiation pending */
timeout = 0x7ffff; timeout = 0x7ffff;
while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout); while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout)
;
if (!timeout) if (!timeout)
printk(BIOS_DEBUG, "timeout!\n"); printk(BIOS_DEBUG, "timeout!\n");
else else
@@ -436,9 +438,8 @@ static void i945_setup_dmi_rcrb(void)
DMIBAR32(DMICC) = reg32; DMIBAR32(DMICC) = reg32;
if (activate_aspm) { if (activate_aspm)
DMIBAR32(DMILCTL) |= (3 << 0); DMIBAR32(DMILCTL) |= (3 << 0);
}
#endif #endif
/* Last but not least, some additional steps */ /* Last but not least, some additional steps */
@@ -510,7 +511,8 @@ static void i945_setup_dmi_rcrb(void)
/* wait for bit toggle to 0 */ /* wait for bit toggle to 0 */
printk(BIOS_DEBUG, "Waiting for DMI hardware..."); printk(BIOS_DEBUG, "Waiting for DMI hardware...");
timeout = 0x7fffff; timeout = 0x7fffff;
while ((DMIBAR8(0x32) & (1 << 1)) && --timeout); while ((DMIBAR8(0x32) & (1 << 1)) && --timeout)
;
if (!timeout) if (!timeout)
printk(BIOS_DEBUG, "timeout!\n"); printk(BIOS_DEBUG, "timeout!\n");
else else
@@ -576,9 +578,8 @@ static void i945_setup_pci_express_x16(void)
reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xba); reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xba);
printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16); printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16);
if (!(reg16 & 0x48)) { if (!(reg16 & 0x48))
goto disable_pciexpress_x16_link; goto disable_pciexpress_x16_link;
}
reg16 |= (1 << 4) | (1 << 0); reg16 |= (1 << 4) | (1 << 0);
pci_write_config16(PCI_DEV(0, 0x01, 0), 0xba, reg16); pci_write_config16(PCI_DEV(0, 0x01, 0), 0xba, reg16);
@@ -613,7 +614,9 @@ static void i945_setup_pci_express_x16(void)
/* Wait for training to succeed */ /* Wait for training to succeed */
printk(BIOS_DEBUG, "PCIe link training ..."); printk(BIOS_DEBUG, "PCIe link training ...");
timeout = 0x7ffff; timeout = 0x7ffff;
while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) && --timeout); while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3)
&& --timeout)
;
reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0); reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0);
if (reg32 != 0x00000000 && reg32 != 0xffffffff) { if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
@@ -638,7 +641,9 @@ static void i945_setup_pci_express_x16(void)
printk(BIOS_DEBUG, "PCIe link training ..."); printk(BIOS_DEBUG, "PCIe link training ...");
timeout = 0x7ffff; timeout = 0x7ffff;
while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) && --timeout); while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3)
&& --timeout)
;
reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0); reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0);
if (reg32 != 0x00000000 && reg32 != 0xffffffff) { if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
@@ -659,15 +664,14 @@ static void i945_setup_pci_express_x16(void)
reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x204); reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x204);
reg32 &= 0xfffffc00; /* clear [9:0] */ reg32 &= 0xfffffc00; /* clear [9:0] */
if (reg16 == 1) { if (reg16 == 1)
reg32 |= 0x32b; reg32 |= 0x32b;
// TODO // TODO
/* pci_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */ /* pci_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */
} else if (reg16 == 16) { else if (reg16 == 16)
reg32 |= 0x0f4; reg32 |= 0x0f4;
// TODO // TODO
/* pci_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */ /* pci_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */
}
reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8); reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8);
printk(BIOS_DEBUG, "PCIe device class: %06x\n", reg32); printk(BIOS_DEBUG, "PCIe device class: %06x\n", reg32);
@@ -749,11 +753,10 @@ static void i945_setup_pci_express_x16(void)
pci_write_config32(PCI_DEV(0, 0x01, 0), 0x200, reg32); pci_write_config32(PCI_DEV(0, 0x01, 0), 0x200, reg32);
reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xe80); reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xe80);
if (i945_silicon_revision() >= 2) { if (i945_silicon_revision() >= 2)
reg32 |= (1 << 12); reg32 |= (1 << 12);
} else { else
reg32 &= ~(1 << 12); reg32 &= ~(1 << 12);
}
pci_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32); pci_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32);
reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xeb4); reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xeb4);
@@ -813,7 +816,8 @@ disable_pciexpress_x16_link:
printk(BIOS_DEBUG, "Wait for link to enter detect state... "); printk(BIOS_DEBUG, "Wait for link to enter detect state... ");
timeout = 0x7fffff; timeout = 0x7fffff;
for (reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS); for (reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS);
(reg32 & 0x000f0000) && --timeout;); (reg32 & 0x000f0000) && --timeout;)
;
if (!timeout) if (!timeout)
printk(BIOS_DEBUG, "timeout!\n"); printk(BIOS_DEBUG, "timeout!\n");
else else

21
src/northbridge/intel/i945/gma.c
View File

@@ -346,8 +346,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf,
printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
} }
for (i = 0; i < (uma_size - 256) / 4; i++) for (i = 0; i < (uma_size - 256) / 4; i++) {
{
outl((i << 2) | 1, piobase); outl((i << 2) | 1, piobase);
outl(pphysbase + (i << 12) + 1, piobase + 4); outl(pphysbase + (i << 12) + 1, piobase + 4);
} }
@@ -526,8 +525,7 @@ static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf,
printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
} }
for (i = 0; i < (uma_size - 256) / 4; i++) for (i = 0; i < (uma_size - 256) / 4; i++) {
{
outl((i << 2) | 1, piobase); outl((i << 2) | 1, piobase);
outl(pphysbase + (i << 12) + 1, piobase + 4); outl(pphysbase + (i << 12) + 1, piobase + 4);
} }
@@ -634,7 +632,8 @@ static void gma_func0_init(struct device *dev)
udelay(50); udelay(50);
pci_write_config8(dev, GDRST, 0); pci_write_config8(dev, GDRST, 0);
/* wait for device to finish */ /* wait for device to finish */
while (pci_read_config8(dev, GDRST) & 1) { }; while (pci_read_config8(dev, GDRST) & 1)
;
/* IGD needs to be Bus Master */ /* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 = pci_read_config32(dev, PCI_COMMAND);
@@ -721,7 +720,8 @@ static void gma_func1_init(struct device *dev)
pci_write_config8(dev, 0xf4, 0xff); pci_write_config8(dev, 0xf4, 0xff);
} }
static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) static void gma_set_subsystem(device_t dev, unsigned int vendor,
unsigned int device)
{ {
if (!vendor || !device) { if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -736,22 +736,19 @@ const struct i915_gpu_controller_info *
intel_gma_get_controller_info(void) intel_gma_get_controller_info(void)
{ {
device_t dev = dev_find_slot(0, PCI_DEVFN(0x2, 0)); device_t dev = dev_find_slot(0, PCI_DEVFN(0x2, 0));
if (!dev) { if (!dev)
return NULL; return NULL;
}
struct northbridge_intel_i945_config *chip = dev->chip_info; struct northbridge_intel_i945_config *chip = dev->chip_info;
if (!chip) { if (!chip)
return NULL; return NULL;
}
return &chip->gfx; return &chip->gfx;
} }
static void gma_ssdt(device_t device) static void gma_ssdt(device_t device)
{ {
const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
if (!gfx) { if (!gfx)
return; return;
}
drivers_intel_gma_displays_ssdt_generate(gfx); drivers_intel_gma_displays_ssdt_generate(gfx);
} }

22
src/northbridge/intel/i945/i945.h
View File

@@ -99,9 +99,9 @@
* MCHBAR * MCHBAR
*/ */
#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) #define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x))))
#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) #define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) #define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x))))
/* Chipset Control Registers */ /* Chipset Control Registers */
#define FSBPMC3 0x40 /* 32bit */ #define FSBPMC3 0x40 /* 32bit */
@@ -283,9 +283,9 @@
* EPBAR - Egress Port Root Complex Register Block * EPBAR - Egress Port Root Complex Register Block
*/ */
#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) #define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x))))
#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) #define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x))))
#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) #define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x))))
#define EPPVCCAP1 0x004 /* 32bit */ #define EPPVCCAP1 0x004 /* 32bit */
#define EPPVCCAP2 0x008 /* 32bit */ #define EPPVCCAP2 0x008 /* 32bit */
@@ -314,9 +314,9 @@
* DMIBAR * DMIBAR
*/ */
#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) #define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x))))
#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) #define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x))))
#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) #define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x))))
#define DMIVCECH 0x000 /* 32bit */ #define DMIVCECH 0x000 /* 32bit */
#define DMIPVCCAP1 0x004 /* 32bit */ #define DMIPVCCAP1 0x004 /* 32bit */
@@ -359,10 +359,10 @@ void setup_ich7_gpios(void);
/* debugging functions */ /* debugging functions */
void print_pci_devices(void); void print_pci_devices(void);
void dump_pci_device(unsigned dev); void dump_pci_device(unsigned int dev);
void dump_pci_devices(void); void dump_pci_devices(void);
void dump_spd_registers(void); void dump_spd_registers(void);
void dump_mem(unsigned start, unsigned end); void dump_mem(unsigned int start, unsigned int end);
u32 decode_igd_memory_size(u32 gms); u32 decode_igd_memory_size(u32 gms);

8
src/northbridge/intel/i945/northbridge.c
View File

@@ -163,7 +163,8 @@ static void mc_read_resources(device_t dev)
} }
} }
static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) static void intel_set_subsystem(device_t dev, unsigned int vendor,
unsigned int device)
{ {
if (!vendor || !device) { if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -214,12 +215,11 @@ static struct device_operations cpu_bus_ops = {
static void enable_dev(device_t dev) static void enable_dev(device_t dev)
{ {
/* Set the operations if it is a special bus type */ /* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) { if (dev->path.type == DEVICE_PATH_DOMAIN)
dev->ops = &pci_domain_ops; dev->ops = &pci_domain_ops;
} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
dev->ops = &cpu_bus_ops; dev->ops = &cpu_bus_ops;
} }
}
struct chip_operations northbridge_intel_i945_ops = { struct chip_operations northbridge_intel_i945_ops = {
CHIP_NAME("Intel i945 Northbridge") CHIP_NAME("Intel i945 Northbridge")

5
src/northbridge/intel/i945/ram_calc.c
View File

@@ -29,12 +29,11 @@ static uintptr_t smm_region_start(void)
{ {
uintptr_t tom; uintptr_t tom;
if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) { if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1))
/* IGD enabled, get top of Memory from BSM register */ /* IGD enabled, get top of Memory from BSM register */
tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM); tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM);
} else { else
tom = (pci_read_config8(PCI_DEV(0, 0, 0), TOLUD) & 0xf7) << 24; tom = (pci_read_config8(PCI_DEV(0, 0, 0), TOLUD) & 0xf7) << 24;
}
/* if TSEG enabled subtract size */ /* if TSEG enabled subtract size */
switch (pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM) & 0x07) { switch (pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM) & 0x07) {

527
src/northbridge/intel/i945/raminit.c
View File

File diff suppressed because it is too large Load Diff

11
src/northbridge/intel/i945/rcven.c
View File

@@ -33,12 +33,11 @@ static u32 sample_strobes(int channel_offset, struct sys_info *sysinfo)
addr = 0; addr = 0;
if (channel_offset != 0) { /* must be dual channel */ if (channel_offset != 0) { /* must be dual channel */
if (sysinfo->interleaved == 1) { if (sysinfo->interleaved == 1)
addr |= (1 << 6); addr |= (1 << 6);
} else { else
addr = ((u32)MCHBAR8(C0DRB3)) << 25; addr = ((u32)MCHBAR8(C0DRB3)) << 25;
} }
}
for (i = 0; i < 28; i++) { for (i = 0; i < 28; i++) {
read32((void *)addr); read32((void *)addr);
@@ -46,9 +45,8 @@ static u32 sample_strobes(int channel_offset, struct sys_info *sysinfo)
} }
reg32 = MCHBAR32(RCVENMT); reg32 = MCHBAR32(RCVENMT);
if (channel_offset == 0) { if (channel_offset == 0)
reg32 = reg32 << 2; reg32 = reg32 << 2;
}
/** /**
* [19] = 1: all bits are high * [19] = 1: all bits are high
@@ -313,9 +311,8 @@ static int receive_enable_autoconfig(int channel_offset,
/* This is a debug check to see if the rcven code is fully working. /* This is a debug check to see if the rcven code is fully working.
* It can be removed when the output message is not printed anymore * It can be removed when the output message is not printed anymore
*/ */
if (MCHBAR8(C0WL0REOST + channel_offset) == 0) { if (MCHBAR8(C0WL0REOST + channel_offset) == 0)
printk(BIOS_DEBUG, "Weird. No C%sWL0REOST\n", channel_offset?"1":"0"); printk(BIOS_DEBUG, "Weird. No C%sWL0REOST\n", channel_offset?"1":"0");
}
return 0; return 0;
} }

3
src/northbridge/intel/i945/udelay.c
View File

@@ -65,9 +65,8 @@ void udelay(u32 us)
tsc1 = rdtsc(); tsc1 = rdtsc();
dword = tsc1.lo + tscd.lo; dword = tsc1.lo + tscd.lo;
if ((dword < tsc1.lo) || (dword < tscd.lo)) { if ((dword < tsc1.lo) || (dword < tscd.lo))
tsc1.hi++; tsc1.hi++;
}
tsc1.lo = dword; tsc1.lo = dword;
tsc1.hi += tscd.hi; tsc1.hi += tscd.hi;