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CBMEM: Clarify CBMEM_TOP_BACKUP function usage

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The deprecated LATE_CBMEM_INIT function is renamed:
  set_top_of_ram -> set_late_cbmem_top

Obscure term top_of_ram is replaced:
  backup_top_of_ram -> backup_top_of_low_cacheable
  get_top_of_ram -> restore_top_of_low_cacheable

New function that always resolves to CBMEM top boundary, with
or without SMM, is named restore_cbmem_top().

Change-Id: I61d20f94840ad61e9fd55976e5aa8c27040b8fb7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
This commit is contained in:
Kyösti Mälkki
2017-04-19 19:57:01 +03:00
parent ef8bb9136e
commit 70d92b9465
34 changed files with 78 additions and 76 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/southbridge/amd/agesa/hudson/ramtop.c
View File

@@ -26,7 +26,7 @@ int acpi_get_sleep_type(void)
return (int)tmp;
}
void backup_top_of_ram(uint64_t ramtop)
void backup_top_of_low_cacheable(uintptr_t ramtop)
{
u32 dword = ramtop;
int nvram_pos = 0xf8, i; /* temp */
@@ -37,7 +37,7 @@ void backup_top_of_ram(uint64_t ramtop)
}
}
unsigned long get_top_of_ram(void)
uintptr_t restore_top_of_low_cacheable(void)
{
uint32_t xdata = 0;
int xnvram_pos = 0xf8, xi;
@@ -47,5 +47,5 @@ unsigned long get_top_of_ram(void)
xdata |= inb(BIOSRAM_DATA) << (xi *8);
xnvram_pos++;
}
return (unsigned long) xdata;
return xdata;
}

6
src/southbridge/amd/cimx/sb700/ramtop.c
View File

@@ -18,7 +18,7 @@
#include <cbmem.h>
#include <southbridge/amd/cimx/cimx_util.h>
void backup_top_of_ram(uint64_t ramtop)
void backup_top_of_low_cacheable(uintptr_t ramtop)
{
u32 dword = ramtop;
int nvram_pos = 0xfc, i;
@@ -29,7 +29,7 @@ void backup_top_of_ram(uint64_t ramtop)
}
}
unsigned long get_top_of_ram(void)
uintptr_t restore_top_of_low_cacheable(void)
{
u32 xdata = 0;
int xnvram_pos = 0xfc, xi;
@@ -39,5 +39,5 @@ unsigned long get_top_of_ram(void)
xdata |= inb(BIOSRAM_DATA) << (xi *8);
xnvram_pos++;
}
return (unsigned long) xdata;
return xdata;
}

6
src/southbridge/amd/cimx/sb800/ramtop.c
View File

@@ -26,7 +26,7 @@ int acpi_get_sleep_type(void)
return (int)tmp;
}
void backup_top_of_ram(uint64_t ramtop)
void backup_top_of_low_cacheable(uintptr_t ramtop)
{
u32 dword = ramtop;
int nvram_pos = 0xf8, i; /* temp */
@@ -37,7 +37,7 @@ void backup_top_of_ram(uint64_t ramtop)
}
}
unsigned long get_top_of_ram(void)
uintptr_t restore_top_of_low_cacheable(void)
{
u32 xdata = 0;
int xnvram_pos = 0xf8, xi;
@@ -47,5 +47,5 @@ unsigned long get_top_of_ram(void)
xdata |= inb(BIOSRAM_DATA) << (xi *8);
xnvram_pos++;
}
return (unsigned long) xdata;
return xdata;
}

6
src/southbridge/amd/cimx/sb900/ramtop.c
View File

@@ -18,7 +18,7 @@
#include <cbmem.h>
#include <southbridge/amd/cimx/cimx_util.h>
void backup_top_of_ram(uint64_t ramtop)
void backup_top_of_low_cacheable(uintptr_t ramtop)
{
u32 dword = ramtop;
int nvram_pos = 0xf8, i; /* temp */
@@ -29,7 +29,7 @@ void backup_top_of_ram(uint64_t ramtop)
}
}
unsigned long get_top_of_ram(void)
uintptr_t restore_top_of_low_cacheable(void)
{
u32 xdata = 0;
int xnvram_pos = 0xf8, xi;
@@ -39,5 +39,5 @@ unsigned long get_top_of_ram(void)
xdata |= inb(BIOSRAM_DATA) << (xi *8);
xnvram_pos++;
}
return (unsigned long) xdata;
return xdata;
}

6
src/southbridge/amd/sb700/early_setup.c
View File

@@ -860,8 +860,7 @@ void set_lpc_sticky_ctl(bool enable)
pmio_write(0xbb, byte);
}
#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
unsigned long get_top_of_ram(void)
uintptr_t restore_top_of_low_cacheable(void)
{
uint32_t xdata = 0;
int xnvram_pos = 0xfc, xi;
@@ -873,8 +872,7 @@ unsigned long get_top_of_ram(void)
xdata |= inb(BIOSRAM_DATA) << (xi *8);
xnvram_pos++;
}
return (unsigned long) xdata;
return xdata;
}
#endif
#endif

2
src/southbridge/amd/sb700/lpc.c
View File

@@ -89,7 +89,7 @@ int acpi_get_sleep_type(void)
return ((tmp & (7 << 10)) >> 10);
}
void backup_top_of_ram(uint64_t ramtop)
void backup_top_of_low_cacheable(uintptr_t ramtop)
{
u32 dword = (u32) ramtop;
int nvram_pos = 0xfc, i;

6
src/southbridge/amd/sb800/early_setup.c
View File

@@ -665,8 +665,7 @@ int acpi_get_sleep_type(void)
return ((tmp & (7 << 10)) >> 10);
}
#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
unsigned long get_top_of_ram(void)
uintptr_t restore_top_of_low_cacheable(void)
{
uint32_t xdata = 0;
int xnvram_pos = 0xfc, xi;
@@ -678,8 +677,7 @@ unsigned long get_top_of_ram(void)
xdata |= inb(BIOSRAM_DATA) << (xi *8);
xnvram_pos++;
}
return (unsigned long) xdata;
return xdata;
}
#endif
#endif

4
src/southbridge/via/k8t890/early_car.c
View File

@@ -177,9 +177,9 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
return nvram_pos;
}
unsigned long get_top_of_ram(void)
uintptr_t restore_top_of_low_cacheable(void)
{
if (acpi_get_sleep_type() != 3)
return 0;
return (unsigned long) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM);
return inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM);
}

6
src/southbridge/via/k8t890/host_ctrl.c
View File

@@ -110,12 +110,10 @@ static void host_ctrl_enable_k8m8xx(struct device *dev) {
}
#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
void backup_top_of_ram(uint64_t ramtop)
void backup_top_of_low_cacheable(uintptr_t ramtop)
{
outl((u32) ramtop, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM);
outl((u32) ramtop, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM);
}
#endif
static struct pci_operations lops_pci = {
.set_subsystem = pci_dev_set_subsystem,