riscv-spike: Move coreboot to 0x80000000 (2GiB)

This is where the RAM is (now), on RISC-V.

We need to put coreboot.rom in RAM because Spike (at the moment) only
supports loading code into the RAM, not into the boot ROM.

Change-Id: I6c9b7cffe5fa414825491ee4ac0d2dad59a2d75c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15149
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/arch/riscv/bootblock.S

@@ -34,8 +34,11 @@ machine_handler:
 .globl _start
 _start:
 
+#define STACK_START 0x80800000 /* 2GiB + 8MiB */
+#define STACK_SIZE  0x0000fff0
+
 	// pending figuring out this f-ing toolchain. Hardcode what we know works.
-  li sp, 0x80FFF0 // stack start + stack size
+  li sp, STACK_START + STACK_SIZE
 
   # make room for HLS and initialize it
   addi sp, sp, -64 // MENTRY_FRAME_SIZE
@@ -43,7 +46,7 @@ _start:
   call hls_init
 
   //poison the stack
-  li t1, 0x800000
+  li t1, STACK_START
   li t0, 0xdeadbeef
   sd t0, 0(t1)
 

src/mainboard/emulation/spike-riscv/memlayout.ld

@@ -17,12 +17,14 @@
 
 #include <arch/header.ld>
 
+#define START 0x80000000
+
 SECTIONS
 {
-        DRAM_START(0x0)
+	DRAM_START(START)
-	BOOTBLOCK(0x0, 64K)
+	BOOTBLOCK(START, 64K)
-        STACK(8M, 64K)
+	STACK(START + 8M, 64K)
-	ROMSTAGE(8M + 64K, 128K)
+	ROMSTAGE(START + 8M + 64K, 128K)
-	PRERAM_CBMEM_CONSOLE(8M + 192k, 8K)
+	PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K)
-	RAMSTAGE(8M + 200K, 256K)
+	RAMSTAGE(START + 8M + 200K, 256K)
 }