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vendorcode/amd/agesa/fam14: Remove dropped platform

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This platform use the LEGACY_SMP_INIT which is to be deprecated after
release 4.18.

Change-Id: I9dd3ce763418ff767acd0c55be26a998df77081b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69124
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Arthur Heymans
2022-11-02 00:09:22 +01:00
parent dbdf170dcd
commit 713e3c087b
550 changed files with 0 additions and 158343 deletions
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1
src/vendorcode/amd/agesa/Makefile.inc
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@@ -1,4 +1,3 @@
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += f14
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += f15tn
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += f16kb

3076
src/vendorcode/amd/agesa/f14/AGESA.h
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File diff suppressed because it is too large Load Diff

485
src/vendorcode/amd/agesa/f14/AMD.h
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@@ -1,485 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Agesa structures and definitions
*
* Contains AMD AGESA core interface
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Include
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _AMD_H_
#define _AMD_H_
#define AGESA_REVISION "Arch2008"
#define AGESA_ID "AGESA"
#define Int16FromChar(a,b) ((a) << 0 | (b) << 8)
#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
//
//
// AGESA Types and Definitions
//
//
#define LAST_ENTRY 0xFFFFFFFF
#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
#define IOCF8 0xCF8
#define IOCFC 0xCFC
/// The return status for all AGESA public services.
///
/// Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
/// will have log entries with more detail.
///
typedef enum {
AGESA_SUCCESS = 0, ///< The service completed normally. Info may be logged.
AGESA_UNSUPPORTED, ///< The dispatcher or create struct had an unimplemented function requested.
///< Not logged.
AGESA_BOUNDS_CHK, ///< A dynamic parameter was out of range and the service was not provided.
///< Example, memory address not installed, heap buffer handle not found.
///< Not Logged.
// AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
AGESA_ALERT, ///< An observed condition, but no loss of function.
///< See log. Example, HT CRC.
AGESA_WARNING, ///< Possible or minor loss of function. See Log.
AGESA_ERROR, ///< Significant loss of function, boot may be possible. See Log.
AGESA_CRITICAL, ///< Continue boot only to notify user. See Log.
AGESA_FATAL, ///< Halt booting. See Log, however Fatal errors pertaining to heap problems
///< may not be able to reliably produce log events.
AgesaStatusMax ///< Not a status, for limit checking.
} AGESA_STATUS;
/// For checking whether a status is at or above the mandatory log level.
#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
/**
* Callout method to the host environment.
*
* Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
*
* @param[in] Function The specific callout function being invoked.
* @param[in] FcnData Function specific data item.
* @param[in,out] ConfigPtr Reference to Callout params.
*/
typedef AGESA_STATUS (*CALLOUT_ENTRY) (
IN UINT32 Function,
IN UINTN FcnData,
IN OUT VOID *ConfigPtr
);
typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
///This allocation type is used by the AmdCreateStruct entry point
typedef enum {
PreMemHeap = 0, ///< Create heap in cache.
PostMemDram, ///< Create heap in memory.
ByHost ///< Create heap by Host.
} ALLOCATION_METHOD;
/// These width descriptors are used by the library function, and others, to specify the data size
typedef enum ACCESS_WIDTH {
AccessWidth8 = 1, ///< Access width is 8 bits.
AccessWidth16, ///< Access width is 16 bits.
AccessWidth32, ///< Access width is 32 bits.
AccessWidth64, ///< Access width is 64 bits.
AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.
AccessS3SaveWidth16, ///< Save 16 bits data.
AccessS3SaveWidth32, ///< Save 32 bits data.
AccessS3SaveWidth64, ///< Save 64 bits data.
} ACCESS_WIDTH;
/// AGESA struct name
typedef enum {
// AGESA BASIC FUNCTIONS
AMD_INIT_RECOVERY = 0x00020000, ///< AmdInitRecovery entry point handle
AMD_CREATE_STRUCT, ///< AmdCreateStruct handle
AMD_INIT_EARLY, ///< AmdInitEarly entry point handle
AMD_INIT_ENV, ///< AmdInitEnv entry point handle
AMD_INIT_LATE, ///< AmdInitLate entry point handle
AMD_INIT_MID, ///< AmdInitMid entry point handle
AMD_INIT_POST, ///< AmdInitPost entry point handle
AMD_INIT_RESET, ///< AmdInitReset entry point handle
AMD_INIT_RESUME, ///< AmdInitResume entry point handle
AMD_RELEASE_STRUCT, ///< AmdReleaseStruct handle
AMD_S3LATE_RESTORE, ///< AmdS3LateRestore entry point handle
AMD_S3_SAVE, ///< AmdS3Save entry point handle
AMD_GET_APIC_ID, ///< AmdGetApicId entry point handle
AMD_GET_PCI_ADDRESS, ///< AmdGetPciAddress entry point handle
AMD_IDENTIFY_CORE, ///< AmdIdentifyCore general service handle
AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle
AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle
AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle
AMD_IDENTIFY_DIMMS, ///< AmdIdentifyDimm general service handle
AMD_GET_2D_DATA_EYE, ///< AmdGet2DDataEye general service handle
AMD_S3FINAL_RESTORE, ///< AmdS3FinalRestore entry point handle
AMD_INIT_RTB ///< AmdInitRtb entry point handle
} AGESA_STRUCT_NAME;
/* ResetType constant values */
#define WARM_RESET_WHENEVER 1
#define COLD_RESET_WHENEVER 2
#define WARM_RESET_IMMEDIATELY 3
#define COLD_RESET_IMMEDIATELY 4
// AGESA Structures
/// The standard header for all AGESA services.
/// For internal AGESA naming conventions, see @ref amdconfigparamname .
typedef struct {
IN UINT32 ImageBasePtr; ///< The AGESA Image base address.
IN UINT32 Func; ///< The service desired
IN UINT32 AltImageBasePtr; ///< Alternate Image location
IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
IN UINT8 HeapStatus; ///< For heap status from boot time slide.
IN VOID *HeapBasePtr; ///< Location of the heap
IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use.
} AMD_CONFIG_PARAMS;
/// Create Struct Interface.
typedef struct {
IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
IN AGESA_STRUCT_NAME AgesaFunctionName; ///< The service to init
IN ALLOCATION_METHOD AllocationMethod; ///< How to handle buffer allocation
IN OUT UINT32 NewStructSize; ///< The size of the allocated data, in for ByHost, else out only.
IN OUT VOID *NewStructPtr; ///< The struct for the service.
///< The struct to init for ByHost allocation,
///< the initialized struct on return.
} AMD_INTERFACE_PARAMS;
#define FUNC_0 0 // bit-placed for PCI address creation
#define FUNC_1 1
#define FUNC_2 2
#define FUNC_3 3
#define FUNC_4 4
#define FUNC_5 5
#define FUNC_6 6
#define FUNC_7 7
/// AGESA Binary module header structure
typedef struct {
IN UINT32 Signature; ///< Binary Signature
IN CHAR8 CreatorID[8]; ///< 8 characters ID
IN CHAR8 Version[12]; ///< 12 characters version
IN UINT32 ModuleInfoOffset; ///< Offset of module
IN UINT32 EntryPointAddress; ///< Entry address
IN UINT32 ImageBase; ///< Image base
IN UINT32 RelocTableOffset; ///< Relocate Table offset
IN UINT32 ImageSize; ///< Size
IN UINT16 Checksum; ///< Checksum
IN UINT8 ImageType; ///< Type
IN UINT8 V_Reserved; ///< Reserved
} AMD_IMAGE_HEADER;
/// AGESA Binary module header structure
typedef struct _AMD_MODULE_HEADER {
IN UINT32 ModuleHeaderSignature; ///< Module signature
IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID
IN CHAR8 ModuleVersion[12]; ///< 12 characters version
IN VOID *ModuleDispatcher; ///< A pointer point to dispatcher
IN struct _AMD_MODULE_HEADER *NextBlock; ///< Next module header link
} AMD_MODULE_HEADER;
// AMD_CODE_HEADER Signatures.
#define AGESA_CODE_SIGNATURE {'!', '!', 'A', 'G', 'E', 'S', 'A', ' '}
#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'}
#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'}
/// AGESA_CODE_SIGNATURE
typedef struct {
IN CHAR8 Signature[8]; ///< code header Signature
IN CHAR8 ComponentName[8]; ///< 8 character name of the code module
IN CHAR8 Version[12]; ///< 12 character version string
IN CHAR8 TerminatorNull; ///< null terminated string
IN CHAR8 VerReserved[7]; ///< reserved space
} AMD_CODE_HEADER;
/// Extended PCI address format
typedef struct {
IN OUT UINT32 Register:12; ///< Register offset
IN OUT UINT32 Function:3; ///< Function number
IN OUT UINT32 Device:5; ///< Device number
IN OUT UINT32 Bus:8; ///< Bus number
IN OUT UINT32 Segment:4; ///< Segment
} EXT_PCI_ADDR;
/// Union type for PCI address
typedef union _PCI_ADDR {
IN UINT32 AddressValue; ///< Formal address
IN EXT_PCI_ADDR Address; ///< Extended address
} PCI_ADDR;
// SBDFO - Segment Bus Device Function Offset
// 31:28 Segment (4-bits)
// 27:20 Bus (8-bits)
// 19:15 Device (5-bits)
// 14:12 Function(3-bits)
// 11:00 Offset (12-bits)
#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
(((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
#define ILLEGAL_SBDFO 0xFFFFFFFF
/// CPUID data received registers format
typedef struct {
OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX
OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX
OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX
OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX
} CPUID_DATA;
/// HT frequency for external callbacks
typedef enum {
HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks
HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks
HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks
HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks
HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks
HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks
HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks
HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks
HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks
HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks
HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks
HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks
HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks
HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks
HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks
HT_FREQUENCY_3200M = 19, ///< HT speed 3200 for external callbacks
HT_FREQUENCY_MAX ///< Limit check.
} HT_FREQUENCIES;
// The minimum HT3 frequency
#define HT3_FREQUENCY_MIN HT_FREQUENCY_1200M
#ifndef BIT0
#define BIT0 0x0000000000000001ull
#endif
#ifndef BIT1
#define BIT1 0x0000000000000002ull
#endif
#ifndef BIT2
#define BIT2 0x0000000000000004ull
#endif
#ifndef BIT3
#define BIT3 0x0000000000000008ull
#endif
#ifndef BIT4
#define BIT4 0x0000000000000010ull
#endif
#ifndef BIT5
#define BIT5 0x0000000000000020ull
#endif
#ifndef BIT6
#define BIT6 0x0000000000000040ull
#endif
#ifndef BIT7
#define BIT7 0x0000000000000080ull
#endif
#ifndef BIT8
#define BIT8 0x0000000000000100ull
#endif
#ifndef BIT9
#define BIT9 0x0000000000000200ull
#endif
#ifndef BIT10
#define BIT10 0x0000000000000400ull
#endif
#ifndef BIT11
#define BIT11 0x0000000000000800ull
#endif
#ifndef BIT12
#define BIT12 0x0000000000001000ull
#endif
#ifndef BIT13
#define BIT13 0x0000000000002000ull
#endif
#ifndef BIT14
#define BIT14 0x0000000000004000ull
#endif
#ifndef BIT15
#define BIT15 0x0000000000008000ull
#endif
#ifndef BIT16
#define BIT16 0x0000000000010000ull
#endif
#ifndef BIT17
#define BIT17 0x0000000000020000ull
#endif
#ifndef BIT18
#define BIT18 0x0000000000040000ull
#endif
#ifndef BIT19
#define BIT19 0x0000000000080000ull
#endif
#ifndef BIT20
#define BIT20 0x0000000000100000ull
#endif
#ifndef BIT21
#define BIT21 0x0000000000200000ull
#endif
#ifndef BIT22
#define BIT22 0x0000000000400000ull
#endif
#ifndef BIT23
#define BIT23 0x0000000000800000ull
#endif
#ifndef BIT24
#define BIT24 0x0000000001000000ull
#endif
#ifndef BIT25
#define BIT25 0x0000000002000000ull
#endif
#ifndef BIT26
#define BIT26 0x0000000004000000ull
#endif
#ifndef BIT27
#define BIT27 0x0000000008000000ull
#endif
#ifndef BIT28
#define BIT28 0x0000000010000000ull
#endif
#ifndef BIT29
#define BIT29 0x0000000020000000ull
#endif
#ifndef BIT30
#define BIT30 0x0000000040000000ull
#endif
#ifndef BIT31
#define BIT31 0x0000000080000000ull
#endif
#ifndef BIT32
#define BIT32 0x0000000100000000ull
#endif
#ifndef BIT33
#define BIT33 0x0000000200000000ull
#endif
#ifndef BIT34
#define BIT34 0x0000000400000000ull
#endif
#ifndef BIT35
#define BIT35 0x0000000800000000ull
#endif
#ifndef BIT36
#define BIT36 0x0000001000000000ull
#endif
#ifndef BIT37
#define BIT37 0x0000002000000000ull
#endif
#ifndef BIT38
#define BIT38 0x0000004000000000ull
#endif
#ifndef BIT39
#define BIT39 0x0000008000000000ull
#endif
#ifndef BIT40
#define BIT40 0x0000010000000000ull
#endif
#ifndef BIT41
#define BIT41 0x0000020000000000ull
#endif
#ifndef BIT42
#define BIT42 0x0000040000000000ull
#endif
#ifndef BIT43
#define BIT43 0x0000080000000000ull
#endif
#ifndef BIT44
#define BIT44 0x0000100000000000ull
#endif
#ifndef BIT45
#define BIT45 0x0000200000000000ull
#endif
#ifndef BIT46
#define BIT46 0x0000400000000000ull
#endif
#ifndef BIT47
#define BIT47 0x0000800000000000ull
#endif
#ifndef BIT48
#define BIT48 0x0001000000000000ull
#endif
#ifndef BIT49
#define BIT49 0x0002000000000000ull
#endif
#ifndef BIT50
#define BIT50 0x0004000000000000ull
#endif
#ifndef BIT51
#define BIT51 0x0008000000000000ull
#endif
#ifndef BIT52
#define BIT52 0x0010000000000000ull
#endif
#ifndef BIT53
#define BIT53 0x0020000000000000ull
#endif
#ifndef BIT54
#define BIT54 0x0040000000000000ull
#endif
#ifndef BIT55
#define BIT55 0x0080000000000000ull
#endif
#ifndef BIT56
#define BIT56 0x0100000000000000ull
#endif
#ifndef BIT57
#define BIT57 0x0200000000000000ull
#endif
#ifndef BIT58
#define BIT58 0x0400000000000000ull
#endif
#ifndef BIT59
#define BIT59 0x0800000000000000ull
#endif
#ifndef BIT60
#define BIT60 0x1000000000000000ull
#endif
#ifndef BIT61
#define BIT61 0x2000000000000000ull
#endif
#ifndef BIT62
#define BIT62 0x4000000000000000ull
#endif
#ifndef BIT63
#define BIT63 0x8000000000000000ull
#endif
#endif // _AMD_H_

108
src/vendorcode/amd/agesa/f14/Config/OptionC6Install.h
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@@ -1,108 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: C6 C-state
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 37456 $ @e \$Date: 2010-09-04 04:17:05 +0800 (Sat, 04 Sep 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_C6_STATE_INSTALL_H_
#define _OPTION_C6_STATE_INSTALL_H_
#include "cpuC6State.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_C6_STATE_FEAT
#define F14_C6_STATE_SUPPORT
#if OPTION_C6_STATE == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
#if OPTION_FAMILY14H_ON == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
#undef OPTION_C6_STATE_FEAT
#define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
extern CONST C6_FAMILY_SERVICES ROMDATA F14C6Support;
#undef F14_C6_STATE_SUPPORT
#define F14_C6_STATE_SUPPORT {AMD_FAMILY_14_ON, &F14C6Support},
#if OPTION_EARLY_SAMPLES == TRUE
extern F_F14_ES_IS_C6_SUPPORTED F14IsC6DisabledEarlySample;
extern F_F14_ES_C6_INIT F14C6A0Workaround;
CONST F14_ES_C6_SUPPORT ROMDATA F14EarlySampleC6Support =
{
F14IsC6DisabledEarlySample,
F14C6A0Workaround
};
#else
CONST F14_ES_C6_SUPPORT ROMDATA F14EarlySampleC6Support =
{
(PF_F14_ES_IS_C6_SUPPORTED) CommonVoid,
(PF_F14_ES_C6_INIT) CommonVoid
};
#endif
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA C6FamilyServiceArray[] =
{
F14_C6_STATE_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA C6FamilyServiceTable =
{
(sizeof (C6FamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&C6FamilyServiceArray[0]
};
#endif // _OPTION_C6_STATE_INSTALL_H_

91
src/vendorcode/amd/agesa/f14/Config/OptionCpbInstall.h
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@@ -1,91 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Core Performance Boost
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_CPB_INSTALL_H_
#define _OPTION_CPB_INSTALL_H_
#include "cpuCpb.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPB_FEAT
#define F14_ON_CPB_SUPPORT
#if OPTION_CPB == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
// Family 14h
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
#if OPTION_FAMILY14H_ON == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
#undef OPTION_CPB_FEAT
#define OPTION_CPB_FEAT &CpuFeatureCpb,
extern CONST CPB_FAMILY_SERVICES ROMDATA F14OnCpbSupport;
#undef F14_ON_CPB_SUPPORT
#define F14_ON_CPB_SUPPORT {AMD_FAMILY_14_ON, &F14OnCpbSupport},
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpbFamilyServiceArray[] =
{
F14_ON_CPB_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpbFamilyServiceTable =
{
(sizeof (CpbFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&CpbFamilyServiceArray[0]
};
#endif // _OPTION_CPB_INSTALL_H_

70
src/vendorcode/amd/agesa/f14/Config/OptionCpuCacheFlushOnHaltInstall.h
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@@ -1,70 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: CPU Cache Flush On Halt
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
#define _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
#include "cpuPostInit.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CacheFlushOnHaltFamilyServiceArray[] =
{
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CacheFlushOnHaltFamilyServiceTable =
{
(sizeof (CacheFlushOnHaltFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&CacheFlushOnHaltFamilyServiceArray[0]
};
#endif // _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_

68
src/vendorcode/amd/agesa/f14/Config/OptionCpuCoreLevelingInstall.h
View File

@@ -1,68 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: CPU Core Leveling
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_CPU_CORELEVELING_INSTALL_H_
#define _OPTION_CPU_CORELEVELING_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPU_CORE_LEVELING_FEAT
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CoreLevelingFamilyServiceArray[] =
{
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CoreLevelingFamilyServiceTable =
{
(sizeof (CoreLevelingFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&CoreLevelingFamilyServiceArray[0]
};
#endif // _OPTION_CPU_CORELEVELING_INSTALL_H_

357
src/vendorcode/amd/agesa/f14/Config/OptionCpuFamiliesInstall.h
View File

@@ -1,357 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of all appropriate CPU family specific support.
*
* This file generates the defaults tables for all family specific
* combinations.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 37640 $ @e \$Date: 2010-09-08 23:01:59 +0800 (Wed, 08 Sep 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/* Default all CPU Specific Service members to off. They
will be enabled as needed by cross referencing families
with entry points in the family / model install files. */
#define GET_PSTATE_POWER FALSE
#define GET_PSTATE_FREQ FALSE
#define DISABLE_PSTATE FALSE
#define TRANSITION_PSTATE FALSE
#define PROC_IDD_MAX FALSE
#define GET_TSC_RATE FALSE
#define PSTATE_TRANSITION_LATENCY FALSE
#define GET_PSTATE_REGISTER_INFO FALSE
#define GET_PSTATE_MAX_STATE FALSE
#define SET_PSTATE_LEVELING_REG FALSE
#define GET_NB_FREQ FALSE
#define IS_NBCOF_INIT_NEEDED FALSE
#define AP_INITIAL_LAUNCH FALSE
#define GET_AP_MAILBOX_FROM_HW FALSE
#define SET_AP_CORE_NUMBER FALSE
#define GET_AP_CORE_NUMBER FALSE
#define TRANSFER_AP_CORE_NUMBER FALSE
#define ID_POSITION_INITIAL_APICID FALSE
#define SAVE_FEATURES FALSE
#define WRITE_FEATURES FALSE
#define SET_DOWN_CORE_REG FALSE
#define SET_WARM_RESET_FLAG FALSE
#define GET_WARM_RESET_FLAG FALSE
#define USES_REGISTER_TABLES FALSE
#define BASE_FAMILY_PCI FALSE
#define MODEL_SPECIFIC_PCI FALSE
#define BASE_FAMILY_MSR FALSE
#define MODEL_SPECIFIC_MSR FALSE
#define BRAND_STRING1 FALSE
#define BRAND_STRING2 FALSE
#define BASE_FAMILY_HT_PCI FALSE
#define MODEL_SPECIFIC_HT_PCI FALSE
#define BASE_FAMILY_WORKAROUNDS FALSE
#define GET_PATCHES FALSE
#define GET_PATCHES_EQUIVALENCE_TABLE FALSE
#define GET_CACHE_INFO FALSE
#define GET_SYSTEM_PM_TABLE FALSE
#define GET_WHEA_INIT FALSE
#define GET_CFOH_REG FALSE
#define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE
#define IS_NB_PSTATE_ENABLED FALSE
/*
* Pull in family specific services based on entry point
*/
#if AGESA_ENTRY_INIT_RESET == TRUE
#undef ID_POSITION_INITIAL_APICID
#define ID_POSITION_INITIAL_APICID TRUE
#undef GET_AP_MAILBOX_FROM_HW
#define GET_AP_MAILBOX_FROM_HW TRUE
#undef SET_WARM_RESET_FLAG
#define SET_WARM_RESET_FLAG TRUE
#undef GET_WARM_RESET_FLAG
#define GET_WARM_RESET_FLAG TRUE
#undef GET_CACHE_INFO
#define GET_CACHE_INFO TRUE
#undef GET_AP_CORE_NUMBER
#define GET_AP_CORE_NUMBER TRUE
#undef TRANSFER_AP_CORE_NUMBER
#define TRANSFER_AP_CORE_NUMBER TRUE
#endif
#if AGESA_ENTRY_INIT_EARLY == TRUE
#undef TRANSITION_PSTATE
#define TRANSITION_PSTATE TRUE
#undef DISABLE_PSTATE
#define DISABLE_PSTATE TRUE
#undef PROC_IDD_MAX
#define PROC_IDD_MAX TRUE
#undef GET_TSC_RATE
#define GET_TSC_RATE TRUE
#undef GET_NB_FREQ
#define GET_NB_FREQ TRUE
#undef IS_NBCOF_INIT_NEEDED
#define IS_NBCOF_INIT_NEEDED TRUE
#undef AP_INITIAL_LAUNCH
#define AP_INITIAL_LAUNCH TRUE
#undef GET_AP_MAILBOX_FROM_HW
#define GET_AP_MAILBOX_FROM_HW TRUE
#undef SET_AP_CORE_NUMBER
#define SET_AP_CORE_NUMBER TRUE
#undef GET_AP_CORE_NUMBER
#define GET_AP_CORE_NUMBER TRUE
#undef TRANSFER_AP_CORE_NUMBER
#define TRANSFER_AP_CORE_NUMBER TRUE
#undef ID_POSITION_INITIAL_APICID
#define ID_POSITION_INITIAL_APICID TRUE
#undef SET_DOWN_CORE_REG
#define SET_DOWN_CORE_REG TRUE
#undef SET_WARM_RESET_FLAG
#define SET_WARM_RESET_FLAG TRUE
#undef GET_WARM_RESET_FLAG
#define GET_WARM_RESET_FLAG TRUE
#undef USES_REGISTER_TABLES
#define USES_REGISTER_TABLES TRUE
#undef BASE_FAMILY_PCI
#define BASE_FAMILY_PCI TRUE
#undef MODEL_SPECIFIC_PCI
#define MODEL_SPECIFIC_PCI TRUE
#undef BASE_FAMILY_MSR
#define BASE_FAMILY_MSR TRUE
#undef MODEL_SPECIFIC_MSR
#define MODEL_SPECIFIC_MSR TRUE
#undef BRAND_STRING1
#define BRAND_STRING1 TRUE
#undef BRAND_STRING2
#define BRAND_STRING2 TRUE
#undef BASE_FAMILY_HT_PCI
#define BASE_FAMILY_HT_PCI TRUE
#undef MODEL_SPECIFIC_HT_PCI
#define MODEL_SPECIFIC_HT_PCI TRUE
#undef BASE_FAMILY_WORKAROUNDS
#define BASE_FAMILY_WORKAROUNDS TRUE
#undef GET_PATCHES
#define GET_PATCHES TRUE
#undef GET_PATCHES_EQUIVALENCE_TABLE
#define GET_PATCHES_EQUIVALENCE_TABLE TRUE
#undef GET_SYSTEM_PM_TABLE
#define GET_SYSTEM_PM_TABLE TRUE
#undef GET_CACHE_INFO
#define GET_CACHE_INFO TRUE
#undef GET_PLATFORM_TYPE_SPECIFIC_INFO
#define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
#undef IS_NB_PSTATE_ENABLED
#define IS_NB_PSTATE_ENABLED TRUE
#endif
#if AGESA_ENTRY_INIT_POST == TRUE
#undef ID_POSITION_INITIAL_APICID
#define ID_POSITION_INITIAL_APICID TRUE
#undef GET_PSTATE_POWER
#define GET_PSTATE_POWER TRUE
#undef GET_PSTATE_FREQ
#define GET_PSTATE_FREQ TRUE
#undef TRANSITION_PSTATE
#define TRANSITION_PSTATE TRUE
#undef PROC_IDD_MAX
#define PROC_IDD_MAX TRUE
#undef GET_AP_CORE_NUMBER
#define GET_AP_CORE_NUMBER TRUE
#undef GET_PSTATE_REGISTER_INFO
#define GET_PSTATE_REGISTER_INFO TRUE
#undef GET_PSTATE_MAX_STATE
#define GET_PSTATE_MAX_STATE TRUE
#undef SET_PSTATE_LEVELING_REG
#define SET_PSTATE_LEVELING_REG TRUE
#undef SET_WARM_RESET_FLAG
#define SET_WARM_RESET_FLAG TRUE
#undef GET_WARM_RESET_FLAG
#define GET_WARM_RESET_FLAG TRUE
#undef SAVE_FEATURES
#define SAVE_FEATURES TRUE
#undef WRITE_FEATURES
#define WRITE_FEATURES TRUE
#undef GET_CFOH_REG
#define GET_CFOH_REG TRUE
#undef IS_NB_PSTATE_ENABLED
#define IS_NB_PSTATE_ENABLED TRUE
#endif
#if AGESA_ENTRY_INIT_ENV == TRUE
#endif
#if AGESA_ENTRY_INIT_MID == TRUE
#endif
#if AGESA_ENTRY_INIT_LATE == TRUE
#undef GET_AP_CORE_NUMBER
#define GET_AP_CORE_NUMBER TRUE
#undef GET_PSTATE_FREQ
#define GET_PSTATE_FREQ TRUE
#undef TRANSITION_PSTATE
#define TRANSITION_PSTATE TRUE
#undef PSTATE_TRANSITION_LATENCY
#define PSTATE_TRANSITION_LATENCY TRUE
#undef GET_WHEA_INIT
#define GET_WHEA_INIT TRUE
#undef GET_PLATFORM_TYPE_SPECIFIC_INFO
#define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
#undef GET_TSC_RATE
#define GET_TSC_RATE TRUE
#undef BRAND_STRING1
#define BRAND_STRING1 TRUE
#undef BRAND_STRING2
#define BRAND_STRING2 TRUE
#endif
#if AGESA_ENTRY_INIT_S3SAVE == TRUE
#endif
#if AGESA_ENTRY_INIT_RESUME == TRUE
#undef GET_CFOH_REG
#define GET_CFOH_REG TRUE
#endif
#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
#endif
#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
#undef ID_POSITION_INITIAL_APICID
#define ID_POSITION_INITIAL_APICID TRUE
#endif
/*
* Initialize PCI MMIO mask to 0
*/
#define FAMILY_MMIO_BASE_MASK (0ull)
/*
* Initialize all families to disabled
*/
#define OPT_F14_TABLE
#define OPT_F14_ID_TABLE
/*
* Install family specific support
*/
#if (OPTION_FAMILY14H == TRUE)
#include "OptionFamily14hInstall.h"
#endif
/*
* Process PCI MMIO mask
*/
// If size is 0, but base is not, break the build.
#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0)
#error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
#endif
// If base is 0, but size is not, break the build.
#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0)
#error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
#endif
#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0)
// Both are non-zero, begin further processing.
// Heap runs from 4MB to 8MB. Disallow any addresses below 8MB.
#if (CFG_PCI_MMIO_BASE < 0x800000)
#error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
#endif
// Break the build if the address is too high for the enabled families.
#if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0)
#error BLDCFG: Invalid PCI MMIO base address for the installed CPU families
#endif
// If the size parameter is not valid, break the build.
#if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16)
#if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256)
#error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
#endif
#endif
#define PCI_MMIO_ALIGNMENT ((0x100000 * CFG_PCI_MMIO_SIZE) - 1)
// If the base is not aligned according to size, break the build.
#if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0)
#error BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size
#endif
#undef PCI_MMIO_ALIGNMENT
#endif
/*
* Process sockets / modules
*/
#ifndef ADVCFG_PLATFORM_SOCKETS
#error BLDOPT Set Family supported sockets.
#endif
#ifndef ADVCFG_PLATFORM_MODULES
#error BLDOPT Set Family supported modules.
#endif
CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration =
{
ADVCFG_PLATFORM_SOCKETS,
ADVCFG_PLATFORM_MODULES
};
/*
* Instantiate global data needed for processor identification
*/
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpuSupportedFamiliesArray[] =
{
OPT_F14_TABLE
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpuSupportedFamiliesTable =
{
(sizeof (CpuSupportedFamiliesArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&CpuSupportedFamiliesArray[0]
};
CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] =
{
OPT_F14_ID_TABLE
};
CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable =
{
(sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)),
CpuSupportedFamilyIdArray
};

78
src/vendorcode/amd/agesa/f14/Config/OptionCpuFeaturesInstall.h
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@@ -1,78 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of multiple CPU features.
*
* Aggregates enabled CPU features into a list for the dispatcher to process.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 37157 $ @e \$Date: 2010-09-01 03:24:07 +0800 (Wed, 01 Sep 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_CPU_FEATURES_INSTALL_H_
#define _OPTION_CPU_FEATURES_INSTALL_H_
#include "OptionHwC1eInstall.h"
#include "OptionMsgBasedC1eInstall.h"
#include "OptionSwC1eInstall.h"
#include "OptionHtAssistInstall.h"
#include "OptionCpuCoreLevelingInstall.h"
#include "OptionIoCstateInstall.h"
#include "OptionC6Install.h"
#include "OptionCpbInstall.h"
#include "OptionCpuCacheFlushOnHaltInstall.h"
#include "OptionLowPwrPstateInstall.h"
#include "OptionPreserveMailboxInstall.h"
CONST CPU_FEATURE_DESCRIPTOR* ROMDATA CONST SupportedCpuFeatureList[] =
{
OPTION_HW_C1E_FEAT
OPTION_MSG_BASED_C1E_FEAT
OPTION_SW_C1E_FEAT
OPTION_HT_ASSIST_FEAT
OPTION_CPU_CORE_LEVELING_FEAT
OPTION_IO_CSTATE_FEAT
OPTION_C6_STATE_FEAT
OPTION_CPB_FEAT
OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT // this function should be run before creating ACPI objects and after Pstate initialization
OPTION_PRESERVE_MAILBOX_FEAT
NULL
};
#endif // _OPTION_CPU_FEATURES_INSTALL_H_

129
src/vendorcode/amd/agesa/f14/Config/OptionDmiInstall.h
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@@ -1,129 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: DMI
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_DMI_INSTALL_H_
#define _OPTION_DMI_INSTALL_H_
#include "cpuLateInit.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#if AGESA_ENTRY_INIT_LATE == TRUE
#ifndef OPTION_DMI
#error BLDOPT: Option not defined: "OPTION_DMI"
#endif
#if OPTION_DMI == TRUE
OPTION_DMI_FEATURE GetDmiInfoMain;
OPTION_DMI_RELEASE_BUFFER ReleaseDmiBuffer;
#define USER_DMI_OPTION &GetDmiInfoMain
#define USER_DMI_RELEASE_BUFFER &ReleaseDmiBuffer
// This additional check keeps AP launch routines from being unnecessarily included
// in single socket systems.
#if OPTION_MULTISOCKET == TRUE
#define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info},
#else
#define CPU_DMI_AP_GET_TYPE4_TYPE7
#endif
// Family 14
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
extern PROC_FAMILY_TABLE ProcFamily14DmiTable;
#define FAM14_DMI_SUPPORT FAM14_ENABLED,
#define FAM14_DMI_TABLE &ProcFamily14DmiTable,
#else
#define FAM14_DMI_SUPPORT
#define FAM14_DMI_TABLE
#endif
#else
#define FAM14_DMI_SUPPORT
#define FAM14_DMI_TABLE
#endif
#else
OPTION_DMI_FEATURE GetDmiInfoStub;
OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub;
#define USER_DMI_OPTION GetDmiInfoStub
#define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
#define FAM14_DMI_SUPPORT
#define FAM14_DMI_TABLE
#define CPU_DMI_AP_GET_TYPE4_TYPE7
#endif
#else
OPTION_DMI_FEATURE GetDmiInfoStub;
OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub;
#define USER_DMI_OPTION GetDmiInfoStub
#define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
#define FAM14_DMI_SUPPORT
#define FAM14_DMI_TABLE
#define CPU_DMI_AP_GET_TYPE4_TYPE7
#endif
/// DMI supported families enum
typedef enum {
FAM14_DMI_SUPPORT ///< Conditionally define F14 support
NUM_DMI_FAMILIES ///< Number of installed families
} AGESA_DMI_SUPPORTED_FAM;
/* Declare the Family List. An array of pointers to tables that each describe a family */
CONST PROC_FAMILY_TABLE ROMDATA *ProcTables[] = {
FAM14_DMI_TABLE
NULL
};
/* Declare the instance of the DMI option configuration structure */
CONST OPTION_DMI_CONFIGURATION ROMDATA OptionDmiConfiguration = {
DMI_STRUCT_VERSION,
USER_DMI_OPTION,
USER_DMI_RELEASE_BUFFER,
NUM_DMI_FAMILIES,
(VOID *((*)[])) &ProcTables // Compiler says array size must match struct decl
};
#endif // _OPTION_DMI_INSTALL_H_

669
src/vendorcode/amd/agesa/f14/Config/OptionFamily14hInstall.h
View File

@@ -1,669 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of family 14h support
*
* This file generates the default tables for family 14h processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 37854 $ @e \$Date: 2010-09-14 06:35:39 +0800 (Tue, 14 Sep 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_FAMILY_14H_INSTALL_H_
#define _OPTION_FAMILY_14H_INSTALL_H_
#include "OptionFamily14hEarlySample.h"
/*
* Common Family 14h routines
*/
extern F_CPU_DISABLE_PSTATE F14DisablePstate;
extern F_CPU_TRANSITION_PSTATE F14TransitionPstate;
extern F_CPU_GET_TSC_RATE F14GetTscRate;
extern F_CPU_GET_NB_FREQ F14GetCurrentNbFrequency;
extern F_CPU_GET_NB_PSTATE_INFO F14GetNbPstateInfo;
extern F_CPU_IS_NBCOF_INIT_NEEDED F14GetNbCofVidUpdate;
extern F_CPU_AP_INITIAL_LAUNCH F14LaunchApCore;
extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F14GetApMailboxFromHardware;
extern F_CPU_GET_AP_CORE_NUMBER F14GetApCoreNumber;
extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F14CpuAmdCoreIdPositionInInitialApicId;
extern F_CPU_SET_WARM_RESET_FLAG F14SetAgesaWarmResetFlag;
extern F_CPU_GET_WARM_RESET_FLAG F14GetAgesaWarmResetFlag;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14BrandIdString1;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14BrandIdString2;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14CacheInfo;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14SysPmTable;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14WheaInitData;
//extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F14GetPlatformTypeSpecificInfo;
extern F_CPU_GET_IDD_MAX F14GetProcIddMax;
extern CONST REGISTER_TABLE ROMDATA F14PciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F14PerCorePciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F14MsrRegisterTable;
extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F14GetNumberOfCoresForBrandstring;
extern F_GET_EARLY_INIT_TABLE GetF14OnEarlyInitOnCoreTable;
extern F_IS_NB_PSTATE_ENABLED F14IsNbPstateEnabled;
#if OPTION_EARLY_SAMPLES == TRUE
extern CONST REGISTER_TABLE ROMDATA F14EarlySampleMsrRegisterTable;
#endif
/*
* Install family 14h model 0 support
*/
#ifdef OPTION_FAMILY14H_ON
#if OPTION_FAMILY14H_ON == TRUE
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14OnMicroCodePatchesStruct;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14OnMicrocodeEquivalenceTable;
extern CONST REGISTER_TABLE ROMDATA F14OnPciRegisterTable;
#if USES_REGISTER_TABLES == TRUE
CONST REGISTER_TABLE ROMDATA * CONST F14OnRegisterTables[] =
{
#if BASE_FAMILY_PCI == TRUE
&F14PciRegisterTable,
#endif
#if BASE_FAMILY_PCI == TRUE
&F14PerCorePciRegisterTable,
#endif
#if BASE_FAMILY_MSR == TRUE
&F14MsrRegisterTable,
#if OPTION_EARLY_SAMPLES == TRUE
&F14EarlySampleMsrRegisterTable,
#endif
#endif
#if MODEL_SPECIFIC_PCI == TRUE
&F14OnPciRegisterTable,
#endif
// the end.
NULL
};
#endif
#if USES_REGISTER_TABLES == TRUE
CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F14OnTableEntryTypeDescriptors[] =
{
{MsrRegister, SetRegisterForMsrEntry},
{PciRegister, SetRegisterForPciEntry},
{FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
// End
{TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
};
#endif
CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF14OnServices =
{
0,
#if DISABLE_PSTATE == TRUE
F14DisablePstate,
#else
(PF_CPU_DISABLE_PSTATE) CommonAssert,
#endif
#if TRANSITION_PSTATE == TRUE
F14TransitionPstate,
#else
(PF_CPU_TRANSITION_PSTATE) CommonAssert,
#endif
#if PROC_IDD_MAX == TRUE
F14GetProcIddMax,
#else
(PF_CPU_GET_IDD_MAX) CommonAssert,
#endif
#if GET_TSC_RATE == TRUE
F14GetTscRate,
#else
(PF_CPU_GET_TSC_RATE) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F14GetCurrentNbFrequency,
#else
(PF_CPU_GET_NB_FREQ) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F14GetNbPstateInfo,
#else
(PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
#endif
#if IS_NBCOF_INIT_NEEDED == TRUE
F14GetNbCofVidUpdate,
#else
(PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
#endif
#if AP_INITIAL_LAUNCH == TRUE
F14LaunchApCore,
#else
(PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
#endif
#if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
F14GetNumberOfCoresForBrandstring,
#else
(PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
#endif
#if GET_AP_MAILBOX_FROM_HW == TRUE
F14GetApMailboxFromHardware,
#else
(PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
#endif
#if SET_AP_CORE_NUMBER == TRUE
(PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
#else
(PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
#endif
#if GET_AP_CORE_NUMBER == TRUE
F14GetApCoreNumber,
#else
(PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
#endif
#if TRANSFER_AP_CORE_NUMBER == TRUE
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
#else
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
#endif
#if ID_POSITION_INITIAL_APICID == TRUE
F14CpuAmdCoreIdPositionInInitialApicId,
#else
(PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
#endif
#if SAVE_FEATURES == TRUE
(PF_CPU_SAVE_FEATURES) CommonVoid,
#else
(PF_CPU_SAVE_FEATURES) CommonAssert,
#endif
#if WRITE_FEATURES == TRUE
(PF_CPU_WRITE_FEATURES) CommonVoid,
#else
(PF_CPU_WRITE_FEATURES) CommonAssert,
#endif
#if SET_WARM_RESET_FLAG == TRUE
F14SetAgesaWarmResetFlag,
#else
(PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
#endif
#if GET_WARM_RESET_FLAG == TRUE
F14GetAgesaWarmResetFlag,
#else
(PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
#endif
#if BRAND_STRING1 == TRUE
GetF14BrandIdString1,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if BRAND_STRING2 == TRUE
GetF14BrandIdString2,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES == TRUE
GetF14OnMicroCodePatchesStruct,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
GetF14OnMicrocodeEquivalenceTable,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_CACHE_INFO == TRUE
GetF14CacheInfo,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_SYSTEM_PM_TABLE == TRUE
GetF14SysPmTable,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_WHEA_INIT == TRUE
GetF14WheaInitData,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
F14GetPlatformTypeSpecificInfo,
#else
(PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
#endif
#if IS_NB_PSTATE_ENABLED == TRUE
F14IsNbPstateEnabled,
#else
(PF_IS_NB_PSTATE_ENABLED) CommonAssert,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
(PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
#else
(PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
(PF_SET_HT_PHY_REGISTER) CommonVoid,
#else
(PF_SET_HT_PHY_REGISTER) CommonAssert,
#endif
#if BASE_FAMILY_PCI == TRUE
(PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
#else
(PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
#endif
#if USES_REGISTER_TABLES == TRUE
(REGISTER_TABLE **) F14OnRegisterTables,
#else
NULL,
#endif
#if USES_REGISTER_TABLES == TRUE
(TABLE_ENTRY_TYPE_DESCRIPTOR *) F14OnTableEntryTypeDescriptors,
#else
NULL,
#endif
#if MODEL_SPECIFIC_HT_PCI == TRUE
NULL,
#else
NULL,
#endif
NULL,
InitCacheDisabled,
#if AGESA_ENTRY_INIT_EARLY == TRUE
GetF14OnEarlyInitOnCoreTable
#else
(PF_GET_EARLY_INIT_TABLE) CommonVoid
#endif
};
#define ON_SOCKETS 1
#define ON_MODULES 1
#define ON_RECOVERY_SOCKETS 1
#define ON_RECOVERY_MODULES 1
extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF14OnLogicalIdAndRev;
#define OPT_F14_ON_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF14OnLogicalIdAndRev,
#ifndef ADVCFG_PLATFORM_SOCKETS
#define ADVCFG_PLATFORM_SOCKETS ON_SOCKETS
#else
#if ADVCFG_PLATFORM_SOCKETS < ON_SOCKETS
#undef ADVCFG_PLATFORM_SOCKETS
#define ADVCFG_PLATFORM_SOCKETS ON_SOCKETS
#endif
#endif
#ifndef ADVCFG_PLATFORM_MODULES
#define ADVCFG_PLATFORM_MODULES ON_MODULES
#else
#if ADVCFG_PLATFORM_MODULES < ON_MODULES
#undef ADVCFG_PLATFORM_MODULES
#define ADVCFG_PLATFORM_MODULES ON_MODULES
#endif
#endif
#if GET_PATCHES == TRUE
#define F14_ON_UCODE_0B
#define F14_ON_UCODE_1A
#define F14_ON_UCODE_29
#define F14_ON_UCODE_119
#if AGESA_ENTRY_INIT_EARLY == TRUE
#if OPTION_EARLY_SAMPLES == TRUE
extern CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500000B;
#undef F14_ON_UCODE_0B
#define F14_ON_UCODE_0B &CpuF14MicrocodePatch0500000B,
extern CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500001A;
#undef F14_ON_UCODE_1A
#define F14_ON_UCODE_1A &CpuF14MicrocodePatch0500001A,
#endif
extern CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000029;
#undef F14_ON_UCODE_29
#define F14_ON_UCODE_29 &CpuF14MicrocodePatch05000029,
extern CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000119;
#undef F14_ON_UCODE_119
#define F14_ON_UCODE_119 &CpuF14MicrocodePatch05000119,
#endif
CONST MICROCODE_PATCHES ROMDATA * CONST CpuF14OnMicroCodePatchArray[] =
{
F14_ON_UCODE_119
F14_ON_UCODE_29
F14_ON_UCODE_0B
F14_ON_UCODE_1A
NULL
};
CONST UINT8 ROMDATA CpuF14OnNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF14OnMicroCodePatchArray) / sizeof (CpuF14OnMicroCodePatchArray[0])) - 1);
#endif
#if OPTION_EARLY_SAMPLES == TRUE
extern F_F14_ES_GET_EARLY_INIT_TABLE GetF14OnEarlySampleEarlyInitTable;
extern F_F14_ES_NB_PSTATE_INIT F14NbPstateInitEarlySampleHook;
extern F_F14_ES_POWER_PLANE_INIT F14PowerPlaneInitEarlySampleHook;
CONST F14_ES_CORE_SUPPORT ROMDATA F14EarlySampleCoreSupport =
{
#if AGESA_ENTRY_INIT_EARLY == TRUE
GetF14OnEarlySampleEarlyInitTable,
F14PowerPlaneInitEarlySampleHook,
#else
(PF_F14_ES_GET_EARLY_INIT_TABLE) CommonAssert,
(PF_F14_ES_POWER_PLANE_INIT) CommonAssert,
#endif
#if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
F14NbPstateInitEarlySampleHook
#else
(PF_F14_ES_NB_PSTATE_INIT) CommonAssert
#endif
};
#else
CONST F14_ES_CORE_SUPPORT ROMDATA F14EarlySampleCoreSupport =
{
#if AGESA_ENTRY_INIT_EARLY == TRUE
(PF_F14_ES_GET_EARLY_INIT_TABLE) CommonVoid,
(PF_F14_ES_POWER_PLANE_INIT) CommonVoid,
#else
(PF_F14_ES_GET_EARLY_INIT_TABLE) CommonAssert,
(PF_F14_ES_POWER_PLANE_INIT) CommonAssert,
#endif
#if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
(PF_F14_ES_NB_PSTATE_INIT) CommonVoid
#else
(PF_F14_ES_NB_PSTATE_INIT) CommonAssert
#endif
};
#endif
#define OPT_F14_ON_CPU {AMD_FAMILY_14_ON, &cpuF14OnServices},
#else // OPTION_FAMILY14H_ON == TRUE
#define OPT_F14_ON_CPU
#define OPT_F14_ON_ID
#endif // OPTION_FAMILY14H_ON == TRUE
#else // defined (OPTION_FAMILY14H_ON)
#define OPT_F14_ON_CPU
#define OPT_F14_ON_ID
#endif // defined (OPTION_FAMILY14H_ON)
/*
* Install unknown family 14h support
*/
#if USES_REGISTER_TABLES == TRUE
CONST REGISTER_TABLE ROMDATA * CONST F14UnknownRegisterTables[] =
{
#if BASE_FAMILY_PCI == TRUE
&F14PciRegisterTable,
#endif
#if BASE_FAMILY_PCI == TRUE
&F14PerCorePciRegisterTable,
#endif
#if BASE_FAMILY_MSR == TRUE
&F14MsrRegisterTable,
#endif
// the end.
NULL
};
#endif
#if USES_REGISTER_TABLES == TRUE
CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F14UnknownTableEntryTypeDescriptors[] =
{
{MsrRegister, SetRegisterForMsrEntry},
{PciRegister, SetRegisterForPciEntry},
{FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
// End
{TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
};
#endif
CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF14UnknownServices =
{
0,
#if DISABLE_PSTATE == TRUE
F14DisablePstate,
#else
(PF_CPU_DISABLE_PSTATE) CommonAssert,
#endif
#if TRANSITION_PSTATE == TRUE
F14TransitionPstate,
#else
(PF_CPU_TRANSITION_PSTATE) CommonAssert,
#endif
#if PROC_IDD_MAX == TRUE
(PF_CPU_GET_IDD_MAX) F14GetProcIddMax,
#else
(PF_CPU_GET_IDD_MAX) CommonAssert,
#endif
#if GET_TSC_RATE == TRUE
F14GetTscRate,
#else
(PF_CPU_GET_TSC_RATE) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F14GetCurrentNbFrequency,
#else
(PF_CPU_GET_NB_FREQ) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F14GetNbPstateInfo,
#else
(PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
#endif
#if IS_NBCOF_INIT_NEEDED == TRUE
F14GetNbCofVidUpdate,
#else
(PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
#endif
#if AP_INITIAL_LAUNCH == TRUE
F14LaunchApCore,
#else
(PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
#endif
#if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
F14GetNumberOfCoresForBrandstring,
#else
(PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
#endif
#if GET_AP_MAILBOX_FROM_HW == TRUE
F14GetApMailboxFromHardware,
#else
(PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
#endif
#if SET_AP_CORE_NUMBER == TRUE
(PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
#else
(PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
#endif
#if GET_AP_CORE_NUMBER == TRUE
F14GetApCoreNumber,
#else
(PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
#endif
#if TRANSFER_AP_CORE_NUMBER == TRUE
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
#else
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
#endif
#if ID_POSITION_INITIAL_APICID == TRUE
F14CpuAmdCoreIdPositionInInitialApicId,
#else
(PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
#endif
#if SAVE_FEATURES == TRUE
(PF_CPU_SAVE_FEATURES) CommonVoid,
#else
(PF_CPU_SAVE_FEATURES) CommonAssert,
#endif
#if WRITE_FEATURES == TRUE
(PF_CPU_WRITE_FEATURES) CommonVoid,
#else
(PF_CPU_WRITE_FEATURES) CommonAssert,
#endif
#if SET_WARM_RESET_FLAG == TRUE
F14SetAgesaWarmResetFlag,
#else
(PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
#endif
#if GET_WARM_RESET_FLAG == TRUE
F14GetAgesaWarmResetFlag,
#else
(PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
#endif
#if BRAND_STRING1 == TRUE
GetF14BrandIdString1,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if BRAND_STRING2 == TRUE
GetF14BrandIdString2,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES == TRUE
GetEmptyArray,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
GetEmptyArray,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_CACHE_INFO == TRUE
GetF14CacheInfo,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_SYSTEM_PM_TABLE == TRUE
GetF14SysPmTable,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_WHEA_INIT == TRUE
GetF14WheaInitData,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
F14GetPlatformTypeSpecificInfo,
#else
(PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
#endif
#if IS_NB_PSTATE_ENABLED == TRUE
F14IsNbPstateEnabled,
#else
(PF_IS_NB_PSTATE_ENABLED) CommonAssert,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
(PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
#else
(PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonVoid,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
(PF_SET_HT_PHY_REGISTER) CommonVoid,
#else
(PF_SET_HT_PHY_REGISTER) CommonVoid,
#endif
#if BASE_FAMILY_PCI == TRUE
(PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
#else
(PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
#endif
#if USES_REGISTER_TABLES == TRUE
(REGISTER_TABLE **) F14UnknownRegisterTables,
#else
NULL,
#endif
#if USES_REGISTER_TABLES == TRUE
(TABLE_ENTRY_TYPE_DESCRIPTOR *) F14UnknownTableEntryTypeDescriptors,
#else
NULL,
#endif
#if MODEL_SPECIFIC_HT_PCI == TRUE
NULL,
#else
NULL,
#endif
NULL,
InitCacheDisabled,
#if AGESA_ENTRY_INIT_EARLY == TRUE
GetF14OnEarlyInitOnCoreTable
#else
(PF_GET_EARLY_INIT_TABLE) CommonVoid
#endif
};
// Family 14h maximum base address is 40 bits. Limit BLDCFG to 40 bits, if appropriate.
#if (FAMILY_MMIO_BASE_MASK < 0xFFFFFF0000000000ull)
#undef FAMILY_MMIO_BASE_MASK
#define FAMILY_MMIO_BASE_MASK (0xFFFFFF0000000000ull)
#endif
#undef OPT_F14_ID_TABLE
#define OPT_F14_ID_TABLE {0x14, {AMD_FAMILY_14, AMD_F14_UNKNOWN}, F14LogicalIdTable, (sizeof (F14LogicalIdTable) / sizeof (F14LogicalIdTable[0]))},
#define OPT_F14_UNKNOWN_CPU {AMD_FAMILY_14, &cpuF14UnknownServices},
#undef OPT_F14_TABLE
#define OPT_F14_TABLE OPT_F14_ON_CPU OPT_F14_UNKNOWN_CPU
#if OPTION_FT1_SOCKET_SUPPORT == TRUE
extern CONST CPU_BRAND_TABLE ROMDATA F14OnBrandIdString1ArrayFt1;
extern CONST CPU_BRAND_TABLE ROMDATA F14OnBrandIdString2ArrayFt1;
#define F14_FT1_BRANDSTRING1 &F14OnBrandIdString1ArrayFt1,
#define F14_FT1_BRANDSTRING2 &F14OnBrandIdString2ArrayFt1,
#else
#define F14_FT1_BRANDSTRING1
#define F14_FT1_BRANDSTRING2
#endif
#if BRAND_STRING1 == TRUE
CONST CPU_BRAND_TABLE ROMDATA * CONST F14BrandIdString1Tables[] =
{
F14_FT1_BRANDSTRING1
};
CONST UINT8 F14BrandIdString1TableCount = (sizeof (F14BrandIdString1Tables) / sizeof (F14BrandIdString1Tables[0]));
#endif
#if BRAND_STRING2 == TRUE
CONST CPU_BRAND_TABLE ROMDATA *CONST F14BrandIdString2Tables[] =
{
F14_FT1_BRANDSTRING2
};
CONST UINT8 F14BrandIdString2TableCount = (sizeof (F14BrandIdString2Tables) / sizeof (F14BrandIdString2Tables[0]));
#endif
CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F14LogicalIdTable[] =
{
OPT_F14_ON_ID
};
#endif // _OPTION_FAMILY_14H_INSTALL_H_

53
src/vendorcode/amd/agesa/f14/Config/OptionGfxRecoveryInstall.h
View File

@@ -1,53 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: GfxRecovery
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_GFX_RECOVERY_INSTALL_H_
#define _OPTION_GFX_RECOVERY_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#endif // _OPTION_GFX_RECOVERY_INSTALL_H_

490
src/vendorcode/amd/agesa/f14/Config/OptionGnbInstall.h
View File

@@ -1,490 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: GNB
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_GNB_INSTALL_H_
#define _OPTION_GNB_INSTALL_H_
#include "S3SaveState.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define GNB_TYPE_LN FALSE
#define GNB_TYPE_ON OPTION_FAMILY14H
#define GNB_TYPE_KR FALSE
#define GNB_TYPE_TN FALSE
#include "Gnb.h"
#include "GnbPcie.h"
#ifndef CFG_IGFX_AS_PCIE_EP
#define CFG_IGFX_AS_PCIE_EP TRUE
#endif
#ifndef CFG_LCLK_DEEP_SLEEP_EN
#if (GNB_TYPE_ON == TRUE)
#define CFG_LCLK_DEEP_SLEEP_EN TRUE
#else
#define CFG_LCLK_DEEP_SLEEP_EN FALSE
#endif
#endif
#ifndef CFG_LCLK_DPM_EN
#if (GNB_TYPE_ON == TRUE)
#define CFG_LCLK_DPM_EN TRUE
#else
#define CFG_LCLK_DPM_EN FALSE
#endif
#endif
#ifndef CFG_GMC_POWER_GATE_STUTTER_ONLY
#define CFG_GMC_POWER_GATE_STUTTER_ONLY FALSE
#endif
#ifndef CFG_SMU_SCLK_CLOCK_GATING_ENABLE
#if (GNB_TYPE_ON == TRUE)
#define CFG_SMU_SCLK_CLOCK_GATING_ENABLE TRUE
#else
#define CFG_SMU_SCLK_CLOCK_GATING_ENABLE FALSE
#endif
#endif
#ifndef CFG_PCIE_ASPM_BLACK_LIST_ENABLE
#define CFG_PCIE_ASPM_BLACK_LIST_ENABLE TRUE
#endif
#ifndef CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING
#define CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000)
#endif
#ifndef CFG_GNB_PCIE_LINK_L0_POOLING
#define CFG_GNB_PCIE_LINK_L0_POOLING (60 * 1000)
#endif
#ifndef CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME
#define CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000)
#endif
#ifndef CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME
#define CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000)
#endif
#ifdef BLDCFG_PCIE_TRAINING_ALGORITHM
#define CFG_GNB_PCIE_TRAINING_ALGORITHM BLDCFG_PCIE_TRAINING_ALGORITHM
#else
#define CFG_GNB_PCIE_TRAINING_ALGORITHM PcieTrainingStandard
#endif
CONST GNB_BUILD_OPTIONS GnbBuildOptions = {
CFG_IGFX_AS_PCIE_EP,
CFG_LCLK_DEEP_SLEEP_EN,
CFG_LCLK_DPM_EN,
CFG_GMC_POWER_GATE_STUTTER_ONLY,
CFG_SMU_SCLK_CLOCK_GATING_ENABLE,
CFG_PCIE_ASPM_BLACK_LIST_ENABLE,
CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING,
CFG_GNB_PCIE_LINK_L0_POOLING,
CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME,
CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME,
CFG_GNB_PCIE_TRAINING_ALGORITHM
};
#if (AGESA_ENTRY_INIT_EARLY == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_EARLY_INIT
#define OPTION_NB_EARLY_INIT TRUE
#endif
#if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
OPTION_GNB_FEATURE NbInitAtEarly;
#define OPTION_NBINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEarly},
#else
#define OPTION_NBINITATEARLY_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
// SMU init
#ifndef OPTION_SMU
#define OPTION_SMU TRUE
#endif
#if (OPTION_SMU == TRUE) && (GNB_TYPE_LN == TRUE)
OPTION_GNB_FEATURE F12NbSmuInitFeature;
#define OPTION_F12NBSMUINITFEATURE_ENTRY {AMD_FAMILY_LN, F12NbSmuInitFeature},
#else
#define OPTION_F12NBSMUINITFEATURE_ENTRY
#endif
#if (OPTION_SMU == TRUE) && (GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE F14NbSmuInitFeature;
#define OPTION_F14NBSMUINITFEATURE_ENTRY {AMD_FAMILY_ON, F14NbSmuInitFeature},
#else
#define OPTION_F14NBSMUINITFEATURE_ENTRY
#endif
#if (OPTION_SMU == TRUE) && (GNB_TYPE_KR == TRUE)
OPTION_GNB_FEATURE KRNbSmuInitFeature;
#define OPTION_KRNBSMUINITFEATURE_ENTRY {AMD_FAMILY_KR, KRNbSmuInitFeature},
#else
#define OPTION_KRNBSMUINITFEATURE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_CONFIG_INIT
#define OPTION_PCIE_CONFIG_INIT TRUE
#endif
#if (OPTION_PCIE_CONFIG_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
OPTION_GNB_FEATURE PcieConfigurationInit;
#define OPTION_PCIECONFIGURATIONINIT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieConfigurationInit},
#else
#define OPTION_PCIECONFIGURATIONINIT_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_EARLY_INIT
#define OPTION_PCIE_EARLY_INIT TRUE
#endif
#if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
OPTION_GNB_FEATURE PcieInitAtEarly;
#define OPTION_PCIEINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEarly},
#else
#define OPTION_PCIEINITATEARLY_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
CONST OPTION_GNB_CONFIGURATION GnbEarlyFeatureTable[] = {
OPTION_NBINITATEARLY_ENTRY
OPTION_F12NBSMUINITFEATURE_ENTRY
OPTION_F14NBSMUINITFEATURE_ENTRY
OPTION_KRNBSMUINITFEATURE_ENTRY
OPTION_PCIECONFIGURATIONINIT_ENTRY
OPTION_PCIEINITATEARLY_ENTRY
{0, NULL}
};
#endif
#if (AGESA_ENTRY_INIT_POST == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_CONFIG_POST_INIT
#define OPTION_GFX_CONFIG_POST_INIT TRUE
#endif
#if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
OPTION_GNB_FEATURE GfxConfigPostInterface;
#define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigPostInterface},
#else
#define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_POST_INIT
#define OPTION_GFX_POST_INIT TRUE
#endif
#if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
OPTION_GNB_FEATURE GfxInitAtPost;
#define OPTION_GFXINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtPost},
#else
#define OPTION_GFXINITATPOST_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_POST_INIT
#define OPTION_NB_POST_INIT TRUE
#endif
#if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
OPTION_GNB_FEATURE NbInitAtPost;
#define OPTION_NBINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtPost},
#else
#define OPTION_NBINITATPOST_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_POST_EALRY_INIT
#define OPTION_PCIE_POST_EALRY_INIT TRUE
#endif
#if (OPTION_PCIE_POST_EALRY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieInitAtPostEarly;
#define OPTION_PCIEINITATPOSTEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPostEarly},
#else
#define OPTION_PCIEINITATPOSTEARLY_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_POST_INIT
#define OPTION_PCIE_POST_INIT TRUE
#endif
#if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
OPTION_GNB_FEATURE PcieInitAtPost;
#define OPTION_PCIEINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPost},
#else
#define OPTION_PCIEINITATPOST_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
CONST OPTION_GNB_CONFIGURATION GnbPostFeatureTable[] = {
OPTION_PCIEINITATPOSTEARLY_ENTRY
OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
OPTION_GFXINITATPOST_ENTRY
{0, NULL}
};
CONST OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[] = {
OPTION_NBINITATPOST_ENTRY
OPTION_PCIEINITATPOST_ENTRY
{0, NULL}
};
#endif
#if (AGESA_ENTRY_INIT_ENV == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_FUSE_TABLE_INIT
#define OPTION_FUSE_TABLE_INIT TRUE
#endif
#if (OPTION_FUSE_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
OPTION_GNB_FEATURE NbFuseTableFeature;
#define OPTION_NBFUSETABLEFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbFuseTableFeature},
#else
#define OPTION_NBFUSETABLEFEATURE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_ENV_INIT
#define OPTION_NB_ENV_INIT TRUE
#endif
#if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
OPTION_GNB_FEATURE NbInitAtEnv;
#define OPTION_NBINITATENVT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEnv},
#else
#define OPTION_NBINITATENVT_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_CONFIG_ENV_INIT
#define OPTION_GFX_CONFIG_ENV_INIT TRUE
#endif
#if (OPTION_GFX_CONFIG_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
OPTION_GNB_FEATURE GfxConfigEnvInterface;
#define OPTION_GFXCONFIGENVINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigEnvInterface},
#else
#define OPTION_GFXCONFIGENVINTERFACE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_ENV_INIT
#define OPTION_GFX_ENV_INIT TRUE
#endif
#if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
OPTION_GNB_FEATURE GfxInitAtEnvPost;
#define OPTION_GFXINITATENVPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtEnvPost},
#else
#define OPTION_GFXINITATENVPOST_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_POWER_GATE
#define OPTION_POWER_GATE TRUE
#endif
#if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE)
OPTION_GNB_FEATURE F12NbPowerGateFeature;
#define OPTION_F12NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, F12NbPowerGateFeature},
#else
#define OPTION_F12NBPOWERGATEFEATURE_ENTRY
#endif
#if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE F14NbPowerGateFeature;
#define OPTION_F14NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_ON, F14NbPowerGateFeature},
#else
#define OPTION_F14NBPOWERGATEFEATURE_ENTRY
#endif
#if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_KR == TRUE)
OPTION_GNB_FEATURE KRNbPowerGateFeature;
#define OPTION_KRNBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_KR, KRNbPowerGateFeature},
#else
#define OPTION_KRNBPOWERGATEFEATURE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_ENV_INIT
#define OPTION_PCIE_ENV_INIT TRUE
#endif
#if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
OPTION_GNB_FEATURE PcieInitAtEnv;
#define OPTION_PCIEINITATENV_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEnv},
#else
#define OPTION_PCIEINITATENV_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
CONST OPTION_GNB_CONFIGURATION GnbEnvFeatureTable[] = {
OPTION_NBFUSETABLEFEATURE_ENTRY
OPTION_NBINITATENVT_ENTRY
OPTION_PCIEINITATENV_ENTRY
OPTION_GFXCONFIGENVINTERFACE_ENTRY
OPTION_GFXINITATENVPOST_ENTRY
OPTION_F12NBPOWERGATEFEATURE_ENTRY
OPTION_F14NBPOWERGATEFEATURE_ENTRY
OPTION_KRNBPOWERGATEFEATURE_ENTRY
{0, NULL}
};
#endif
#if (AGESA_ENTRY_INIT_MID == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTOIN_GNB_CABLESAFE
#define OPTOIN_GNB_CABLESAFE TRUE
#endif
#if (OPTOIN_GNB_CABLESAFE == TRUE) && (GNB_TYPE_LN == TRUE)
OPTION_GNB_FEATURE GnbCableSafeEntry;
#define OPTION_GNBCABLESAFEENTRY_ENTRY {AMD_FAMILY_LN, GnbCableSafeEntry},
#else
#define OPTION_GNBCABLESAFEENTRY_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTOIN_NB_LCLK_NCLK_RATIO
#define OPTOIN_NB_LCLK_NCLK_RATIO TRUE
#endif
#if (OPTOIN_NB_LCLK_NCLK_RATIO == TRUE) && (GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE F14NbLclkNclkRatioFeature;
#define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY {AMD_FAMILY_ON, F14NbLclkNclkRatioFeature},
#else
#define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY
#endif
#if (OPTOIN_NB_LCLK_NCLK_RATIO == TRUE) && (GNB_TYPE_KR == TRUE)
OPTION_GNB_FEATURE KRNbLclkNclkRatioFeature;
#define OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY {AMD_FAMILY_KR, KRNbLclkNclkRatioFeature},
#else
#define OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_LCLK_DPM_INIT
#define OPTION_NB_LCLK_DPM_INIT TRUE
#endif
#if (OPTION_NB_LCLK_DPM_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
OPTION_GNB_FEATURE NbLclkDpmFeature;
#define OPTION_NBLCLKDPMFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbLclkDpmFeature},
#else
#define OPTION_NBLCLKDPMFEATURE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_POWER_GATE
#define OPTION_PCIE_POWER_GATE TRUE
#endif
#if (OPTION_PCIE_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE)
OPTION_GNB_FEATURE PciePowerGateFeature;
#define OPTION_PCIEPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, PciePowerGateFeature},
#else
#define OPTION_PCIEPOWERGATEFEATURE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_MID_INIT
#define OPTION_GFX_MID_INIT TRUE
#endif
#if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
OPTION_GNB_FEATURE GfxInitAtMidPost;
#define OPTION_GFXINITATMIDPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtMidPost},
#else
#define OPTION_GFXINITATMIDPOST_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_INTEGRATED_TABLE_INIT
#define OPTION_GFX_INTEGRATED_TABLE_INIT TRUE
#endif
#if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
OPTION_GNB_FEATURE GfxIntegratedInfoTableEntry;
#define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxIntegratedInfoTableEntry},
#else
#define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIe_MID_INIT
#define OPTION_PCIe_MID_INIT TRUE
#endif
#if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
OPTION_GNB_FEATURE PcieInitAtMid;
#define OPTION_PCIEINITATMID_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtMid},
#else
#define OPTION_PCIEINITATMID_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_MID_INIT
#define OPTION_NB_MID_INIT TRUE
#endif
#if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
OPTION_GNB_FEATURE NbInitAtLatePost;
#define OPTION_NBINITATLATEPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtLatePost},
#else
#define OPTION_NBINITATLATEPOST_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
CONST OPTION_GNB_CONFIGURATION GnbMidFeatureTable[] = {
OPTION_GFXINITATMIDPOST_ENTRY
OPTION_GFXINTEGRATEDINFOTABLE_ENTRY
OPTION_GNBCABLESAFEENTRY_ENTRY
OPTION_PCIEINITATMID_ENTRY
OPTION_NBINITATLATEPOST_ENTRY
OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY
OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY
OPTION_NBLCLKDPMFEATURE_ENTRY
OPTION_PCIEPOWERGATEFEATURE_ENTRY
{0, NULL}
};
#endif
#if (AGESA_ENTRY_INIT_LATE == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_ALIB
#define OPTION_ALIB FALSE
#endif
#if (OPTION_ALIB == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
OPTION_GNB_FEATURE PcieAlibFeature;
#define OPTION_PCIEALIBFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieAlibFeature},
#else
#define OPTION_PCIEALIBFEATURE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
CONST OPTION_GNB_CONFIGURATION GnbLateFeatureTable[] = {
OPTION_PCIEALIBFEATURE_ENTRY
{0, NULL}
};
#endif
#if (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
S3_DISPATCH_FUNCTION NbSmuServiceRequestS3Script;
S3_DISPATCH_FUNCTION PcieLateRestoreS3Script;
S3_DISPATCH_FUNCTION NbSmuIndirectWriteS3Script;
#define GNB_S3_DISPATCH_FUNCTION_TABLE \
{S3DispatchGnbSmuIndirectWrite, NbSmuIndirectWriteS3Script}, \
{S3DispatchGnbSmuServiceRequest, NbSmuServiceRequestS3Script}, \
{S3DispatchGnbPcieLateRestore, PcieLateRestoreS3Script},
#endif
#endif // _OPTION_GNB_INSTALL_H_

80
src/vendorcode/amd/agesa/f14/Config/OptionHtAssistInstall.h
View File

@@ -1,80 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: HT Assist
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_HT_ASSIST_INSTALL_H_
#define _OPTION_HT_ASSIST_INSTALL_H_
#include "cpuHtAssist.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_HT_ASSIST_FEAT
#define HT_ASSIST_AP_DISABLE_CACHE
#define HT_ASSIST_AP_ENABLE_CACHE
#if (OPTION_HT_ASSIST == TRUE || OPTION_ATM_MODE == TRUE)
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HtAssistFamilyServiceArray[] =
{
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HtAssistFamilyServiceTable =
{
(sizeof (HtAssistFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&HtAssistFamilyServiceArray[0]
};
#undef HT_ASSIST_AP_DISABLE_CACHE
#define HT_ASSIST_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches},
#undef HT_ASSIST_AP_ENABLE_CACHE
#define HT_ASSIST_AP_ENABLE_CACHE {AP_LATE_TASK_ENABLE_CACHE, (IMAGE_ENTRY) EnableAllCaches},
#endif
#endif
#endif // _OPTION_HT_ASSIST_INSTALL_H_

248
src/vendorcode/amd/agesa/f14/Config/OptionHtInstall.h
View File

@@ -1,248 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Ht
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_HT_INSTALL_H_
#define _OPTION_HT_INSTALL_H_
#include "Topology.h"
#include "htFeat.h"
#include "htInterface.h"
#include "htNb.h"
#include "htTopologies.h"
/*
* Advanced Option only, hardware socket naming is the preferred method.
*/
#ifdef BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP
#define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP)
#else
#define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (NULL)
#endif
/*
* OPTION_IS_RECOVERY_HT is true if Basic API is being used.
*/
#ifndef OPTION_IS_RECOVERY_HT
#define OPTION_IS_RECOVERY_HT TRUE
#endif
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition.
*/
#ifndef OPTION_MULTISOCKET
#error BLDOPT: Option not defined: "OPTION_MULTISOCKET"
#endif
/*
* Based on user level options, set Ht internal options.
* this will have to be changed to not set non-coherent only.
*/
#define OPTION_HT_NON_COHERENT_ONLY FALSE
/* Fusion Families do not need a non-coherent only option. */
/*
* Macros will generate the correct item reference based on options
*/
#if AGESA_ENTRY_INIT_EARLY == TRUE
// Select the interface and features
#if OPTION_FAMILY14H == TRUE
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
#define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNone
#define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceMapsOnly
#define INTERNAL_HT_OPTION_FAM14_NB &HtFam14Nb,
#else
#define INTERNAL_HT_OPTION_FAM14_NB
#endif
#define INTERNAL_ONLY_NB_LIST_ITEM INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS,
#ifndef INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS
#undef INTERNAL_ONLY_NB_LIST_ITEM
#define INTERNAL_ONLY_NB_LIST_ITEM
#endif
/* Install the correct set of northbridge implementations. Each item provides its own comma, the last item
* is ok to have a comma because the final item (NULL) is added below.
*/
#define INTERNAL_HT_OPTION_SUPPORTED_NBS \
INTERNAL_ONLY_NB_LIST_ITEM \
INTERNAL_HT_OPTION_FAM14_NB
#else
// Not Init Early
#define INTERNAL_HT_OPTION_FEATURES NULL
#define INTERNAL_HT_OPTION_INTERFACE NULL
#define INTERNAL_HT_OPTION_SUPPORTED_NBS NULL
#define HT_OPTIONS_PLATFORM NULL
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
#endif
#ifdef AGESA_ENTRY_INIT_EARLY
#if AGESA_ENTRY_INIT_EARLY == TRUE
extern HT_FEATURES HtFeaturesDefault;
extern HT_FEATURES HtFeaturesNonCoherentOnly;
extern HT_FEATURES HtFeaturesNone;
extern HT_INTERFACE HtInterfaceDefault;
extern HT_INTERFACE HtInterfaceNonCoherentOnly;
extern HT_INTERFACE HtInterfaceMapsOnly;
extern HT_INTERFACE HtInterfaceNone;
extern NORTHBRIDGE HtFam10NbDefault;
extern NORTHBRIDGE HtFam10RevDNbDefault;
extern NORTHBRIDGE HtFam10NbNonCoherentOnly;
extern NORTHBRIDGE HtFam10RevDNbNonCoherentOnly;
extern NORTHBRIDGE HtFam12Nb;
extern NORTHBRIDGE HtFam14Nb;
extern NORTHBRIDGE HtFam10NbNone;
extern NORTHBRIDGE HtFam15NbDefault;
extern NORTHBRIDGE HtFam15NbNonCoherentOnly;
CONST VOID * CONST ROMDATA HtInstalledFamilyNorthbridgeList[] = {
INTERNAL_HT_OPTION_SUPPORTED_NBS
NULL
};
STATIC CONST AMD_HT_INTERFACE ROMDATA HtOptionsPlatform =
{
CFG_STARTING_BUSNUM, CFG_MAXIMUM_BUSNUM, CFG_ALLOCATED_BUSNUM,
(MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
(DEVICE_CAP_OVERRIDE *)CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST,
(CPU_TO_CPU_PCB_LIMITS *)CFG_HTFABRIC_LIMITS_LIST,
(IO_PCB_LIMITS *)CFG_HTCHAIN_LIMITS_LIST,
(OVERRIDE_BUS_NUMBERS *)CFG_BUS_NUMBERS_LIST,
(IGNORE_LINK *)CFG_IGNORE_LINK_LIST,
(SKIP_REGANG *)CFG_LINK_SKIP_REGANG_LIST,
(UINT8 **)CFG_ADDITIONAL_TOPOLOGIES_LIST,
(SYSTEM_PHYSICAL_SOCKET_MAP *)CFG_SYSTEM_PHYSICAL_SOCKET_MAP
};
#ifndef HT_OPTIONS_PLATFORM
#define HT_OPTIONS_PLATFORM &HtOptionsPlatform
#endif
/**
* A list of all the supported topologies.
*
*/
#ifndef INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
CONST UINT8 *CONST ROMDATA AmdTopolist[] =
{
amdHtTopologySingleNode,
amdHtTopologyDualNode,
amdHtTopologyThreeLine,
amdHtTopologyTriangle,
amdHtTopologyFourLine,
amdHtTopologyFourStar,
amdHtTopologyFourDegenerate,
amdHtTopologyFourSquare,
amdHtTopologyFourKite,
amdHtTopologyFourFully,
amdHtTopologyFiveFully,
amdHtTopologyFiveTwistedLadder,
amdHtTopologySixFully,
amdHtTopologySixDoubloonLower,
amdHtTopologySixDoubloonUpper,
amdHtTopologySixTwistedLadder,
amdHtTopologySevenFully,
amdHtTopologySevenTwistedLadder,
amdHtTopologyEightFully,
amdHtTopologyEightDoubloon,
amdHtTopologyEightTwistedLadder,
amdHtTopologyEightStraightLadder,
amdHtTopologySixTwinTriangles,
amdHtTopologyEightTwinFullyFourWays,
NULL
};
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES AmdTopolist
#endif
/**
* Declare the instance of the Ht option configuration structure
*/
CONST OPTION_HT_CONFIGURATION ROMDATA OptionHtConfiguration = {
OPTION_IS_RECOVERY_HT,
CFG_SET_HTCRC_SYNC_FLOOD,
CFG_USE_UNIT_ID_CLUMPING,
HT_OPTIONS_PLATFORM,
INTERNAL_HT_OPTION_INTERFACE,
INTERNAL_HT_OPTION_FEATURES,
&HtInstalledFamilyNorthbridgeList,
INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
};
#endif
#endif
#ifndef OPTION_HT_INIIT_RESET_ENTRY
#define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
#if OPTION_FAMILY14H == TRUE
#undef OPTION_HT_INIIT_RESET_ENTRY
#undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
#define OPTION_HT_INIIT_RESET_ENTRY NULL
#define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY NULL
#endif
#endif
#ifdef AGESA_ENTRY_INIT_RESET
#if AGESA_ENTRY_INIT_RESET == TRUE
CONST AMD_HT_RESET_INTERFACE ROMDATA HtOptionResetDefaults = {
(MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
0 // Unused by options
};
CONST OPTION_HT_INIT_RESET ROMDATA HtOptionInitReset = {
OPTION_HT_INIIT_RESET_ENTRY,
OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
};
#endif
#endif
#endif // _OPTION_HT_INSTALL_H_

69
src/vendorcode/amd/agesa/f14/Config/OptionHwC1eInstall.h
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@@ -1,69 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: HW C1e
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_HW_C1E_INSTALL_H_
#define _OPTION_HW_C1E_INSTALL_H_
#include "cpuHwC1e.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_HW_C1E_FEAT
#if AGESA_ENTRY_INIT_EARLY == TRUE
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HwC1eFamilyServiceArray[] =
{
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HwC1eFamilyServiceTable =
{
(sizeof (HwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&HwC1eFamilyServiceArray[0]
};
#endif
#endif // _OPTION_HW_C1E_INSTALL_H_

281
src/vendorcode/amd/agesa/f14/Config/OptionIdsInstall.h
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@@ -1,281 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* IDS Option Install File
*
* This file generates the defaults tables for family 10h model 5 processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_IDS_INSTALL_H_
#define _OPTION_IDS_INSTALL_H_
#include "Ids.h"
#include "IdsHt.h"
#include "IdsLib.h"
#ifdef __IDS_EXTENDED__
#include OPTION_IDS_EXT_INSTALL_FILE
#endif
#define IDS_LATE_RUN_AP_TASK
#define M_HTIDS_PORT_OVERRIDE_HOOK (PF_HtIdsGetPortOverride)CommonVoid
#if (IDSOPT_IDS_ENABLED == TRUE)
#if (IDSOPT_CONTROL_ENABLED == TRUE)
// Check for all families which include HT Features.
#endif
#endif // OPTION_IDS_LEVEL
CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVERRIDE_HOOK;
#if (IDSOPT_IDS_ENABLED == TRUE)
#if (AGESA_ENTRY_INIT_LATE == TRUE)
#undef IDS_LATE_RUN_AP_TASK
#define IDS_LATE_RUN_AP_TASK
#endif
#endif // OPTION_IDS_LEVEL
#if (IDSOPT_TRACING_ENABLED == TRUE)
#if (AGESA_ENTRY_INIT_POST == TRUE)
#include <mu.h>
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
{ (UINTN) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"},
{ (UINTN) MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"},
{ (UINTN) MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"}
};
#else
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
{ (UINTN) CommonReturnFalse, "DefRet()"},
{ (UINTN) CommonReturnFalse, "DefRet()"},
{ (UINTN) CommonReturnFalse, "DefRet()"}
};
#endif
#endif
///Ids Feat Options
#if (IDSOPT_IDS_ENABLED == TRUE)
#if (IDSOPT_CONTROL_ENABLED == TRUE)
#ifndef OPTION_IDS_EXTEND_FEATS
#define OPTION_IDS_EXTEND_FEATS
#endif
#define OPTION_IDS_FEAT_GNB_PLATFORMCFG\
OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
/*----------------------------------------------------------------------------
* Family 14 feat blocks
*
*----------------------------------------------------------------------------
*/
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF14;
#undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 &IdsFeatGnbPlatformCfgBlockF14,
#endif
#endif
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatUcodeBlock =
{
IDS_FEAT_UCODE_UPDATE,
IDS_ALL_CORES,
IDS_UCODE,
IDS_FAMILY_ALL,
IdsSubUCode
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatPowerPolicyBlock =
{
IDS_FEAT_POWER_POLICY,
IDS_ALL_CORES,
IDS_PLATFORMCFG_OVERRIDE,
IDS_FAMILY_ALL,
IdsSubPowerPolicyOverride
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatTargetPstateBlock =
{
IDS_FEAT_TARGET_PSTATE,
IDS_BSP_ONLY,
IDS_INIT_LATE_AFTER,
IDS_FAMILY_ALL,
IdsSubTargetPstate
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatPostPstateBlock =
{
IDS_FEAT_POSTPSTATE,
IDS_ALL_CORES,
IDS_CPU_Early_Override,
IDS_FAMILY_ALL,
IdsSubPostPState
};
//Dram controller Features
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctAllMemClkBlock =
{
IDS_FEAT_DCT_ALLMEMCLK,
IDS_BSP_ONLY,
IDS_ALL_MEMORY_CLOCK,
IDS_FAMILY_ALL,
IdsSubAllMemClkEn
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctGangModeBlock =
{
IDS_FEAT_DCT_GANGMODE,
IDS_BSP_ONLY,
IDS_GANGING_MODE,
IDS_FAMILY_ALL,
IdsSubGangingMode
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctBurstLengthBlock =
{
IDS_FEAT_DCT_BURSTLENGTH,
IDS_BSP_ONLY,
IDS_BURST_LENGTH32,
AMD_FAMILY_10,
IdsSubBurstLength32
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownCtrlBlock =
{
IDS_FEAT_DCT_POWERDOWN,
IDS_BSP_ONLY,
IDS_INIT_POST_BEFORE,
IDS_FAMILY_ALL,
IdsSubPowerDownCtrl
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctDllShutDownBlock =
{
IDS_FEAT_DCT_DLLSHUTDOWN,
IDS_BSP_ONLY,
IDS_DLL_SHUT_DOWN,
IDS_FAMILY_ALL,
IdsSubDllShutDownSR
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownModeBlock =
{
IDS_FEAT_DCT_POWERDOWN,
IDS_BSP_ONLY,
IDS_POWERDOWN_MODE,
IDS_FAMILY_ALL,
IdsSubPowerDownMode
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHdtOutBlock =
{
IDS_FEAT_HDTOUT,
IDS_BSP_ONLY,
IDS_INIT_EARLY_BEFORE,
IDS_FAMILY_ALL,
IdsSubHdtOut
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtSettingBlock =
{
IDS_FEAT_HT_SETTING,
IDS_BSP_ONLY,
IDS_HT_CONTROL,
IDS_FAMILY_ALL,
IdsSubHtLinkControl
};
CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] =
{
&IdsFeatUcodeBlock,
&IdsFeatPowerPolicyBlock,
&IdsFeatTargetPstateBlock,
&IdsFeatPostPstateBlock,
OPTION_IDS_FEAT_ECCSYMBOLSIZE
OPTION_IDS_FEAT_ECCCTRL
&IdsFeatDctAllMemClkBlock,
&IdsFeatDctGangModeBlock,
&IdsFeatDctBurstLengthBlock,
&IdsFeatDctPowerDownCtrlBlock,
&IdsFeatDctPowerDownModeBlock,
&IdsFeatDctPowerDownModeBlock,
OPTION_IDS_FEAT_HT_ASSIST
&IdsFeatHdtOutBlock,
&IdsFeatHtSettingBlock,
OPTION_IDS_FEAT_GNB_PLATFORMCFG
OPTION_IDS_FEAT_CPB_CTRL
OPTION_IDS_FEAT_HTC_CTRL
OPTION_IDS_FEAT_MEMORY_MAPPING
OPTION_IDS_EXTEND_FEATS
NULL
};
#else
CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] =
{
NULL
};
#endif//IDSOPT_CONTROL_ENABLED
#else
CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] =
{
NULL
};
#endif// IDSOPT_IDS_ENABLED
#endif

91
src/vendorcode/amd/agesa/f14/Config/OptionIoCstateInstall.h
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@@ -1,91 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: IO C-state
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_IO_CSTATE_INSTALL_H_
#define _OPTION_IO_CSTATE_INSTALL_H_
#include "cpuIoCstate.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_IO_CSTATE_FEAT
#define F14_IO_CSTATE_SUPPORT
#if OPTION_IO_CSTATE == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
#if OPTION_FAMILY14H_ON == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
#undef OPTION_IO_CSTATE_FEAT
#define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F14IoCstateSupport;
#undef F14_IO_CSTATE_SUPPORT
#define F14_IO_CSTATE_SUPPORT {AMD_FAMILY_14_ON, &F14IoCstateSupport},
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA IoCstateFamilyServiceArray[] =
{
F14_IO_CSTATE_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA IoCstateFamilyServiceTable =
{
(sizeof (IoCstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&IoCstateFamilyServiceArray[0]
};
#endif // _OPTION_IO_CSTATE_INSTALL_H_

74
src/vendorcode/amd/agesa/f14/Config/OptionLowPwrPstateInstall.h
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@@ -1,74 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Low Power Pstate for PROCHOT_L Throttling.
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_LOW_PWR_PSTATE_INSTALL_H_
#define _OPTION_LOW_PWR_PSTATE_INSTALL_H_
#include "cpuLowPwrPstate.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT
#if OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA LowPwrPstateFamilyServiceArray[] =
{
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA LowPwrPstateFamilyServiceTable =
{
(sizeof (LowPwrPstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&LowPwrPstateFamilyServiceArray[0]
};
#endif // _OPTION_LOW_PWR_PSTATE_INSTALL_H_

784
src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h
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@@ -1,784 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Memory
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 37402 $ @e \$Date: 2010-09-03 05:36:02 +0800 (Fri, 03 Sep 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_MEMORY_INSTALL_H_
#define _OPTION_MEMORY_INSTALL_H_
/*-------------------------------------------------------------------------------
* This option file is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
/*----------------------------------------------------------------------------------
* FEATURE BLOCK FUNCTIONS
*
* This section defines function names that depend upon options that are selected
* in the platform solution install file.
*/
BOOLEAN MemFDefRet (
IN OUT MEM_NB_BLOCK *NBPtr
)
{
return FALSE;
}
BOOLEAN MemMDefRet (
IN MEM_MAIN_DATA_BLOCK *MMPtr
)
{
return TRUE;
}
BOOLEAN MemMDefRetFalse (
IN MEM_MAIN_DATA_BLOCK *MMPtr
)
{
return FALSE;
}
/* -----------------------------------------------------------------------------*/
/**
*
*
* This function initializes the northbridge block for dimm identification translator
*
* @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
* @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
* @param[in,out] NodeID - ID of current node to construct
* @return TRUE - This is the correct constructor for the targeted node.
* @return FALSE - This isn't the correct constructor for the targeted node.
*/
BOOLEAN MemNIdentifyDimmConstructorRetDef (
IN OUT MEM_NB_BLOCK *NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
)
{
return FALSE;
}
/*----------------------------------------------------------------------------------
* TABLE FEATURE BLOCK FUNCTIONS
*
* This section defines function names that depend upon options that are selected
* in the platform solution install file.
*/
UINT8 MemFTableDefRet (
IN OUT MEM_TABLE_ALIAS **MTPtr
)
{
return 0;
}
/*----------------------------------------------------------------------------------
* FEATURE S3 BLOCK FUNCTIONS
*
* This section defines function names that depend upon options that are selected
* in the platform solution install file.
*/
BOOLEAN MemFS3DefConstructorRet (
IN OUT VOID *S3NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
)
{
return TRUE;
}
#if (OPTION_MEMCTLR_ON == TRUE)
#if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
#if (OPTION_S3_MEM_SUPPORT == TRUE)
extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockON;
#define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemS3ResumeConstructNBBlockON
#else
#define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemFS3DefConstructorRet
#endif
#else
#define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemFS3DefConstructorRet
#endif
#if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorON;
#define MEM_IDENDIMM_ON MemNIdentifyDimmConstructorON
#else
#define MEM_IDENDIMM_ON MemNIdentifyDimmConstructorRetDef
#endif
#endif
/*----------------------------------------------------------------------------------
* NORTHBRIDGE BLOCK CONSTRUCTOR AND INITIALIZER FUNCTION DEFAULT ASSIGNMENTS
*
*----------------------------------------------------------------------------------
*/
#define MEM_NB_SUPPORT_ON
#define MEM_NB_SUPPORT_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0, 0, 0 }
#if (AGESA_ENTRY_INIT_POST == TRUE)
/*----------------------------------------------------------------------------------
* FLOW CONTROL FUNCTION
*
* This section selects the function that controls the memory initialization sequence
* based upon the number of processor families that the BIOS will support.
*/
extern MEM_FLOW_CFG MemMFlowDef;
#if (OPTION_MEMCTLR_ON == TRUE)
extern MEM_FLOW_CFG MemMFlowON;
#define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowON,
#else
#define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowDef,
#endif
MEM_FLOW_CFG* CONST memFlowControlInstalled[] = {
MEM_MAIN_FLOW_CONTROL_PTR_ON
NULL
};
#if (OPTION_ONLINE_SPARE == TRUE)
extern OPTION_MEM_FEATURE_MAIN MemMOnlineSpare;
#define MEM_MAIN_FEATURE_ONLINE_SPARE MemMOnlineSpare
extern OPTION_MEM_FEATURE_NB MemFOnlineSpare;
#define MEM_FEATURE_ONLINE_SPARE MemFOnlineSpare
#else
#define MEM_MAIN_FEATURE_ONLINE_SPARE MemMDefRet
#define MEM_FEATURE_ONLINE_SPARE MemFDefRet
#endif
#if (OPTION_MEM_RESTORE == TRUE)
extern OPTION_MEM_FEATURE_MAIN MemMContextSave;
extern OPTION_MEM_FEATURE_MAIN MemMContextRestore;
#define MEM_MAIN_FEATURE_MEM_SAVE MemMContextSave
#define MEM_MAIN_FEATURE_MEM_RESTORE MemMContextRestore
#else
#define MEM_MAIN_FEATURE_MEM_SAVE MemMDefRet
#define MEM_MAIN_FEATURE_MEM_RESTORE MemMDefRetFalse
#endif
#if (OPTION_BANK_INTERLEAVE == TRUE)
extern OPTION_MEM_FEATURE_NB MemFInterleaveBanks;
#define MEM_FEATURE_BANK_INTERLEAVE MemFInterleaveBanks
extern OPTION_MEM_FEATURE_NB MemFUndoInterleaveBanks;
#define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFUndoInterleaveBanks
#else
#define MEM_FEATURE_BANK_INTERLEAVE MemFDefRet
#define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFDefRet
#endif
#if (OPTION_NODE_INTERLEAVE == TRUE)
extern OPTION_MEM_FEATURE_MAIN MemMInterleaveNodes;
#define MEM_MAIN_FEATURE_NODE_INTERLEAVE MemMInterleaveNodes
extern OPTION_MEM_FEATURE_NB MemFCheckInterleaveNodes;
extern OPTION_MEM_FEATURE_NB MemFInterleaveNodes;
#define MEM_FEATURE_NODE_INTERLEAVE_CHECK MemFCheckInterleaveNodes
#define MEM_FEATURE_NODE_INTERLEAVE MemFInterleaveNodes
#else
#define MEM_FEATURE_NODE_INTERLEAVE_CHECK MemFDefRet
#define MEM_FEATURE_NODE_INTERLEAVE MemFDefRet
#define MEM_MAIN_FEATURE_NODE_INTERLEAVE MemMDefRet
#endif
#if (OPTION_DCT_INTERLEAVE == TRUE)
extern OPTION_MEM_FEATURE_NB MemFInterleaveChannels;
#define MEM_FEATURE_CHANNEL_INTERLEAVE MemFInterleaveChannels
#else
#define MEM_FEATURE_CHANNEL_INTERLEAVE MemFDefRet
#endif
#if (OPTION_ECC == TRUE)
extern OPTION_MEM_FEATURE_MAIN MemMEcc;
#define MEM_MAIN_FEATURE_ECC MemMEcc
extern OPTION_MEM_FEATURE_NB MemFCheckECC;
extern OPTION_MEM_FEATURE_NB MemFInitECC;
#define MEM_FEATURE_CK_ECC MemFCheckECC
#define MEM_FEATURE_ECC MemFInitECC
#define MEM_FEATURE_ECCX8 MemMDefRet
#else
#define MEM_MAIN_FEATURE_ECC MemMDefRet
#define MEM_FEATURE_CK_ECC MemFDefRet
#define MEM_FEATURE_ECC MemFDefRet
#define MEM_FEATURE_ECCX8 MemMDefRet
#endif
extern OPTION_MEM_FEATURE_MAIN MemMMctMemClr;
#define MEM_MAIN_FEATURE_MEM_CLEAR MemMMctMemClr
#if (OPTION_DMI == TRUE)
#if (OPTION_DDR3 == TRUE)
extern OPTION_MEM_FEATURE_MAIN MemFDMISupport3;
#define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport3
#else
extern OPTION_MEM_FEATURE_MAIN MemFDMISupport2;
#define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport2
#endif
#else
#define MEM_MAIN_FEATURE_MEM_DMI MemMDefRet
#endif
#if (OPTION_DDR3 == TRUE)
extern OPTION_MEM_FEATURE_NB MemFOnDimmThermal;
extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3;
extern OPTION_MEM_FEATURE_NB MemFLvDdr3;
#define MEM_FEATURE_ONDIMMTHERMAL MemFOnDimmThermal
#define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3
#define MEM_FEATURE_LVDDR3 MemFLvDdr3
#else
#define MEM_FEATURE_ONDIMMTHERMAL MemFDefRet
#define MEM_MAIN_FEATURE_LVDDR3 MemMDefRet
#define MEM_FEATURE_LVDDR3 MemFDefRet
#endif
extern OPTION_MEM_FEATURE_NB MemFInterleaveRegion;
#define MEM_FEATURE_REGION_INTERLEAVE MemFInterleaveRegion
extern OPTION_MEM_FEATURE_MAIN MemMUmaAlloc;
#define MEM_MAIN_FEATURE_UMAALLOC MemMUmaAlloc
extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
#if (OPTION_PARALLEL_TRAINING == TRUE)
extern OPTION_MEM_FEATURE_MAIN MemMParallelTraining;
#define MEM_MAIN_FEATURE_TRAINING MemMParallelTraining
#else
#define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining
#endif
#if (OPTION_DIMM_EXCLUDE == TRUE)
extern OPTION_MEM_FEATURE_MAIN MemMRASExcludeDIMM;
#define MEM_MAIN_FEATURE_DIMM_EXCLUDE MemMRASExcludeDIMM
extern OPTION_MEM_FEATURE_NB MemFRASExcludeDIMM;
#define MEM_FEATURE_DIMM_EXCLUDE MemFRASExcludeDIMM
#else
#define MEM_FEATURE_DIMM_EXCLUDE MemFDefRet
#define MEM_MAIN_FEATURE_DIMM_EXCLUDE MemMDefRet
#endif
/*----------------------------------------------------------------------------------
* TECHNOLOGY BLOCK CONSTRUCTOR FUNCTION ASSIGNMENTS
*
*----------------------------------------------------------------------------------
*/
#if OPTION_DDR3 == TRUE
extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock3;
#define MEM_TECH_CONSTRUCTOR_DDR3 MemConstructTechBlock3,
#if (OPTION_HW_DRAM_INIT == TRUE)
extern MEM_TECH_FEAT MemTDramInitHw;
#define MEM_TECH_FEATURE_HW_DRAMINIT MemTDramInitHw
#else
#define MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef
#endif
#if (OPTION_SW_DRAM_INIT == TRUE)
// extern MEM_TECH_FEAT MemTDramInitSw3;
#define MEM_TECH_FEATURE_SW_DRAMINIT MemTDramInitSw3
#else
#define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef
#endif
#else
#define MEM_TECH_CONSTRUCTOR_DDR3
#endif
/*---------------------------------------------------------------------------------------------------
* FEATURE BLOCKS
*
* This section instantiates a feature block structure for each memory controller installed
* by the platform solution install file.
*---------------------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------------------
* ONTARIO FEATURE BLOCK
*---------------------------------------------------------------------------------------------------
*/
#if (OPTION_MEMCTLR_ON == TRUE)
#if OPTION_DDR3
#undef MEM_TECH_FEATURE_DRAMINIT
#define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
#endif
#if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
extern OPTION_MEM_FEATURE_NB MemNInitCPGClientNb;
#undef MEM_TECH_FEATURE_CPG
#define MEM_TECH_FEATURE_CPG MemNInitCPGClientNb
#else
#undef MEM_TECH_FEATURE_CPG
#define MEM_TECH_FEATURE_CPG MemFDefRet
#endif
#if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
#undef MEM_TECH_FEATURE_HWRXEN
#define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb
#else
extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
#undef MEM_TECH_FEATURE_HWRXEN
#define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb
#endif
#undef MEM_MAIN_FEATURE_TRAINING
#undef MEM_FEATURE_TRAINING
#define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining
extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
#define MEM_FEATURE_TRAINING MemFStandardTraining
#if (OPTION_EARLY_SAMPLES == TRUE)
extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportON;
#define MEM_EARLY_SAMPLE_SUPPORT MemNInitEarlySampleSupportON
#else
#define MEM_EARLY_SAMPLE_SUPPORT MemFDefRet
#endif
CONST MEM_FEAT_BLOCK_NB MemFeatBlockOn = {
MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
MemFDefRet,
MEM_FEATURE_BANK_INTERLEAVE,
MEM_FEATURE_UNDO_BANK_INTERLEAVE,
MemFDefRet,
MemFDefRet,
MemFDefRet,
MemFDefRet,
MemFDefRet,
MemFDefRet,
MEM_FEATURE_TRAINING,
MEM_FEATURE_LVDDR3,
MEM_FEATURE_ONDIMMTHERMAL,
MEM_TECH_FEATURE_DRAMINIT,
MEM_FEATURE_DIMM_EXCLUDE,
MEM_EARLY_SAMPLE_SUPPORT,
MEM_TECH_FEATURE_CPG,
MEM_TECH_FEATURE_HWRXEN
};
#undef MEM_NB_SUPPORT_ON
extern MEM_NB_CONSTRUCTOR MemConstructNBBlockON;
extern MEM_INITIALIZER MemNInitDefaultsON;
#define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockON, MemNInitDefaultsON, &MemFeatBlockOn, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON },
#endif // OPTION_MEMCTRL_ON
/*---------------------------------------------------------------------------------------------------
* MAIN FEATURE BLOCK
*---------------------------------------------------------------------------------------------------
*/
CONST MEM_FEAT_BLOCK_MAIN MemFeatMain = {
MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION,
MEM_MAIN_FEATURE_TRAINING,
MEM_MAIN_FEATURE_DIMM_EXCLUDE,
MEM_MAIN_FEATURE_ONLINE_SPARE,
MEM_MAIN_FEATURE_NODE_INTERLEAVE,
MEM_MAIN_FEATURE_ECC,
MEM_MAIN_FEATURE_MEM_CLEAR,
MEM_MAIN_FEATURE_MEM_DMI,
MEM_MAIN_FEATURE_LVDDR3,
MEM_MAIN_FEATURE_UMAALLOC,
MEM_MAIN_FEATURE_MEM_SAVE,
MEM_MAIN_FEATURE_MEM_RESTORE
};
/*---------------------------------------------------------------------------------------------------
* Technology Training SPECIFIC CONFIGURATION
*
*
*---------------------------------------------------------------------------------------------------
*/
#if OPTION_MEMCTLR_ON
extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceON;
#if OPTION_DDR3
#undef TECH_TRAIN_ENTER_HW_TRN_DDR3
#define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
#undef TECH_TRAIN_EXIT_HW_TRN_DDR3
#define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTrainingClient3
#if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
#define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1
#define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2
#else
#define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
#define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
#endif
#define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
#if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
#define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1
#define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2
#else
#define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
#define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
#endif
#if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
#define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1
#else
#define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
#endif
#undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3
#if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
#define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1
#else
#define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
#endif
#if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
#define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
#else
#define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
#endif
#if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
#define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
#else
#define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
#endif
#if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
#define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency
#else
#define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
#endif
CONST MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3ON = {
MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
TECH_TRAIN_ENTER_HW_TRN_DDR3,
TECH_TRAIN_SW_WL_DDR3,
TECH_TRAIN_HW_WL_P1_DDR3,
TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
TECH_TRAIN_HW_WL_P2_DDR3,
TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
TECH_TRAIN_EXIT_HW_TRN_DDR3,
TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
TECH_TRAIN_MAX_RD_LAT_DDR3
};
// extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
#define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb
// extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
#define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceON, &memTechTrainingFeatSequenceDDR3ON },
#else
#undef TECH_TRAIN_ENTER_HW_TRN_DDR3
#define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
#undef TECH_TRAIN_EXIT_HW_TRN_DDR3
#define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
#define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
#define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
#define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
#define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
#define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
#define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
#define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
#define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
#define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
#define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
#define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
#define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
#endif
#else
#define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
#endif
#define MEM_TECH_ENABLE_TRAINING_SEQUENCE_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0 }
CONST MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON
MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
};
/*---------------------------------------------------------------------------------------------------
* NB TRAINING FLOW CONTROL
*
*
*---------------------------------------------------------------------------------------------------
*/
#define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
OPTION_MEM_FEATURE_NB* CONST memNTrainFlowControl[] = { // Training flow control
NB_TRAIN_FLOW_DDR2,
NB_TRAIN_FLOW_DDR3,
};
/*---------------------------------------------------------------------------------------------------
* TECHNOLOGY BLOCK
*
*
*---------------------------------------------------------------------------------------------------
*/
MEM_TECH_CONSTRUCTOR* CONST memTechInstalled[] = { // Types of technology installed
MEM_TECH_CONSTRUCTOR_DDR3
NULL
};
/*---------------------------------------------------------------------------------------------------
* PLATFORM SPECIFIC BLOCK FORM FACTOR DEFINITION
*
*
*---------------------------------------------------------------------------------------------------
*/
#if OPTION_MEMCTLR_ON
#if OPTION_UDIMMS
#if OPTION_DDR3
#define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUON3,
#else
#define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef,
#endif
#else
#define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef,
#endif
#if OPTION_SODIMMS
#if OPTION_DDR3
#define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsSON3,
#else
#define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef,
#endif
#else
#define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef,
#endif
#else
#define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef,
#define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef,
#endif
MEM_PLAT_SPEC_CFG* CONST memPlatSpecFFInstalledON[MAX_FF_TYPES] = {
PLAT_SP_ON_FF_SDIMM3
PLAT_SP_ON_FF_UDIMM3
NULL
};
/*---------------------------------------------------------------------------------------------------
* PLATFORM-SPECIFIC CONFIGURATION
*
*
*---------------------------------------------------------------------------------------------------
*/
#if OPTION_MEMCTLR_ON
#if OPTION_UDIMMS
#if OPTION_DDR3
#define PSC_ON_UDIMM_DDR3 MemAGetPsCfgUON3,
#else
#define PSC_ON_UDIMM_DDR3
#endif
#endif
#if OPTION_RDIMMS
#if OPTION_DDR3
#define PSC_ON_RDIMM_DDR3 //MemAGetPsCfgRON3,
#else
#define PSC_ON_RDIMM_DDR3
#endif
#endif
#if OPTION_SODIMMS
#if OPTION_DDR3
#define PSC_ON_SODIMM_DDR3 MemAGetPsCfgSON3,
#else
#define PSC_ON_SODIMM_DDR3
#endif
#endif
#endif
/*----------------------------------------------------------------------
* DEFAULT PSCFG DEFINITIONS
*
*----------------------------------------------------------------------
*/
#ifndef PSC_ON_UDIMM_DDR3
#define PSC_ON_UDIMM_DDR3
#endif
#ifndef PSC_ON_RDIMM_DDR3
#define PSC_ON_RDIMM_DDR3
#endif
#ifndef PSC_ON_SODIMM_DDR3
#define PSC_ON_SODIMM_DDR3
#endif
MEM_PLATFORM_CFG* CONST memPlatformTypeInstalled[] = {
PSC_ON_UDIMM_DDR3
PSC_ON_RDIMM_DDR3
PSC_ON_SODIMM_DDR3
NULL
};
CONST UINTN SIZE_OF_PLATFORM = (sizeof (memPlatformTypeInstalled) / sizeof (MEM_PLATFORM_CFG*));
// #if SIZE_OF_PLATFORM > MAX_PLATFORM_TYPES
// #error Size of memPlatformTypeInstalled array larger than MAX_PLATFORM_TYPES
// #endif
/*---------------------------------------------------------------------------------------------------
* EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
*
*
*---------------------------------------------------------------------------------------------------
*/
#define MEM_PSC_FLOW_BLOCK_END NULL
#define PSC_TBL_END NULL
#define MEM_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue
MEM_PSC_FLOW_BLOCK* CONST memPlatSpecFlowArray[] = {
MEM_PSC_FLOW_BLOCK_END
};
/*---------------------------------------------------------------------------------------------------
*
* LRDIMM CONTROL
*
*---------------------------------------------------------------------------------------------------
*/
#if (OPTION_LRDIMMS == TRUE)
#define MEM_TECH_FEATURE_LRDIMM_INIT MemTFeatDef
#else //#if (OPTION_LRDIMMS == FALSE)
#define MEM_TECH_FEATURE_LRDIMM_INIT MemTFeatDef
#endif
CONST MEM_TECH_LRDIMM memLrdimmSupported = {
MEM_TECH_LRDIMM_STRUCT_VERSION,
MEM_TECH_FEATURE_LRDIMM_INIT
};
#else
/*---------------------------------------------------------------------------------------------------
* MAIN FLOW CONTROL
*
*
*---------------------------------------------------------------------------------------------------
*/
MEM_FLOW_CFG* CONST memFlowControlInstalled[] = {
NULL
};
/*---------------------------------------------------------------------------------------------------
* NB TRAINING FLOW CONTROL
*
*
*---------------------------------------------------------------------------------------------------
*/
OPTION_MEM_FEATURE_NB* CONST memNTrainFlowControl[] = { // Training flow control
NULL,
NULL,
};
/*---------------------------------------------------------------------------------------------------
* DEFAULT TECHNOLOGY BLOCK
*
*
*---------------------------------------------------------------------------------------------------
*/
MEM_TECH_CONSTRUCTOR* CONST memTechInstalled[] = { // Types of technology installed
NULL
};
/*---------------------------------------------------------------------------------------------------
* DEFAULT TECHNOLOGY MAP
*
*
*---------------------------------------------------------------------------------------------------
*/
CONST UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0};
/*---------------------------------------------------------------------------------------------------
* DEFAULT MAIN FEATURE BLOCK
*---------------------------------------------------------------------------------------------------
*/
CONST MEM_FEAT_BLOCK_MAIN MemFeatMain = {
0
};
/*---------------------------------------------------------------------------------------------------
* DEFAULT NORTHBRIDGE SUPPORT LIST
*
*
*---------------------------------------------------------------------------------------------------
*/
#if (OPTION_MEMCTLR_ON == TRUE)
#undef MEM_NB_SUPPORT_ON
#define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON },
#endif
/*---------------------------------------------------------------------------------------------------
* DEFAULT Technology Training
*
*
*---------------------------------------------------------------------------------------------------
*/
#if OPTION_DDR3
CONST MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR3 = {
0
};
CONST MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
{ 0 }
};
#endif
/*---------------------------------------------------------------------------------------------------
* DEFAULT Platform Specific list
*
*
*---------------------------------------------------------------------------------------------------
*/
#if (OPTION_MEMCTLR_ON == TRUE)
MEM_PLAT_SPEC_CFG* CONST memPlatSpecFFInstalledON[MAX_FF_TYPES] = {
NULL
};
#endif
/*----------------------------------------------------------------------
* DEFAULT PSCFG DEFINITIONS
*
*----------------------------------------------------------------------
*/
MEM_PLATFORM_CFG* CONST memPlatformTypeInstalled[] = {
NULL
};
/*----------------------------------------------------------------------
* EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
*
*----------------------------------------------------------------------
*/
MEM_PSC_FLOW_BLOCK* CONST memPlatSpecFlowArray[] = {
NULL
};
CONST MEM_TECH_LRDIMM memLrdimmSupported = {
MEM_TECH_LRDIMM_STRUCT_VERSION,
NULL
};
#endif
/*---------------------------------------------------------------------------------------------------
* NORTHBRIDGE SUPPORT LIST
*
*
*---------------------------------------------------------------------------------------------------
*/
CONST MEM_NB_SUPPORT memNBInstalled[] = {
MEM_NB_SUPPORT_ON
MEM_NB_SUPPORT_END
};
#endif // _OPTION_MEMORY_INSTALL_H_

71
src/vendorcode/amd/agesa/f14/Config/OptionMsgBasedC1eInstall.h
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@@ -1,71 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Message-Based C1e
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_MSG_BASED_C1E_INSTALL_H_
#define _OPTION_MSG_BASED_C1E_INSTALL_H_
#include "cpuMsgBasedC1e.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_MSG_BASED_C1E_FEAT
#if OPTION_MSG_BASED_C1E == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MsgBasedC1eFamilyServiceArray[] =
{
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MsgBasedC1eFamilyServiceTable =
{
(sizeof (MsgBasedC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&MsgBasedC1eFamilyServiceArray[0]
};
#endif
#endif
#endif // _OPTION_MSG_BASED_C1E_INSTALL_H_

92
src/vendorcode/amd/agesa/f14/Config/OptionMultiSocketInstall.h
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@@ -1,92 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Multiple Socket Support
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_MULTISOCKET_INSTALL_H_
#define _OPTION_MULTISOCKET_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#ifndef OPTION_MULTISOCKET
#error BLDOPT: Option not defined: "OPTION_MULTISOCKET"
#endif
#if OPTION_MULTISOCKET == TRUE
OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrMulti;
#define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrMulti
OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sMulti;
#define CORE0_PM_TASK RunCodeOnAllSystemCore0sMulti
OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofMulti;
#define GET_SYS_NB_COF GetSystemNbCofMulti
OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti;
#define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti
OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsMulti;
#define GET_EARLY_PM_ERRORS GetEarlyPmErrorsMulti
#else
OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrSingle;
#define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrSingle
OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sSingle;
#define CORE0_PM_TASK RunCodeOnAllSystemCore0sSingle
OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofSingle;
#define GET_SYS_NB_COF GetSystemNbCofSingle
OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle;
#define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle
OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsSingle;
#define GET_EARLY_PM_ERRORS GetEarlyPmErrorsSingle
#endif
/* Declare the instance of the DMI option configuration structure */
CONST OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration = {
MULTISOCKET_STRUCT_VERSION,
GET_NUM_PM_STEPS,
CORE0_PM_TASK,
GET_SYS_NB_COF,
GET_SYS_NB_COF_UPDATE,
GET_EARLY_PM_ERRORS
};
#endif // _OPTION_MULTISOCKET_INSTALL_H_

71
src/vendorcode/amd/agesa/f14/Config/OptionPreserveMailboxInstall.h
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@@ -1,71 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Preserve Mailbox
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_PRESERVE_MAILBOX_INSTALL_H_
#define _OPTION_PRESERVE_MAILBOX_INSTALL_H_
#include "PreserveMailbox.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_PRESERVE_MAILBOX_FEAT
#if ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PreserveMailboxFamilyServiceArray[] =
{
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PreserveMailboxFamilyServiceTable =
{
(sizeof (PreserveMailboxFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&PreserveMailboxFamilyServiceArray[0]
};
#endif
#endif // _OPTION_PRESERVE_MAILBOX_INSTALL_H_

215
src/vendorcode/amd/agesa/f14/Config/OptionPstateInstall.h
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@@ -1,215 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: PState
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_PSTATE_INSTALL_H_
#define _OPTION_PSTATE_INSTALL_H_
#include "cpuPstateTables.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define F14_PSTATE_SERVICE_SUPPORT
#if ((AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
//
//Define Pstate CPU Family service
//
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F14PstateServices;
#undef F14_PSTATE_SERVICE_SUPPORT
#define F14_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_14, &F14PstateServices},
#endif
#endif
//
//Define ACPI Pstate objects.
//
#ifndef OPTION_ACPI_PSTATES
#error BLDOPT: Option not defined: "OPTION_ACPI_PSTATES"
#endif
#if (OPTION_ACPI_PSTATES == TRUE)
// OPTION_SSDT_FEATURE GenerateSsdt;
#define USER_SSDT_MAIN GenerateSsdt
#ifndef OPTION_MULTISOCKET
#error BLDOPT: Option not defined: "OPTION_MULTISOCKET"
#endif
OPTION_ACPI_FEATURE CreatePStateAcpiTables;
OPTION_PSTATE_GATHER PStateGatherMain;
#if ((OPTION_MULTISOCKET == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE))
OPTION_PSTATE_LEVELING PStateLevelingMain;
#define USER_PSTATE_OPTION_LEVEL PStateLevelingMain
#else
OPTION_PSTATE_LEVELING PStateLevelingStub;
#define USER_PSTATE_OPTION_LEVEL PStateLevelingStub
#endif
#if AGESA_ENTRY_INIT_LATE == TRUE
#define USER_PSTATE_OPTION_MAIN CreatePStateAcpiTables
#else
OPTION_ACPI_FEATURE CreateAcpiTablesStub;
#define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub
#endif
#if AGESA_ENTRY_INIT_POST == TRUE
#define USER_PSTATE_OPTION_GATHER PStateGatherMain
#else
OPTION_PSTATE_GATHER PStateGatherStub;
#define USER_PSTATE_OPTION_GATHER PStateGatherStub
#endif
#if CFG_ACPI_PSTATES_PPC == TRUE
#define USER_PSTATE_CFG_PPC TRUE
#else
#define USER_PSTATE_CFG_PPC FALSE
#endif
#if CFG_ACPI_PSTATES_PCT == TRUE
#define USER_PSTATE_CFG_PCT TRUE
#else
#define USER_PSTATE_CFG_PCT FALSE
#endif
#if CFG_ACPI_PSTATES_PSD == TRUE
#define USER_PSTATE_CFG_PSD TRUE
#else
#define USER_PSTATE_CFG_PSD FALSE
#endif
#if CFG_ACPI_PSTATES_PSS == TRUE
#define USER_PSTATE_CFG_PSS TRUE
#else
#define USER_PSTATE_CFG_PSS FALSE
#endif
#if CFG_ACPI_PSTATES_XPSS == TRUE
#define USER_PSTATE_CFG_XPSS TRUE
#else
#define USER_PSTATE_CFG_XPSS FALSE
#endif
#if OPTION_IO_CSTATE == TRUE
OPTION_ACPI_FEATURE CreateCStateAcpiTables;
#define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables
#else
OPTION_ACPI_FEATURE CreateAcpiTablesStub;
#define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub
#endif
#else
OPTION_SSDT_FEATURE GenerateSsdtStub;
OPTION_ACPI_FEATURE CreateAcpiTablesStub;
OPTION_PSTATE_GATHER PStateGatherStub;
OPTION_PSTATE_LEVELING PStateLevelingStub;
#define USER_SSDT_MAIN GenerateSsdtStub
#define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub
#define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub
#define USER_PSTATE_OPTION_GATHER PStateGatherStub
#define USER_PSTATE_OPTION_LEVEL PStateLevelingStub
#define USER_PSTATE_CFG_PPC FALSE
#define USER_PSTATE_CFG_PCT FALSE
#define USER_PSTATE_CFG_PSD FALSE
#define USER_PSTATE_CFG_PSS FALSE
#define USER_PSTATE_CFG_XPSS FALSE
// If ACPI Objects are disabled for PStates, we still need to check
// whether ACPI Objects are enabled for CStates
#if OPTION_IO_CSTATE == TRUE
OPTION_SSDT_FEATURE GenerateSsdt;
OPTION_PSTATE_GATHER PStateGatherMain;
OPTION_ACPI_FEATURE CreateCStateAcpiTables;
#undef USER_SSDT_MAIN
#define USER_SSDT_MAIN GenerateSsdt
#undef USER_PSTATE_OPTION_GATHER
#define USER_PSTATE_OPTION_GATHER PStateGatherMain
#undef USER_CSTATE_OPTION_MAIN
#define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables
#endif
#endif
#else
OPTION_SSDT_FEATURE GenerateSsdtStub;
OPTION_ACPI_FEATURE CreateAcpiTablesStub;
OPTION_PSTATE_GATHER PStateGatherStub;
OPTION_PSTATE_LEVELING PStateLevelingStub;
#define USER_SSDT_MAIN GenerateSsdtStub
#define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub
#define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub
#define USER_PSTATE_OPTION_GATHER PStateGatherStub
#define USER_PSTATE_OPTION_LEVEL PStateLevelingStub
#define USER_PSTATE_CFG_PPC FALSE
#define USER_PSTATE_CFG_PCT FALSE
#define USER_PSTATE_CFG_PSD FALSE
#define USER_PSTATE_CFG_PSS FALSE
#define USER_PSTATE_CFG_XPSS FALSE
#endif
/* Declare the instance of the PSTATE option configuration structure */
CONST OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration = {
PSTATE_STRUCT_VERSION,
USER_PSTATE_OPTION_GATHER,
USER_PSTATE_OPTION_LEVEL
};
CONST OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration = {
PSTATE_STRUCT_VERSION,
USER_SSDT_MAIN,
USER_PSTATE_OPTION_MAIN,
USER_CSTATE_OPTION_MAIN,
USER_PSTATE_CFG_PPC,
USER_PSTATE_CFG_PCT,
USER_PSTATE_CFG_PSD,
USER_PSTATE_CFG_PSS,
USER_PSTATE_CFG_XPSS
};
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateCpuFamilyServiceArray[] =
{
F14_PSTATE_SERVICE_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateFamilyServiceTable =
{
(sizeof (PstateCpuFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&PstateCpuFamilyServiceArray[0]
};
#endif // _OPTION_PSTATE_INSTALL_H_

91
src/vendorcode/amd/agesa/f14/Config/OptionS3ScriptInstall.h
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@@ -1,91 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: S3SCRIPT
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_S3SCRIPT_INSTALL_H_
#define _OPTION_S3SCRIPT_INSTALL_H_
#include "S3SaveState.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#ifndef OPTION_S3SCRIPT
#define OPTION_S3SCRIPT FALSE //if not define assume PI not use script
#endif
#if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE)
#if OPTION_S3SCRIPT == TRUE
#define P_S3_SCRIPT_INIT S3ScriptInitState
#endif
#endif
#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
#if OPTION_S3SCRIPT == TRUE
#define P_S3_SCRIPT_RESTORE S3ScriptRestoreState
#endif
#endif
#ifndef P_S3_SCRIPT_INIT
#define P_S3_SCRIPT_INIT S3ScriptInitStateStub
#endif
#ifndef P_S3_SCRIPT_RESTORE
#define P_S3_SCRIPT_RESTORE S3ScriptInitStateStub
#undef GNB_S3_DISPATCH_FUNCTION_TABLE
#endif
#ifndef GNB_S3_DISPATCH_FUNCTION_TABLE
#define GNB_S3_DISPATCH_FUNCTION_TABLE
#endif
/* Declare the instance of the S3SCRIPT option configuration structure */
S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration = {
P_S3_SCRIPT_INIT,
P_S3_SCRIPT_RESTORE
};
S3_DISPATCH_FUNCTION_ENTRY S3DispatchFunctionTable [] = {
GNB_S3_DISPATCH_FUNCTION_TABLE
{0, NULL}
};
#endif // _OPTION_S3SCRIPT_INSTALL_H_

79
src/vendorcode/amd/agesa/f14/Config/OptionSlitInstall.h
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@@ -1,79 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: SLIT
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_SLIT_INSTALL_H_
#define _OPTION_SLIT_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#if AGESA_ENTRY_INIT_LATE == TRUE
#ifndef OPTION_SLIT
#error BLDOPT: Option not defined: "OPTION_SLIT"
#endif
#if OPTION_SLIT == TRUE
OPTION_SLIT_FEATURE GetAcpiSlitMain;
OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBuffer;
#define USER_SLIT_OPTION GetAcpiSlitMain
#define USER_SLIT_RELEASE_BUFFER ReleaseSlitBuffer
#else
OPTION_SLIT_FEATURE GetAcpiSlitStub;
OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub;
#define USER_SLIT_OPTION GetAcpiSlitStub
#define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub
#endif
#else
OPTION_SLIT_FEATURE GetAcpiSlitStub;
OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub;
#define USER_SLIT_OPTION GetAcpiSlitStub
#define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub
#endif
/* Declare the instance of the SLIT option configuration structure */
OPTION_SLIT_CONFIGURATION OptionSlitConfiguration = {
SLIT_STRUCT_VERSION,
USER_SLIT_OPTION,
USER_SLIT_RELEASE_BUFFER
};
#endif // _OPTION_SLIT_INSTALL_H_

73
src/vendorcode/amd/agesa/f14/Config/OptionSratInstall.h
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@@ -1,73 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: SRAT
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_SRAT_INSTALL_H_
#define _OPTION_SRAT_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#if AGESA_ENTRY_INIT_LATE == TRUE
#ifndef OPTION_SRAT
#error BLDOPT: Option not defined: "OPTION_SRAT"
#endif
#if OPTION_SRAT == TRUE
OPTION_SRAT_FEATURE GetAcpiSratMain;
#define USER_SRAT_OPTION GetAcpiSratMain
#else
OPTION_SRAT_FEATURE GetAcpiSratStub;
#define USER_SRAT_OPTION GetAcpiSratStub
#endif
#else
OPTION_SRAT_FEATURE GetAcpiSratStub;
#define USER_SRAT_OPTION GetAcpiSratStub
#endif
/* Declare the instance of the WHEA option configuration structure */
OPTION_SRAT_CONFIGURATION OptionSratConfiguration = {
SRAT_STRUCT_VERSION,
USER_SRAT_OPTION
};
#endif // _OPTION_WHEA_INSTALL_H_

66
src/vendorcode/amd/agesa/f14/Config/OptionSwC1eInstall.h
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@@ -1,66 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: SW C1e
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_SW_C1E_INSTALL_H_
#define _OPTION_SW_C1E_INSTALL_H_
#include "cpuSwC1e.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_SW_C1E_FEAT
#if AGESA_ENTRY_INIT_EARLY == TRUE
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA SwC1eFamilyServiceArray[] =
{
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA SwC1eFamilyServiceTable =
{
(sizeof (SwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&SwC1eFamilyServiceArray[0]
};
#endif
#endif // _OPTION_SW_C1E_INSTALL_H_

74
src/vendorcode/amd/agesa/f14/Config/OptionWheaInstall.h
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@@ -1,74 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: WHEA
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_WHEA_INSTALL_H_
#define _OPTION_WHEA_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#if AGESA_ENTRY_INIT_LATE == TRUE
#ifndef OPTION_WHEA
#error BLDOPT: Option not defined: "OPTION_WHEA"
#endif
#if OPTION_WHEA == TRUE
OPTION_WHEA_FEATURE GetAcpiWheaMain;
#define USER_WHEA_OPTION GetAcpiWheaMain
#else
OPTION_WHEA_FEATURE GetAcpiWheaStub;
#define USER_WHEA_OPTION GetAcpiWheaStub
#endif
#else
OPTION_WHEA_FEATURE GetAcpiWheaStub;
#define USER_WHEA_OPTION GetAcpiWheaStub
#endif
/* Declare the instance of the WHEA option configuration structure */
OPTION_WHEA_CONFIGURATION OptionWheaConfiguration = {
WHEA_STRUCT_VERSION,
USER_WHEA_OPTION
};
#endif // _OPTION_WHEA_INSTALL_H_

1584
src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h
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File diff suppressed because it is too large Load Diff

54
src/vendorcode/amd/agesa/f14/Dispatcher.h
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@@ -1,54 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Pushhigh Interface
*
* Contains interface to Pushhigh entry
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Legacy
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _DISPATCHER_H_
#define _DISPATCHER_H_
// AGESA function prototypes
AGESA_STATUS CALLCONV AmdAgesaDispatcher ( IN OUT VOID *ConfigPtr );
AGESA_STATUS CALLCONV AmdAgesaCallout ( IN UINT32 Func, IN UINTN Data, IN OUT VOID *ConfigPtr );
#endif // _DISPATCHER_H_

166
src/vendorcode/amd/agesa/f14/Include/AdvancedApi.h
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@@ -1,166 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Advanced API Interface for HT, Memory and CPU
*
* Contains additional declarations need to use HT, Memory and CPU Advanced interface, such as
* would be required by the basic interface implementations.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Include
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _ADVANCED_API_H_
#define _ADVANCED_API_H_
/*----------------------------------------------------------------------------
* HT FUNCTIONS PROTOTYPE
*
*----------------------------------------------------------------------------
*/
/**
* A constructor for the HyperTransport input structure.
*
* Sets inputs to valid, basic level, defaults.
*
* @param[in] StdHeader Opaque handle to standard config header
* @param[in] AmdHtInterface HT Interface structure to initialize.
*
* @retval AGESA_SUCCESS Constructors are not allowed to fail
*/
AGESA_STATUS
AmdHtInterfaceConstructor (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_INTERFACE *AmdHtInterface
);
/**
* The top level external interface for Hypertransport Initialization.
*
* Create our initial internal state, initialize the coherent fabric,
* initialize the non-coherent chains, and perform any required fabric tuning or
* optimization.
*
* @param[in] StdHeader Opaque handle to standard config header
* @param[in] PlatformConfiguration The platform configuration options.
* @param[in] AmdHtInterface HT Interface structure.
*
* @retval AGESA_SUCCESS Only information events logged.
* @retval AGESA_ALERT Sync Flood or CRC error logged.
* @retval AGESA_WARNING Example: expected capability not found
* @retval AGESA_ERROR logged events indicating some devices may not be available
* @retval AGESA_FATAL Mixed Family or MP capability mismatch
*
*/
AGESA_STATUS
AmdHtInitialize (
IN AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfiguration,
IN AMD_HT_INTERFACE *AmdHtInterface
);
/*----------------------------------------------------------------------------
* HT Recovery FUNCTIONS PROTOTYPE
*
*----------------------------------------------------------------------------
*/
/**
* A constructor for the HyperTransport input structure.
*
*/
AGESA_STATUS
AmdHtResetConstructor (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
);
/**
* Initialize HT at Reset for both Normal and Recovery.
*
*/
AGESA_STATUS
AmdHtInitReset (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
);
/**
* Initialize the Node and Socket maps for an AP Core.
*
*/
AGESA_STATUS
AmdHtInitRecovery (
IN AMD_CONFIG_PARAMS *StdHeader
);
///----------------------------------------------------------------------------
/// MEMORY FUNCTIONS PROTOTYPE
///
///----------------------------------------------------------------------------
AGESA_STATUS
AmdMemRecovery (
IN OUT MEM_DATA_STRUCT *MemPtr
);
AGESA_STATUS
AmdMemAuto (
IN OUT MEM_DATA_STRUCT *MemPtr
);
VOID
AmdMemInitDataStructDef (
IN OUT MEM_DATA_STRUCT *MemPtr,
IN OUT PLATFORM_CONFIGURATION *PlatFormConfig
);
VOID
memDefRet ( VOID );
BOOLEAN
memDefTrue ( VOID );
BOOLEAN
memDefFalse ( VOID );
VOID
MemRecDefRet ( VOID );
BOOLEAN
MemRecDefTrue ( VOID );
#endif // _ADVANCED_API_H_

124
src/vendorcode/amd/agesa/f14/Include/CommonReturns.h
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@@ -1,124 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Common Return routines.
*
* Routines which do nothing, returning a result (preferably some version of zero) which
* is consistent with "do nothing" or "default". Useful for function pointer tables.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Common
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*
*/
#ifndef _COMMON_RETURNS_H_
#define _COMMON_RETURNS_H_
/**
* Return True
*
* @retval True Default case, no special action
*/
BOOLEAN
CommonReturnTrue ( VOID );
/**
* Return False.
*
* @retval FALSE Default case, no special action
*/
BOOLEAN
CommonReturnFalse ( VOID );
/**
* Return (UINT8)zero.
*
*
* @retval zero None, or only case zero.
*/
UINT8
CommonReturnZero8 ( VOID );
/**
* Return (UINT32)zero.
*
*
* @retval zero None, or only case zero.
*/
UINT32
CommonReturnZero32 ( VOID );
/**
* Return (UINT64)zero.
*
*
* @retval zero None, or only case zero.
*/
UINT64
CommonReturnZero64 ( VOID );
/**
* Return NULL
*
* @retval NULL pointer to nothing
*/
VOID *
CommonReturnNULL ( VOID );
/**
* Return AGESA_SUCCESS.
*
* @retval AGESA_SUCCESS Success.
*/
AGESA_STATUS
CommonReturnAgesaSuccess ( VOID );
/**
* Do Nothing.
*
*/
VOID
CommonVoid ( VOID );
/**
* ASSERT if this routine is called.
*
*/
VOID
CommonAssert ( VOID );
#endif // _COMMON_RETURNS_H_

852
src/vendorcode/amd/agesa/f14/Include/Filecode.h
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@@ -1,852 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Collectively assign unique filecodes for assert and debug to each source file.
*
* Publish values for decorated filenames, which can be used for
* ASSERT and debug support using a preprocessor define like:
* @n <tt> \#define FILECODE MY_C_FILENAME_FILECODE </tt> @n
* This file serves as a reference for debugging to associate the code and filename.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Include
* @e \$Revision: 46485 $ @e \$Date: 2011-02-03 09:03:14 -0700 (Thu, 03 Feb 2011) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _FILECODE_H_
#define _FILECODE_H_
#define UNASSIGNED_FILE_FILECODE (0xFFFF)
/// For debug use in any Platform's options C file.
/// Can be reused for platforms and image builds, since only one options file can be built.
#define PLATFORM_SPECIFIC_OPTIONS_FILECODE (0xBBBB)
#define PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE (0xA001)
#define PROC_GNB_GFX_FAMILY_0X12_F12GFXSERVICES_FILECODE (0xA002)
#define PROC_GNB_GFX_FAMILY_0X14_F14GFXSERVICES_FILECODE (0xA003)
#define PROC_GNB_GFX_GFXCONFIGDATA_FILECODE (0xA004)
#define PROC_GNB_GFX_GFXDEBUGBAR_FILECODE (0xA005)
#define PROC_GNB_GFX_GFXGMCINIT_FILECODE (0xA006)
#define PROC_GNB_GFX_GFXINITATENVPOST_FILECODE (0xA010)
#define PROC_GNB_GFX_GFXINITATMIDPOST_FILECODE (0xA011)
#define PROC_GNB_GFX_GFXINITATPOST_FILECODE (0xA012)
#define PROC_GNB_GFX_GFXINTEGRATEDINFOTABLEINIT_FILECODE (0xA013)
#define PROC_GNB_GFX_GFXLIB_FILECODE (0xA014)
#define PROC_GNB_GFX_GFXREGISTERACC_FILECODE (0xA015)
#define PROC_GNB_GFX_GFXSTRAPSINIT_FILECODE (0xA016)
#define PROC_GNB_GNBINITATEARLY_FILECODE (0xA017)
#define PROC_GNB_GNBINITATENV_FILECODE (0xA020)
#define PROC_GNB_GNBINITATLATE_FILECODE (0xA021)
#define PROC_GNB_GNBINITATMID_FILECODE (0xA022)
#define PROC_GNB_GNBINITATPOST_FILECODE (0xA023)
#define PROC_GNB_GNBINITATRESET_FILECODE (0xA024)
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE (0xA025)
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE (0xA026)
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE (0xA027)
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE (0xA028)
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE (0xA029)
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE (0xA02A)
#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE (0xA030)
#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE (0xA031)
#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE (0xA032)
#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXPOWERPLAYTABLE_FILECODE (0xA033)
#define PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE (0xA034)
#define PROC_GNB_MODULES_GNBPCIEALIBV1_PCIEALIB_FILECODE (0xA035)
#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE (0xA036)
#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE (0xA037)
#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE (0xA038)
#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE (0xA039)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPM_FILECODE (0xA03A)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE (0xA03B)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE (0xA03C)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE (0xA03D)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE (0xA03E)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE (0xA03F)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE (0xA041)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE (0xA043)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESBLINK_FILECODE (0xA044)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE (0xA045)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE (0xA046)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE (0xA047)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE (0xA048)
#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE (0xA049)
#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIETRAINING_FILECODE (0xA04A)
#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIEWORKAROUNDS_FILECODE (0xA04B)
#define PROC_GNB_NB_FAMILY_0X12_F12NBPOWERGATE_FILECODE (0xA04C)
#define PROC_GNB_NB_FAMILY_0X12_F12NBSERVICES_FILECODE (0xA04D)
#define PROC_GNB_NB_FAMILY_0X12_F12NBSMU_FILECODE (0xA04E)
#define PROC_GNB_NB_FAMILY_0X14_F14NBLCLKNCLKRATIO_FILECODE (0xA04F)
#define PROC_GNB_NB_FAMILY_0X14_F14NBPOWERGATE_FILECODE (0xA050)
#define PROC_GNB_NB_FAMILY_0X14_F14NBSERVICES_FILECODE (0xA051)
#define PROC_GNB_NB_FAMILY_0X14_F14NBSMU_FILECODE (0xA052)
#define PROC_GNB_NB_FEATURE_NBFUSETABLE_FILECODE (0xA053)
#define PROC_GNB_NB_FEATURE_NBLCLKDPM_FILECODE (0xA054)
#define PROC_GNB_NB_FAMILY_0X12_F12NBLCLKDPM_FILECODE (0xA055)
#define PROC_GNB_NB_FAMILY_0X14_F14NBLCLKDPM_FILECODE (0xA056)
#define PROC_GNB_NB_NBCONFIGDATA_FILECODE (0xA060)
#define PROC_GNB_NB_NBINIT_FILECODE (0xA061)
#define PROC_GNB_NB_NBINITATEARLY_FILECODE (0xA062)
#define PROC_GNB_NB_NBINITATENV_FILECODE (0xA063)
#define PROC_GNB_NB_NBINITATLATEPOST_FILECODE (0xA070)
#define PROC_GNB_NB_NBINITATPOST_FILECODE (0xA071)
#define PROC_GNB_NB_NBINITATRESET_FILECODE (0xA072)
#define PROC_GNB_NB_NBPOWERMGMT_FILECODE (0xA073)
#define PROC_GNB_NB_NBSMULIB_FILECODE (0xA074)
#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEALIB_FILECODE (0xA075)
#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE (0xA076)
#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXSERVICES_FILECODE (0xA077)
#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEPHYSERVICES_FILECODE (0xA078)
#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEPIFSERVICES_FILECODE (0xA079)
#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEWRAPPERSERVICES_FILECODE (0xA07A)
#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEALIB_FILECODE (0xA07D)
#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIECOMPLEXCONFIG_FILECODE (0xA07E)
#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIECOMPLEXSERVICES_FILECODE (0xA07F)
#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEPHYSERVICES_FILECODE (0xA080)
#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEPIFSERVICES_FILECODE (0xA081)
#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEWRAPPERSERVICES_FILECODE (0xA082)
#define PROC_GNB_PCIE_FEATURE_PCIEPOWERGATE_FILECODE (0xA083)
#define PROC_GNB_PCIE_PCIEINIT_FILECODE (0xA084)
#define PROC_GNB_PCIE_PCIEINITATEARLYPOST_FILECODE (0xA085)
#define PROC_GNB_PCIE_PCIEINITATENV_FILECODE (0xA086)
#define PROC_GNB_PCIE_PCIEINITATLATEPOST_FILECODE (0xA087)
#define PROC_GNB_PCIE_PCIEINITATPOST_FILECODE (0xA088)
#define PROC_GNB_PCIE_PCIELATEINIT_FILECODE (0xA089)
#define PROC_GNB_PCIE_PCIEMISCLIB_FILECODE (0xA08A)
#define PROC_GNB_PCIE_PCIEPORTINIT_FILECODE (0xA08B)
#define PROC_GNB_PCIE_PCIEPORTLATEINIT_FILECODE (0xA08C)
#define PROC_GNB_MODULES_GNBCABLESAFE_GNBCABLESAFE_FILECODE (0xA08D)
#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE (0xA08E)
#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE (0xA08F)
#define PROC_RECOVERY_GNB_GNBRECOVERY_FILECODE (0xAE01)
#define PROC_RECOVERY_GNB_NBINITRECOVERY_FILECODE (0xAE02)
// FCH
#define PROC_COMMON_AMDFCH_FILECODE (0xB000)
#define PROC_FCH_AZALIA_AZALIA_FILECODE (0xB001)
#define PROC_FCH_AZALIA_AZALIARESET_FILECODE (0xB002)
#define PROC_FCH_COMMON_ACPILIB_FILECODE (0xB010)
#define PROC_FCH_COMMON_AMDSBLIB_FILECODE (0xB011)
#define PROC_FCH_COMMON_FCHCOMMON_FILECODE (0xB012)
#define PROC_FCH_COMMON_FCHCOMMONSMM_FILECODE (0xB013)
#define PROC_FCH_COMMON_MEMLIB_FILECODE (0xB014)
#define PROC_FCH_COMMON_PCILIB_FILECODE (0xB015)
#define PROC_FCH_COMMON_SBPELIB_FILECODE (0xB016)
#define PROC_FCH_GEC_FAMILY_HUDSON2_GEC_FILECODE (0xB020)
#define PROC_FCH_GEC_FAMILY_HUDSON2_GECRESET_FILECODE (0xB021)
#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HWACPI_FILECODE (0xB030)
#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HWACPIRESET_FILECODE (0xB031)
#define PROC_FCH_HWM_FAMILY_HUDSON2_HWM_FILECODE (0xB032)
#define PROC_FCH_HWM_FAMILY_HUDSON2_HWMRESET_FILECODE (0xB033)
#define PROC_FCH_IDE_IDE_FILECODE (0xB040)
#define PROC_FCH_IMC_FAMILY_HUDSON2_IMC_FILECODE (0xB050)
#define PROC_FCH_IMC_FAMILY_HUDSON2_IMCLIB_FILECODE (0xB051)
#define PROC_FCH_IMC_FAMILY_HUDSON2_IMCRESET_FILECODE (0xB052)
#define PROC_FCH_IMC_FAMILY_HUDSON2_SBEC_FILECODE (0xB053)
#define PROC_FCH_IMC_FAMILY_HUDSON2_SBECRESET_FILECODE (0xB054)
#define PROC_FCH_INTERFACE_INITRESETDEF_FILECODE (0xB060)
#define PROC_FCH_INTERFACE_INITENVDEF_FILECODE (0xB061)
#define PROC_FCH_INTERFACE_FCHINITRESET_FILECODE (0xB062)
#define PROC_FCH_INTERFACE_FCHINITENV_FILECODE (0xB063)
#define PROC_FCH_INTERFACE_FCHINITLATE_FILECODE (0xB064)
#define PROC_FCH_INTERFACE_FCHINITMID_FILECODE (0xB065)
#define PROC_FCH_INTERFACE_FCHINITS3_FILECODE (0xB066)
#define PROC_FCH_INTERFACE_FCHTASKLAUNCHER_FILECODE (0xB067)
#define PROC_FCH_IR_IR_FILECODE (0xB070)
#define PROC_FCH_PCIB_PCIB_FILECODE (0xB080)
#define PROC_FCH_PCIB_PCIBRESET_FILECODE (0xB081)
#define PROC_FCH_PCIE_FAMILY_HUDSON2_AB_FILECODE (0xB090)
#define PROC_FCH_PCIE_FAMILY_HUDSON2_ABRESET_FILECODE (0xB091)
#define PROC_FCH_PCIE_FAMILY_HUDSON2_GPP_FILECODE (0xB092)
#define PROC_FCH_PCIE_FAMILY_HUDSON2_GPPHP_FILECODE (0xB093)
#define PROC_FCH_PCIE_FAMILY_HUDSON2_GPPLIB_FILECODE (0xB094)
#define PROC_FCH_PCIE_FAMILY_HUDSON2_GPPRESET_FILECODE (0xB095)
#define PROC_FCH_PCIE_FAMILY_HUDSON2_PCIE_FILECODE (0xB096)
#define PROC_FCH_PCIE_FAMILY_HUDSON2_PCIERESET_FILECODE (0xB097)
#define PROC_FCH_SATA_FAMILY_HUDSON2_AHCI_FILECODE (0xB0A0)
#define PROC_FCH_SATA_FAMILY_HUDSON2_AHCILIB_FILECODE (0xB0A1)
#define PROC_FCH_SATA_FAMILY_HUDSON2_IDE2AHCI_FILECODE (0xB0A2)
#define PROC_FCH_SATA_FAMILY_HUDSON2_IDE2AHCILIB_FILECODE (0xB0A3)
#define PROC_FCH_SATA_FAMILY_HUDSON2_RAID_FILECODE (0xB0A4)
#define PROC_FCH_SATA_FAMILY_HUDSON2_RAIDLIB_FILECODE (0xB0A5)
#define PROC_FCH_SATA_FAMILY_HUDSON2_SATA_FILECODE (0xB0A6)
#define PROC_FCH_SATA_FAMILY_HUDSON2_SATAIDE_FILECODE (0xB0A7)
#define PROC_FCH_SATA_FAMILY_HUDSON2_SATAIDELIB_FILECODE (0xB0A8)
#define PROC_FCH_SATA_FAMILY_HUDSON2_SATALIB_FILECODE (0xB0A9)
#define PROC_FCH_SATA_FAMILY_HUDSON2_SATARESET_FILECODE (0xB0AA)
#define PROC_FCH_SBUSB_FAMILY_HUDSON2_EHCI_FILECODE (0xB0B0)
#define PROC_FCH_SBUSB_FAMILY_HUDSON2_EHCIRESET_FILECODE (0xB0B1)
#define PROC_FCH_SBUSB_FAMILY_HUDSON2_OHCI_FILECODE (0xB0B2)
#define PROC_FCH_SBUSB_FAMILY_HUDSON2_OHCIRESET_FILECODE (0xB0B3)
#define PROC_FCH_SBUSB_FAMILY_HUDSON2_USB_FILECODE (0xB0B4)
#define PROC_FCH_SBUSB_FAMILY_HUDSON2_USBRESET_FILECODE (0xB0B5)
#define PROC_FCH_SBUSB_FAMILY_HUDSON2_XHCI_FILECODE (0xB0B6)
#define PROC_FCH_SBUSB_FAMILY_HUDSON2_XHCIRESET_FILECODE (0xB0B7)
#define PROC_FCH_SD_SD_FILECODE (0xB0C0)
#define PROC_FCH_SPI_LPC_FILECODE (0xB0D0)
#define PROC_FCH_SPI_LPCRESET_FILECODE (0xB0D1)
#define PROC_FCH_SPI_SPI_FILECODE (0xB0D2)
#define PROC_FCH_SPI_SPIRESET_FILECODE (0xB0D3)
#define UEFI_DXE_AMDSBDXE_AMDSBDXE_FILECODE (0xB200)
#define UEFI_DXE_AMDSBWHEA_AMDSBWHEA_FILECODE (0xB210)
#define UEFI_DXE_AMDSBWHEA_BERTTABLE_FILECODE (0xB211)
#define UEFI_DXE_AMDSBWHEA_EINJTABLE_FILECODE (0xB212)
#define UEFI_DXE_AMDSBWHEA_ERSTTABLE_FILECODE (0xB213)
#define UEFI_DXE_AMDSBWHEA_HESTTABLE_FILECODE (0xB214)
#define UEFI_DXE_CF9RESET_CF9RESET_FILECODE (0xB220)
#define UEFI_DXE_CF9RESET_IA32_IA32CF9RESET_FILECODE (0xB221)
#define UEFI_DXE_CF9RESET_X64_X64CF9RESET_FILECODE (0xB222)
#define UEFI_DXE_LEGACYINTERRUPT_LEGACYINTERRUPT_FILECODE (0xB230)
#define UEFI_DXE_SMMCONTROL_SMMCONTROL_FILECODE (0xB240)
#define UEFI_LIBRARY_DECCAN_FCHSMMLIB_FCHDXECOMMON_FILECODE (0xB250)
#define UEFI_LIBRARY_DECCAN_FCHSMMLIB_FCHSMMLIB_FILECODE (0xB251)
#define UEFI_LIBRARY_DECCAN_FCHDXELIB_FCHDXELIB_FILECODE (0xB252)
#define UEFI_PEI_AMDSBPEI_AMDSBPEI_FILECODE (0xB260)
#define UEFI_PEI_AMDSBPEI_SBRESET_FILECODE (0xB261)
#define UEFI_PEI_AMDSBPEI_SBSTALL_FILECODE (0xB262)
#define UEFI_PEI_SMBUS_SMBUS_FILECODE (0xB270)
#define UEFI_SMM_AMDSBSMM_AMDSBSMM_FILECODE (0xB280)
#define UEFI_SMM_AMDSBSMM_GECSMI_FILECODE (0xB281)
#define UEFI_SMM_AMDSBSMM_GPESMI_FILECODE (0xB282)
#define UEFI_SMM_AMDSBSMM_IOTRAPSMI_FILECODE (0xB283)
#define UEFI_SMM_AMDSBSMM_MISCSMI_FILECODE (0xB284)
#define UEFI_SMM_AMDSBSMM_PERIODICTIMERSMI_FILECODE (0xB285)
#define UEFI_SMM_AMDSBSMM_POWERBUTTONSMI_FILECODE (0xB286)
#define UEFI_SMM_AMDSBSMM_SWSMI_FILECODE (0xB287)
#define UEFI_SMM_AMDSBSMM_SXSMI_FILECODE (0xB288)
#define UEFI_DXE_SMBUS_SMBUSLIGHT_FILECODE (0xB2A0)
#define UEFI_SMM_AMDSBSMMDISPATCHER_AMDSBSMMDISPATCHER_FILECODE (0xB290)
#define UEFI_SMM_AMDSBSMMGECROMDISPATCHER_AMDSBSMMGECROMDISPATCHER_FILECODE (0xB291)
#define UEFI_SMM_AMDSBSMMGPEDISPATCHER_AMDSBSMMGPEDISPATCHER_FILECODE (0xB292)
#define UEFI_SMM_AMDSBSMMIOTRAPDISPATCHER_AMDSBSMMIOTRAPDISPATCHER_FILECODE (0xB293)
#define UEFI_SMM_AMDSBSMMMISCDISPATCHER_AMDSBSMMMISCDISPATCHER_FILECODE (0xB294)
#define UEFI_SMM_AMDSBSMMPERIODICALDISPATCHER_AMDSBSMMPERIODICALDISPATCHER_FILECODE (0xB295)
#define UEFI_SMM_AMDSBSMMPWRBTNDISPATCHER_AMDSBSMMPWRBTNDISPATCHER_FILECODE (0xB296)
#define UEFI_SMM_AMDSBSMMSWDISPATCHER_AMDSBSMMSWDISPATCHER_FILECODE (0xB297)
#define UEFI_SMM_AMDSBSMMSXDISPATCHER_AMDSBSMMSXDISPATCHER_FILECODE (0xB298)
#define UEFI_SMM_AMDSBSMMUSBDISPATCHER_AMDSBSMMUSBDISPATCHER_FILECODE (0xB299)
#define LIB_AMDLIB_FILECODE (0xC001)
#define LEGACY_PROC_AGESACALLOUTS_FILECODE (0xC010)
#define LEGACY_PROC_HOBTRANSFER_FILECODE (0xC011)
#define LEGACY_PROC_DISPATCHER_FILECODE (0xC012)
#define UEFI_DXE_AMDAGESADXEDRIVER_AMDAGESADXEDRIVER_FILECODE (0xC120)
#define UEFI_PEI_AMDINITPOSTPEIM_AMDINITPOSTPEIM_FILECODE (0xC140)
#define UEFI_PEI_AMDPROCESSORINITPEIM_AMDPROCESSORINITPEIM_FILECODE (0xC141)
#define UEFI_PEI_AMDRESETMANAGER_AMDRESETMANAGER_FILECODE (0xC142)
#define UEFI_PROC_HOBTRANSFERUEFI_FILECODE (0xC162)
#define PROC_COMMON_AMDINITEARLY_FILECODE (0xC020)
#define PROC_COMMON_AMDINITENV_FILECODE (0xC021)
#define PROC_COMMON_AMDINITLATE_FILECODE (0xC022)
#define PROC_COMMON_AMDINITMID_FILECODE (0xC023)
#define PROC_COMMON_AMDINITPOST_FILECODE (0xC024)
#define PROC_COMMON_AMDINITRECOVERY_FILECODE (0xC025)
#define PROC_COMMON_AMDINITRESET_FILECODE (0xC026)
#define PROC_COMMON_AMDINITRESUME_FILECODE (0xC027)
#define PROC_COMMON_AMDS3LATERESTORE_FILECODE (0xC028)
#define PROC_COMMON_AMDS3SAVE_FILECODE (0xC029)
#define PROC_COMMON_AMDLATERUNAPTASK_FILECODE (0xC02A)
#define PROC_COMMON_COMMONRETURNS_FILECODE (0xC0C0)
#define PROC_COMMON_CREATESTRUCT_FILECODE (0xC0D0)
#define PROC_COMMON_COMMONINITS_FILECODE (0xC0F0)
#define PROC_COMMON_S3RESTORESTATE_FILECODE (0xC0F8)
#define PROC_COMMON_S3SAVESTATE_FILECODE (0xC0F9)
#define PROC_CPU_CPUAPICUTILITIES_FILECODE (0xC401)
#define PROC_CPU_CPUBRANDID_FILECODE (0xC402)
#define PROC_CPU_TABLE_FILECODE (0xC403)
#define PROC_CPU_CPUEARLYINIT_FILECODE (0xC405)
#define PROC_CPU_CPUEVENTLOG_FILECODE (0xC406)
#define PROC_CPU_CPUFAMILYTRANSLATION_FILECODE (0xC407)
#define PROC_CPU_CPUGENERALSERVICES_FILECODE (0xC408)
#define PROC_CPU_CPUINITEARLYTABLE_FILECODE (0xC409)
#define PROC_CPU_CPULATEINIT_FILECODE (0xC40A)
#define PROC_CPU_CPUMICROCODEPATCH_FILECODE (0xC40B)
#define PROC_CPU_CPUWARMRESET_FILECODE (0xC40C)
#define PROC_CPU_HEAPMANAGER_FILECODE (0xC40D)
#define PROC_CPU_CPUBIST_FILECODE (0xC40E)
#define PROC_CPU_CPUPOSTINIT_FILECODE (0xC420)
#define PROC_CPU_CPUPOWERMGMT_FILECODE (0xC430)
#define PROC_CPU_CPUPOWERMGMTMULTISOCKET_FILECODE (0xC431)
#define PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE (0xC432)
#define PROC_CPU_S3_FILECODE (0xC460)
// Family 10h
#define PROC_CPU_FAMILY_0X10_CPUCOMMONF10UTILITIES_FILECODE (0xC801)
#define PROC_CPU_FAMILY_0X10_CPUF10BRANDID_FILECODE (0xC802)
#define PROC_CPU_FAMILY_0X10_CPUF10CACHEDEFAULTS_FILECODE (0xC803)
#define PROC_CPU_FAMILY_0X10_CPUF10CACHEFLUSHONHALT_FILECODE (0xC804)
#define PROC_CPU_FAMILY_0X10_CPUF10DMI_FILECODE (0xC805)
#define PROC_CPU_FAMILY_0X10_CPUF10EARLYINIT_FILECODE (0xC806)
#define PROC_CPU_FAMILY_0X10_CPUF10FEATURELEVELING_FILECODE (0xC807)
#define PROC_CPU_FAMILY_0X10_CPUF10HTPHYTABLES_FILECODE (0xC808)
#define PROC_CPU_FAMILY_0X10_CPUF10MSRTABLES_FILECODE (0xC809)
#define PROC_CPU_FAMILY_0X10_CPUF10PCITABLES_FILECODE (0xC80A)
#define PROC_CPU_FAMILY_0X10_CPUF10POWERCHECK_FILECODE (0xC80B)
#define PROC_CPU_FAMILY_0X10_CPUF10POWERMGMTSYSTEMTABLES_FILECODE (0xC80C)
#define PROC_CPU_FAMILY_0X10_CPUF10POWERPLANE_FILECODE (0xC80D)
#define PROC_CPU_FAMILY_0X10_CPUF10SOFTWARETHERMAL_FILECODE (0xC80E)
#define PROC_CPU_FAMILY_0X10_CPUF10UTILITIES_FILECODE (0xC80F)
#define PROC_CPU_FAMILY_0X10_CPUF10WHEAINITDATATABLES_FILECODE (0xC810)
#define PROC_CPU_FAMILY_0X10_CPUF10PSTATE_FILECODE (0xC811)
#define PROC_CPU_FAMILY_0X10_CPUF10CPB_FILECODE (0xC812)
#define PROC_CPU_FAMILY_0X10_CPUF10WORKAROUNDSTABLE_FILECODE (0xC813)
#define PROC_CPU_FAMILY_0X10_F10PMNBCOFVIDINIT_FILECODE (0xC820)
#define PROC_CPU_FAMILY_0X10_F10SINGLELINKPCITABLES_FILECODE (0xC821)
#define PROC_CPU_FAMILY_0X10_F10MULTILINKPCITABLES_FILECODE (0xC822)
#define PROC_CPU_FAMILY_0X10_F10PMNBPSTATEINIT_FILECODE (0xC823)
#define PROC_CPU_FAMILY_0X10_F10PMASYMBOOSTINIT_FILECODE (0xC824)
#define PROC_CPU_FAMILY_0X10_F10INITEARLYTABLE_FILECODE (0xC825)
#define PROC_CPU_FAMILY_0X10_F10PMDUALPLANEONLYSUPPORT_FILECODE (0xC826)
#define PROC_CPU_FAMILY_0X10_F10IOCSTATE_FILECODE (0xC827)
#define PROC_CPU_FAMILY_0X10_REVC_F10REVCUTILITIES_FILECODE (0xC830)
#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHWC1E_FILECODE (0xC831)
#define PROC_CPU_FAMILY_0X10_REVC_F10REVCSWC1E_FILECODE (0xC832)
#define PROC_CPU_FAMILY_0X10_REVC_F10REVCPCITABLES_FILECODE (0xC833)
#define PROC_CPU_FAMILY_0X10_REVC_F10REVCMSRTABLES_FILECODE (0xC834)
#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHTPHYTABLES_FILECODE (0xC835)
#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLHTPHYTABLES_FILECODE (0xC836)
#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLLOGICALIDTABLES_FILECODE (0xC837)
#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMICROCODEPATCHTABLES_FILECODE (0xC838)
#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMSRTABLES_FILECODE (0xC839)
#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLEQUIVALENCETABLE_FILECODE (0xC83A)
#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLPCITABLES_FILECODE (0xC83B)
#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLCACHEFLUSHONHALT_FILECODE (0xC83C)
#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAHTPHYTABLES_FILECODE (0xC83D)
#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DALOGICALIDTABLES_FILECODE (0xC83E)
#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMICROCODEPATCHTABLES_FILECODE (0xC83F)
#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMSRTABLES_FILECODE (0xC840)
#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAEQUIVALENCETABLE_FILECODE (0xC841)
#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAPCITABLES_FILECODE (0xC842)
#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DACACHEFLUSHONHALT_FILECODE (0xC843)
#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBHTPHYTABLES_FILECODE (0xC844)
#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBLOGICALIDTABLES_FILECODE (0xC845)
#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMICROCODEPATCHTABLES_FILECODE (0xC846)
#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMSRTABLES_FILECODE (0xC847)
#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBEQUIVALENCETABLE_FILECODE (0xC848)
#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBPCITABLES_FILECODE (0xC849)
#define PROC_CPU_FAMILY_0X10_REVD_F10REVDUTILITIES_FILECODE (0xC850)
#define PROC_CPU_FAMILY_0X10_REVD_F10REVDMSGBASEDC1E_FILECODE (0xC851)
#define PROC_CPU_FAMILY_0X10_REVD_F10REVDHTASSIST_FILECODE (0xC852)
#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYHTPHYTABLES_FILECODE (0xC853)
#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYINITEARLYTABLE_FILECODE (0xC854)
#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYLOGICALIDTABLES_FILECODE (0xC855)
#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMICROCODEPATCHTABLES_FILECODE (0xC856)
#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMSRTABLES_FILECODE (0xC857)
#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYEQUIVALENCETABLE_FILECODE (0xC858)
#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYPCITABLES_FILECODE (0xC859)
#define PROC_CPU_FAMILY_0X10_REVE_F10REVEUTILITIES_FILECODE (0xC860)
#define PROC_CPU_FAMILY_0X10_REVE_F10REVEMSRTABLES_FILECODE (0xC861)
#define PROC_CPU_FAMILY_0X10_REVE_F10REVEPCITABLES_FILECODE (0xC862)
#define PROC_CPU_FAMILY_0X10_REVE_F10REVEHTPHYTABLES_FILECODE (0xC863)
#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHEQUIVALENCETABLE_FILECODE (0xC864)
#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHHTPHYTABLES_FILECODE (0xC865)
#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHLOGICALIDTABLES_FILECODE (0xC866)
#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHMICROCODEPATCHTABLES_FILECODE (0xC867)
// Family 12h
#define PROC_CPU_FAMILY_0X12_CPUCOMMONF12UTILITIES_FILECODE (0xC901)
#define PROC_CPU_FAMILY_0X12_CPUF12BRANDID_FILECODE (0xC902)
#define PROC_CPU_FAMILY_0X12_CPUF12CACHEDEFAULTS_FILECODE (0xC903)
#define PROC_CPU_FAMILY_0X12_CPUF12DMI_FILECODE (0xC904)
#define PROC_CPU_FAMILY_0X12_CPUF12MSRTABLES_FILECODE (0xC905)
#define PROC_CPU_FAMILY_0X12_CPUF12EARLYNBPSTATEINIT_FILECODE (0xC906)
#define PROC_CPU_FAMILY_0X12_CPUF12PCITABLES_FILECODE (0xC907)
#define PROC_CPU_FAMILY_0X12_CPUF12POWERCHECK_FILECODE (0xC908)
#define PROC_CPU_FAMILY_0X12_CPUF12POWERMGMTSYSTEMTABLES_FILECODE (0xC909)
#define PROC_CPU_FAMILY_0X12_CPUF12POWERPLANE_FILECODE (0xC90A)
#define PROC_CPU_FAMILY_0X12_CPUF12SOFTWARETHERMAL_FILECODE (0xC90B)
#define PROC_CPU_FAMILY_0X12_CPUF12UTILITIES_FILECODE (0xC90C)
#define PROC_CPU_FAMILY_0X12_CPUF12WHEAINITDATATABLES_FILECODE (0xC90D)
#define PROC_CPU_FAMILY_0X12_CPUF12PSTATE_FILECODE (0xC90E)
#define PROC_CPU_FAMILY_0X12_F12C6STATE_FILECODE (0xC90F)
#define PROC_CPU_FAMILY_0X12_F12CPB_FILECODE (0xC910)
#define PROC_CPU_FAMILY_0X12_F12IOCSTATE_FILECODE (0xC911)
#define PROC_CPU_FAMILY_0X12_LN_F12LNLOGICALIDTABLES_FILECODE (0xC921)
#define PROC_CPU_FAMILY_0X12_LN_F12LNMICROCODEPATCHTABLES_FILECODE (0xC922)
#define PROC_CPU_FAMILY_0X12_LN_F12LNEQUIVALENCETABLE_FILECODE (0xC923)
#define PROC_CPU_FAMILY_0X12_CPUF12PERCOREPCITABLES_FILECODE (0xC924)
#define PROC_CPU_FAMILY_0X12_LN_F12LNEARLYSAMPLES_FILECODE (0xC925)
// Family 14h
#define PROC_CPU_FAMILY_0X14_CPUCOMMONF14UTILITIES_FILECODE (0xCA01)
#define PROC_CPU_FAMILY_0X14_CPUF14BRANDID_FILECODE (0xCA02)
#define PROC_CPU_FAMILY_0X14_CPUF14CACHEDEFAULTS_FILECODE (0xCA03)
#define PROC_CPU_FAMILY_0X14_CPUF14DMI_FILECODE (0xCA04)
#define PROC_CPU_FAMILY_0X14_CPUF14MSRTABLES_FILECODE (0xCA05)
#define PROC_CPU_FAMILY_0X14_CPUF14PCITABLES_FILECODE (0xCA06)
#define PROC_CPU_FAMILY_0X14_CPUF14POWERCHECK_FILECODE (0xCA07)
#define PROC_CPU_FAMILY_0X14_CPUF14POWERMGMTSYSTEMTABLES_FILECODE (0xCA08)
#define PROC_CPU_FAMILY_0X14_CPUF14POWERPLANE_FILECODE (0xCA09)
#define PROC_CPU_FAMILY_0X14_CPUF14SOFTWARETHERMAL_FILECODE (0xCA0A)
#define PROC_CPU_FAMILY_0X14_CPUF14UTILITIES_FILECODE (0xCA0B)
#define PROC_CPU_FAMILY_0X14_CPUF14WHEAINITDATATABLES_FILECODE (0xCA0C)
#define PROC_CPU_FAMILY_0X14_CPUF14PSTATE_FILECODE (0xCA0D)
#define PROC_CPU_FAMILY_0X14_F14C6STATE_FILECODE (0xCA0E)
#define PROC_CPU_FAMILY_0X14_F14IOCSTATE_FILECODE (0xCA0F)
#define PROC_CPU_FAMILY_0X14_CPUF14PERCOREPCITABLES_FILECODE (0xCA10)
#define PROC_CPU_FAMILY_0X14_CPUF14LOWPOWERINIT_FILECODE (0xCA11)
#define PROC_CPU_FAMILY_0X14_ON_F14ONLOGICALIDTABLES_FILECODE (0xCA21)
#define PROC_CPU_FAMILY_0X14_ON_F14ONMICROCODEPATCHTABLES_FILECODE (0xCA22)
#define PROC_CPU_FAMILY_0X14_ON_F14ONEQUIVALENCETABLE_FILECODE (0xCA23)
#define PROC_CPU_FAMILY_0X14_ON_F14ONINITEARLYTABLE_FILECODE (0xCA24)
#define PROC_CPU_FAMILY_0X14_ON_F14ONEARLYSAMPLES_FILECODE (0xCA26)
#define PROC_CPU_FAMILY_0X14_ON_F14ONCPB_FILECODE (0xCA2C)
#define PROC_CPU_FAMILY_0X14_ON_F14ONPCITABLES_FILECODE (0xCA2D)
// Family 15h
#define PROC_CPU_FAMILY_0X15_CPUCOMMONF15UTILITIES_FILECODE (0xCB01)
#define PROC_CPU_FAMILY_0X15_CPUF15BRANDID_FILECODE (0xCB02)
#define PROC_CPU_FAMILY_0X15_CPUF15CACHEDEFAULTS_FILECODE (0xCB03)
#define PROC_CPU_FAMILY_0X15_CPUF15CACHEFLUSHONHALT_FILECODE (0xCB04)
#define PROC_CPU_FAMILY_0X15_CPUF15COREAFTERRESET_FILECODE (0xCB05)
#define PROC_CPU_FAMILY_0X15_CPUF15DMI_FILECODE (0xCB06)
#define PROC_CPU_FAMILY_0X15_CPUF15FEATURELEVELING_FILECODE (0xCB07)
#define PROC_CPU_FAMILY_0X15_CPUF15HTPHYTABLES_FILECODE (0xCB08)
#define PROC_CPU_FAMILY_0X15_CPUF15MSRTABLES_FILECODE (0xCB09)
#define PROC_CPU_FAMILY_0X15_CPUF15NBAFTERRESET_FILECODE (0xCB0A)
#define PROC_CPU_FAMILY_0X15_CPUF15PCITABLES_FILECODE (0xCB0B)
#define PROC_CPU_FAMILY_0X15_CPUF15POWERCHECK_FILECODE (0xCB0C)
#define PROC_CPU_FAMILY_0X15_CPUF15POWERMGMTSYSTEMTABLES_FILECODE (0xCB0D)
#define PROC_CPU_FAMILY_0X15_CPUF15POWERPLANE_FILECODE (0xCB0E)
#define PROC_CPU_FAMILY_0X15_CPUF15SOFTWARETHERMAL_FILECODE (0xCB0F)
#define PROC_CPU_FAMILY_0X15_CPUF15UTILITIES_FILECODE (0xCB10)
#define PROC_CPU_FAMILY_0X15_CPUF15WHEAINITDATATABLES_FILECODE (0xCB11)
#define PROC_CPU_FAMILY_0X15_CPUF15PSTATE_FILECODE (0xCB12)
#define PROC_CPU_FAMILY_0X15_F15PMNBCOFVIDINIT_FILECODE (0xCB13)
#define PROC_CPU_FAMILY_0X15_F15SINGLELINKPCITABLES_FILECODE (0xCB14)
#define PROC_CPU_FAMILY_0X15_F15MULTILINKPCITABLES_FILECODE (0xCB15)
#define PROC_CPU_FAMILY_0X15_F15C6STATE_FILECODE (0xCB16)
#define PROC_CPU_FAMILY_0X15_F15CPB_FILECODE (0xCB17)
#define PROC_CPU_FAMILY_0X15_F15INITEARLYTABLE_FILECODE (0xCB18)
#define PROC_CPU_FAMILY_0X15_F15LOWPWRPSTATE_FILECODE (0xCB19)
#define PROC_CPU_FAMILY_0X15_CPUF15WORKAROUNDSTABLE_FILECODE (0xCB1A)
#define PROC_CPU_FAMILY_0X15_F15IOCSTATE_FILECODE (0xCB1B)
#define PROC_CPU_FAMILY_0X15_OR_F15ORHTASSIST_FILECODE (0xCB30)
#define PROC_CPU_FAMILY_0X15_OR_F15ORMSGBASEDC1E_FILECODE (0xCB31)
#define PROC_CPU_FAMILY_0X15_OR_F15ORLOGICALIDTABLES_FILECODE (0xCB32)
#define PROC_CPU_FAMILY_0X15_OR_F15ORMICROCODEPATCHTABLES_FILECODE (0xCB33)
#define PROC_CPU_FAMILY_0X15_OR_F15ORMSRTABLES_FILECODE (0xCB34)
#define PROC_CPU_FAMILY_0X15_OR_F15ORSHAREDMSRTABLE_FILECODE (0xCB35)
#define PROC_CPU_FAMILY_0X15_OR_F15OREQUIVALENCETABLE_FILECODE (0xCB36)
#define PROC_CPU_FAMILY_0X15_OR_F15ORPCITABLES_FILECODE (0xCB37)
#define PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE (0xDC01)
#define PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE (0xDC02)
#define PROC_CPU_FEATURE_CPUDMI_FILECODE (0xDC10)
#define PROC_CPU_FEATURE_CPUFEATURELEVELING_FILECODE (0xDC20)
#define PROC_CPU_FEATURE_CPUHTASSIST_FILECODE (0xDC30)
#define PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE (0xDC41)
#define PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE (0xDC42)
#define PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE (0xDC43)
#define PROC_CPU_FEATURE_CPUSLIT_FILECODE (0xDC50)
#define PROC_CPU_FEATURE_CPUSRAT_FILECODE (0xDC60)
#define PROC_CPU_FEATURE_CPUWHEA_FILECODE (0xDC70)
#define PROC_CPU_FEATURE_CPUHWC1E_FILECODE (0xDC80)
#define PROC_CPU_FEATURE_CPUSWC1E_FILECODE (0xDC81)
#define PROC_CPU_FEATURE_CPUC6STATE_FILECODE (0xDC82)
#define PROC_CPU_FEATURE_CPUCPB_FILECODE (0xDC83)
#define PROC_CPU_FEATURE_CPULOWPWRPSTATE_FILECODE (0xDC84)
#define PROC_CPU_FEATURE_CPUIOCSTATE_FILECODE (0xDC85)
#define PROC_CPU_FEATURE_CPUFEATURES_FILECODE (0xDC90)
#define PROC_CPU_FEATURE_CPUMSGBASEDC1E_FILECODE (0xDCA0)
#define PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE (0xDCB0)
#define PROC_CPU_FEATURE_PRESERVEMAILBOX_FILECODE (0xDCC0)
#define PROC_RECOVERY_CPU_CPURECOVERY_FILECODE (0xDE01)
#define PROC_HT_FEATURES_HTFEATSETS_FILECODE (0xE001)
#define PROC_HT_FEATURES_HTFEATDYNAMICDISCOVERY_FILECODE (0xE002)
#define PROC_HT_FEATURES_HTFEATGANGING_FILECODE (0xE003)
#define PROC_HT_FEATURES_HTFEATNONCOHERENT_FILECODE (0xE004)
#define PROC_HT_FEATURES_HTFEATOPTIMIZATION_FILECODE (0xE005)
#define PROC_HT_FEATURES_HTFEATROUTING_FILECODE (0xE006)
#define PROC_HT_FEATURES_HTFEATSUBLINKS_FILECODE (0xE007)
#define PROC_HT_FEATURES_HTFEATTRAFFICDISTRIBUTION_FILECODE (0xE008)
#define PROC_HT_FEATURES_HTIDS_FILECODE (0xE009)
#define PROC_HT_HTFEAT_FILECODE (0xE021)
#define PROC_HT_HTINTERFACE_FILECODE (0xE022)
#define PROC_HT_HTINTERFACECOHERENT_FILECODE (0xE023)
#define PROC_HT_HTINTERFACEGENERAL_FILECODE (0xE024)
#define PROC_HT_HTINTERFACENONCOHERENT_FILECODE (0xE025)
#define PROC_HT_HTMAIN_FILECODE (0xE026)
#define PROC_HT_HTNOTIFY_FILECODE (0xE027)
#define PROC_HT_HTGRAPH_HTGRAPH_FILECODE (0xE028)
#define PROC_HT_HTNB_FILECODE (0xE081)
#define PROC_HT_NBCOMMON_HTNBCOHERENT_FILECODE (0xE082)
#define PROC_HT_NBCOMMON_HTNBNONCOHERENT_FILECODE (0xE083)
#define PROC_HT_NBCOMMON_HTNBOPTIMIZATION_FILECODE (0xE084)
#define PROC_HT_NBCOMMON_HTNBUTILITIES_FILECODE (0xE085)
#define PROC_HT_FAM10_HTNBFAM10_FILECODE (0xE0C1)
#define PROC_HT_FAM10_HTNBCOHERENTFAM10_FILECODE (0xE0C2)
#define PROC_HT_FAM10_HTNBNONCOHERENTFAM10_FILECODE (0xE0C3)
#define PROC_HT_FAM10_HTNBOPTIMIZATIONFAM10_FILECODE (0xE0C4)
#define PROC_HT_FAM10_HTNBSYSTEMFAM10_FILECODE (0xE0C5)
#define PROC_HT_FAM10_HTNBUTILITIESFAM10_FILECODE (0xE0C6)
#define PROC_HT_FAM12_HTNBFAM12_FILECODE (0xE101)
#define PROC_HT_FAM12_HTNBUTILITIESFAM12_FILECODE (0xE102)
#define PROC_HT_FAM14_HTNBFAM14_FILECODE (0xE141)
#define PROC_HT_FAM14_HTNBUTILITIESFAM14_FILECODE (0xE142)
#define PROC_HT_FAM15_HTNBFAM15_FILECODE (0xE181)
#define PROC_HT_FAM15_HTNBCOHERENTFAM15_FILECODE (0xE182)
#define PROC_HT_FAM15_HTNBNONCOHERENTFAM15_FILECODE (0xE183)
#define PROC_HT_FAM15_HTNBOPTIMIZATIONFAM15_FILECODE (0xE184)
#define PROC_HT_FAM15_HTNBSYSTEMFAM15_FILECODE (0xE185)
#define PROC_HT_FAM15_HTNBUTILITIESFAM15_FILECODE (0xE186)
#define PROC_RECOVERY_HT_HTINITRECOVERY_FILECODE (0xE302)
#define PROC_RECOVERY_HT_HTINITRESET_FILECODE (0xE301)
#define PROC_IDS_CONTROL_IDSCTRL_FILECODE (0xE801)
#define PROC_IDS_CONTROL_IDSLIB_FILECODE (0xE802)
#define PROC_IDS_DEBUG_IDSDEBUG_FILECODE (0xE803)
#define PROC_IDS_PERF_IDSPERF_FILECODE (0xE804)
#define PROC_IDS_FAMILY_0X10_IDSF10ALLSERVICE_FILECODE (0xE805)
#define PROC_IDS_FAMILY_0X10_BL_IDSF10BLSERVICE_FILECODE (0xE806)
#define PROC_IDS_FAMILY_0X10_DA_IDSF10DASERVICE_FILECODE (0xE807)
#define PROC_IDS_FAMILY_0X10_HY_IDSF10HYSERVICE_FILECODE (0xE808)
#define PROC_IDS_FAMILY_0X10_RB_IDSF10RBSERVICE_FILECODE (0xE809)
#define PROC_IDS_FAMILY_0X12_IDSF12ALLSERVICE_FILECODE (0xE80A)
#define PROC_IDS_FAMILY_0X14_IDSF14ALLSERVICE_FILECODE (0xE80B)
#define PROC_IDS_FAMILY_0X15_IDSF15ALLSERVICE_FILECODE (0xE80C)
#define PROC_IDS_DEBUG_IDSIDTTABLE_FILECODE (0xE80D)
#define PROC_IDS_CONTROL_IDSNVTOCMOS_FILECODE (0xE80E)
///0xE820 ~ 0xE840 is reserved for ids extend module
#define PROC_MEM_ARDK_MA_FILECODE (0xF001)
#define PROC_MEM_ARDK_DR_MARDR2_FILECODE (0xF002)
#define PROC_MEM_ARDK_DR_MARDR3_FILECODE (0xF003)
#define PROC_MEM_ARDK_HY_MARHY3_FILECODE (0xF004)
#define PROC_MEM_ARDK_LN_MASLN3_FILECODE (0xF005)
#define PROC_MEM_ARDK_DR_MAUDR3_FILECODE (0xF006)
#define PROC_MEM_ARDK_HY_MAUHY3_FILECODE (0xF007)
#define PROC_MEM_ARDK_LN_MAULN3_FILECODE (0xF008)
#define PROC_MEM_ARDK_DA_MAUDA3_FILECODE (0xF009)
#define PROC_MEM_ARDK_DA_MASDA2_FILECODE (0xF00A)
#define PROC_MEM_ARDK_DA_MASDA3_FILECODE (0xF00B)
#define PROC_MEM_ARDK_NI_MASNI3_FILECODE (0xF00C)
#define PROC_MEM_ARDK_C32_MARC32_3_FILECODE (0xF00D)
#define PROC_MEM_ARDK_C32_MAUC32_3_FILECODE (0xF00E)
#define PROC_MEM_ARDK_NI_MAUNI3_FILECODE (0xF00F)
#define PROC_MEM_ARDK_ON_MASON3_FILECODE (0xF010)
#define PROC_MEM_ARDK_ON_MAUON3_FILECODE (0xF011)
#define PROC_MEM_ARDK_PH_MASPH3_FILECODE (0xF012)
#define PROC_MEM_ARDK_PH_MAUPH3_FILECODE (0xF013)
#define PROC_MEM_ARDK_OR_MAROR3_FILECODE (0xF014)
#define PROC_MEM_ARDK_OR_MAUOR3_FILECODE (0xF017)
#define PROC_MEM_ARDK_RB_MASRB3_FILECODE (0xF018)
#define PROC_MEM_ARDK_RB_MAURB3_FILECODE (0xF019)
#define PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE (0xF081)
#define PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE (0xF082)
#define PROC_MEM_FEAT_ECC_MFECC_FILECODE (0xF083)
#define PROC_MEM_FEAT_ECC_MFEMP_FILECODE (0xF085)
#define PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE (0xF086)
#define PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE (0xF088)
#define PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE (0xF089)
#define PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE (0xF08A)
#define PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE (0xF08B)
#define PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE (0xF08C)
#define PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE (0xF08D)
#define PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE (0xF08E)
#define PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE (0xF08F)
#define PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE (0xF091)
#define PROC_MEM_FEAT_S3_MFS3_FILECODE (0xF092)
#define PROC_MEM_FEAT_TABLE_MFTDS_FILECODE (0xF093)
#define PROC_MEM_MAIN_MDEF_FILECODE (0xF101)
#define PROC_MEM_MAIN_MINIT_FILECODE (0xF102)
#define PROC_MEM_MAIN_MM_FILECODE (0xF103)
#define PROC_MEM_FEAT_DMI_MFDMI_FILECODE (0xF104)
#define PROC_MEM_MAIN_MMECC_FILECODE (0xF105)
#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE (0xF106)
#define PROC_MEM_MAIN_DR_MMFLOWDR_FILECODE (0xF107)
#define PROC_MEM_MAIN_HY_MMFLOWHY_FILECODE (0xF108)
#define PROC_MEM_MAIN_LN_MMFLOWLN_FILECODE (0xF109)
#define PROC_MEM_MAIN_ON_MMFLOWON_FILECODE (0xF10A)
#define PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE (0xF10B)
#define PROC_MEM_MAIN_MMONLINESPARE_FILECODE (0xF10C)
#define PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE (0xF10D)
#define PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE (0xF10E)
#define PROC_MEM_MAIN_MUC_FILECODE (0xF10F)
#define PROC_MEM_MAIN_MMMEMCLR_FILECODE (0xF110)
#define PROC_MEM_MAIN_DA_MMFLOWDA_FILECODE (0xF111)
#define PROC_MEM_MAIN_MMFLOW_FILECODE (0xF112)
#define PROC_MEM_MAIN_MERRHDL_FILECODE (0xF113)
#define PROC_MEM_MAIN_C32_MMFLOWC32_FILECODE (0xF114)
#define PROC_MEM_MAIN_MMLVDDR3_FILECODE (0xF115)
#define PROC_MEM_MAIN_MMUMAALLOC_FILECODE (0xF116)
#define PROC_MEM_MAIN_MMMEMRESTORE_FILECODE (0xF117)
#define PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE (0xF118)
#define PROC_MEM_MAIN_OR_MMFLOWOR_FILECODE (0xF119)
#define PROC_MEM_MAIN_RB_MMFLOWRB_FILECODE (0xF11A)
#define PROC_MEM_MAIN_PH_MMFLOWPH_FILECODE (0xF11B)
#define PROC_MEM_NB_DR_MNDR_FILECODE (0xF213)
#define PROC_MEM_NB_DR_MNFLOWDR_FILECODE (0xF214)
#define PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE (0xF216)
#define PROC_MEM_NB_DR_MNMCTDR_FILECODE (0xF217)
#define PROC_MEM_NB_DR_MNDCTDR_FILECODE (0xF218)
#define PROC_MEM_NB_DR_MNOTDR_FILECODE (0xF219)
#define PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE (0xF21A)
#define PROC_MEM_NB_DR_MNPROTODR_FILECODE (0xF21C)
#define PROC_MEM_NB_DR_MNS3DR_FILECODE (0xF21D)
#define PROC_MEM_NB_DR_MNREGDR_FILECODE (0xF21E)
#define PROC_MEM_NB_RB_MNRB_FILECODE (0xF220)
#define PROC_MEM_NB_RB_MNFLOWRB_FILECODE (0xF221)
#define PROC_MEM_NB_RB_MNS3RB_FILECODE (0xF222)
#define PROC_MEM_NB_RB_MNIDENDIMMRB_FILECODE (0xF223)
#define PROC_MEM_NB_HY_MNFLOWHY_FILECODE (0xF233)
#define PROC_MEM_NB_HY_MNHY_FILECODE (0xF235)
#define PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE (0xF236)
#define PROC_MEM_NB_HY_MNMCTHY_FILECODE (0xF237)
#define PROC_MEM_NB_HY_MNDCTHY_FILECODE (0xF238)
#define PROC_MEM_NB_HY_MNOTHY_FILECODE (0xF239)
#define PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE (0xF23A)
#define PROC_MEM_NB_HY_MNPHYHY_FILECODE (0xF23B)
#define PROC_MEM_NB_HY_MNPROTOHY_FILECODE (0xF23C)
#define PROC_MEM_NB_HY_MNS3HY_FILECODE (0xF23D)
#define PROC_MEM_NB_HY_MNREGHY_FILECODE (0xF23E)
#define PROC_MEM_NB_ON_MNON_FILECODE (0xF240)
#define PROC_MEM_NB_ON_MNREGON_FILECODE (0xF241)
#define PROC_MEM_NB_ON_MNDCTON_FILECODE (0xF242)
#define PROC_MEM_NB_ON_MNIDENDIMMON_FILECODE (0xF244)
#define PROC_MEM_NB_ON_MNMCTON_FILECODE (0xF245)
#define PROC_MEM_NB_ON_MNOTON_FILECODE (0xF246)
#define PROC_MEM_NB_ON_MNPHYON_FILECODE (0xF247)
#define PROC_MEM_NB_ON_MNS3ON_FILECODE (0xF248)
#define PROC_MEM_NB_ON_MNFLOWON_FILECODE (0xF249)
#define PROC_MEM_NB_ON_MNPROTOON_FILECODE (0xF24A)
#define PROC_MEM_NB_LN_MNDCTLN_FILECODE (0xF252)
#define PROC_MEM_NB_LN_MNFLOWLN_FILECODE (0xF253)
#define PROC_MEM_NB_LN_MNIDENDIMMLN_FILECODE (0xF254)
#define PROC_MEM_NB_LN_MNMCTLN_FILECODE (0xF255)
#define PROC_MEM_NB_LN_MNOTLN_FILECODE (0xF256)
#define PROC_MEM_NB_LN_MNPHYLN_FILECODE (0xF257)
#define PROC_MEM_NB_LN_MNPROTOLN_FILECODE (0xF258)
#define PROC_MEM_NB_LN_MNLN_FILECODE (0xF259)
#define PROC_MEM_NB_LN_MNS3LN_FILECODE (0xF25A)
#define PROC_MEM_NB_LN_MNREGLN_FILECODE (0xF25B)
#define PROC_MEM_NB_DA_MNDA_FILECODE (0xF260)
#define PROC_MEM_NB_DA_MNFLOWDA_FILECODE (0xF261)
#define PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE (0xF263)
#define PROC_MEM_NB_DA_MNMCTDA_FILECODE (0xF264)
#define PROC_MEM_NB_DA_MNDCTDA_FILECODE (0xF265)
#define PROC_MEM_NB_DA_MNOTDA_FILECODE (0xF266)
#define PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE (0xF267)
#define PROC_MEM_NB_DA_MNPROTODA_FILECODE (0xF269)
#define PROC_MEM_NB_DA_MNS3DA_FILECODE (0xF26A)
#define PROC_MEM_NB_DA_MNREGDA_FILECODE (0xF26B)
#define PROC_MEM_NB_C32_MNC32_FILECODE (0xF26C)
#define PROC_MEM_NB_C32_MNDCTC32_FILECODE (0xF26D)
#define PROC_MEM_NB_C32_MNFLOWC32_FILECODE (0xF26E)
#define PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE (0xF26F)
#define PROC_MEM_NB_C32_MNMCTC32_FILECODE (0xF270)
#define PROC_MEM_NB_C32_MNOTC32_FILECODE (0xF271)
#define PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE (0xF272)
#define PROC_MEM_NB_C32_MNPHYC32_FILECODE (0xF273)
#define PROC_MEM_NB_C32_MNPROTOC32_FILECODE (0xF274)
#define PROC_MEM_NB_C32_MNS3C32_FILECODE (0xF275)
#define PROC_MEM_NB_C32_MNREGC32_FILECODE (0xF277)
#define PROC_MEM_NB_MN_FILECODE (0xF27C)
#define PROC_MEM_NB_MNDCT_FILECODE (0xF27D)
#define PROC_MEM_NB_MNPHY_FILECODE (0xF27E)
#define PROC_MEM_NB_MNMCT_FILECODE (0xF27F)
#define PROC_MEM_NB_MNS3_FILECODE (0xF280)
#define PROC_MEM_NB_MNFLOW_FILECODE (0xF281)
#define PROC_MEM_NB_MNFEAT_FILECODE (0xF282)
#define PROC_MEM_NB_MNTRAIN2_FILECODE (0xF283)
#define PROC_MEM_NB_MNTRAIN3_FILECODE (0xF284)
#define PROC_MEM_NB_MNREG_FILECODE (0xF285)
#define PROC_MEM_NB_NI_MNNI_FILECODE (0xF286)
#define PROC_MEM_NB_NI_MNS3NI_FILECODE (0xF287)
#define PROC_MEM_NB_NI_MNFLOWNI_FILECODE (0xF288)
#define PROC_MEM_NB_PH_MNFLOWPH_FILECODE (0xF289)
#define PROC_MEM_NB_PH_MNPH_FILECODE (0xF28A)
#define PROC_MEM_NB_PH_MNS3PH_FILECODE (0xF28B)
#define PROC_MEM_NB_PH_MNIDENDIMMPH_FILECODE (0xF28C)
#define PROC_MEM_NB_OR_MNFLOWOR_FILECODE (0xF290)
#define PROC_MEM_NB_OR_MNOR_FILECODE (0xF291)
#define PROC_MEM_NB_OR_MNIDENDIMMOR_FILECODE (0xF292)
#define PROC_MEM_NB_OR_MNMCTOR_FILECODE (0xF293)
#define PROC_MEM_NB_OR_MNDCTOR_FILECODE (0xF294)
#define PROC_MEM_NB_OR_MNOTOR_FILECODE (0xF295)
#define PROC_MEM_NB_OR_MNPARTRAINOR_FILECODE (0xF296)
#define PROC_MEM_NB_OR_MNPHYOR_FILECODE (0xF297)
#define PROC_MEM_NB_OR_MNPROTOOR_FILECODE (0xF298)
#define PROC_MEM_NB_OR_MNS3OR_FILECODE (0xF299)
#define PROC_MEM_NB_OR_MNREGOR_FILECODE (0xF29A)
#define PROC_MEM_PS_MP_FILECODE (0xF401)
#define PROC_MEM_PS_DR_MPRDR3_FILECODE (0xF402)
#define PROC_MEM_PS_HY_MPRHY3_FILECODE (0xF403)
#define PROC_MEM_PS_LN_MPRLN3_FILECODE (0xF404)
#define PROC_MEM_PS_DR_MPSDR3_FILECODE (0xF405)
#define PROC_MEM_PS_HY_MPSHY3_FILECODE (0xF406)
#define PROC_MEM_PS_LN_MPSLN3_FILECODE (0xF407)
#define PROC_MEM_PS_DR_MPUDR3_FILECODE (0xF408)
#define PROC_MEM_PS_HY_MPUHY3_FILECODE (0xF409)
#define PROC_MEM_PS_LN_MPULN3_FILECODE (0xF40A)
#define PROC_MEM_PS_DA_MPUDA3_FILECODE (0xF40B)
#define PROC_MEM_PS_DA_MPSDA2_FILECODE (0xF40C)
#define PROC_MEM_PS_DA_MPSDA3_FILECODE (0xF40D)
#define PROC_MEM_PS_DR_MPRDR2_FILECODE (0xF40E)
#define PROC_MEM_PS_DR_MPUDR2_FILECODE (0xF40F)
#define PROC_MEM_PS_C32_MPRC32_3_FILECODE (0xF410)
#define PROC_MEM_PS_C32_MPUC32_3_FILECODE (0xF411)
#define PROC_MEM_PS_NI_MPSNI3_FILECODE (0xF412)
#define PROC_MEM_PS_NI_MPUNI3_FILECODE (0xF413)
#define PROC_MEM_PS_ON_MPSON3_FILECODE (0xF414)
#define PROC_MEM_PS_ON_MPUON3_FILECODE (0xF415)
#define PROC_MEM_PS_PH_MPSPH3_FILECODE (0xF416)
#define PROC_MEM_PS_PH_MPUPH3_FILECODE (0xF417)
#define PROC_MEM_PS_RB_MPSRB3_FILECODE (0xF418)
#define PROC_MEM_PS_RB_MPURB3_FILECODE (0xF419)
#define PROC_MEM_PS_OR_AM3_MPUORA3_FILECODE (0xF41A)
#define PROC_MEM_PS_OR_AM3_MPSORA3_FILECODE (0xF41B)
#define PROC_MEM_PS_OR_C32_MPRORC3_FILECODE (0xF41C)
#define PROC_MEM_PS_OR_C32_MPUORC3_FILECODE (0xF41D)
#define PROC_MEM_PS_OR_C32_MPLORC3_FILECODE (0xF41E)
#define PROC_MEM_PS_OR_G34_MPRORG3_FILECODE (0xF41F)
#define PROC_MEM_PS_OR_G34_MPUORG3_FILECODE (0xF420)
#define PROC_MEM_PS_OR_G34_MPLORG3_FILECODE (0xF421)
#define PROC_MEM_PS_MPRTT_FILECODE (0xF422)
#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0xF423)
#define PROC_MEM_PS_MPODTPAT_FILECODE (0xF424)
#define PROC_MEM_PS_MPSAO_FILECODE (0xF425)
#define PROC_MEM_PS_MPMR0_FILECODE (0xF426)
#define PROC_MEM_PS_MPRC2IBT_FILECODE (0xF427)
#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0xF428)
#define PROC_MEM_PS_MPLRIBT_FILECODE (0xF429)
#define PROC_MEM_PS_MPLRNPR_FILECODE (0xF42A)
#define PROC_MEM_PS_MPLRNLR_FILECODE (0xF42B)
#define PROC_MEM_PS_OR_MPOR3_FILECODE (0xF42C)
#define PROC_MEM_TECH_MT_FILECODE (0xF501)
#define PROC_MEM_TECH_MTHDI_FILECODE (0xF502)
#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0xF504)
#define PROC_MEM_TECH_MTTECC_FILECODE (0xF505)
#define PROC_MEM_TECH_MTTHRC_FILECODE (0xF506)
#define PROC_MEM_TECH_MTTML_FILECODE (0xF507)
#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0xF509)
#define PROC_MEM_TECH_MTTSRC_FILECODE (0xF50B)
#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0xF50C)
#define PROC_MEM_TECH_DDR2_MT2_FILECODE (0xF541)
#define PROC_MEM_TECH_DDR2_MTOT2_FILECODE (0xF543)
#define PROC_MEM_TECH_DDR2_MTSPD2_FILECODE (0xF544)
#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0xF581)
#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0xF583)
#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0xF584)
#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0xF585)
#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0xF586)
#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0xF587)
#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0xF588)
#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0xF589)
#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0xF801)
#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0xF802)
#define PROC_RECOVERY_MEM_MRM_FILECODE (0xF803)
#define PROC_RECOVERY_MEM_MRUC_FILECODE (0xF804)
#define PROC_RECOVERY_MEM_NB_DR_MRNDR_FILECODE (0xF812)
#define PROC_RECOVERY_MEM_NB_DR_MRNMCTDR_FILECODE (0xF813)
#define PROC_RECOVERY_MEM_NB_HY_MRNDCTHY_FILECODE (0xF821)
#define PROC_RECOVERY_MEM_NB_HY_MRNHY_FILECODE (0xF822)
#define PROC_RECOVERY_MEM_NB_HY_MRNMCTHY_FILECODE (0xF823)
#define PROC_RECOVERY_MEM_NB_HY_MRNPROTOHY_FILECODE (0xF825)
#define PROC_RECOVERY_MEM_NB_LN_MRNDCTLN_FILECODE (0xF831)
#define PROC_RECOVERY_MEM_NB_LN_MRNMCTLN_FILECODE (0xF832)
#define PROC_RECOVERY_MEM_NB_LN_MRNLN_FILECODE (0xF833)
#define PROC_RECOVERY_MEM_NB_DA_MRNDA_FILECODE (0xF842)
#define PROC_RECOVERY_MEM_NB_DA_MRNMCTDA_FILECODE (0xF843)
#define PROC_RECOVERY_MEM_NB_NI_MRNNI_FILECODE (0xF845)
#define PROC_RECOVERY_MEM_NB_C32_MRNC32_FILECODE (0xF851)
#define PROC_RECOVERY_MEM_NB_C32_MRNMCTC32_FILECODE (0xF852)
#define PROC_RECOVERY_MEM_NB_C32_MRNPROTOC32_FILECODE (0xF853)
#define PROC_RECOVERY_MEM_NB_ON_MRNDCTON_FILECODE (0xF861)
#define PROC_RECOVERY_MEM_NB_ON_MRNMCTON_FILECODE (0xF862)
#define PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE (0xF863)
#define PROC_RECOVERY_MEM_NB_PH_MRNPH_FILECODE (0xF871)
#define PROC_RECOVERY_MEM_NB_RB_MRNRB_FILECODE (0xF881)
#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0xF8C1)
#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0xF8C2)
#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0xF8C3)
#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0xF8C4)
#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0xF8C5)
#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0xF8C6)
#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0xF8C7)
#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0xF8C8)
#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0xF8C9)
#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0xF8CA)
#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0xF8CB)
#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0xF8CC)
#define PROC_RECOVERY_MEM_NB_OR_MRNDCTOR_FILECODE (0xF8CD)
#define PROC_RECOVERY_MEM_NB_OR_MRNOR_FILECODE (0xF8CE)
#define PROC_RECOVERY_MEM_NB_OR_MRNMCTOR_FILECODE (0xF8CF)
#define PROC_RECOVERY_MEM_NB_OR_MRNPROTOOR_FILECODE (0xF8D0)
#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0xF8E0)
#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0xF8E1)
#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0xF8E2)
#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0xF8E3)
#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0xF8E4)
#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0xF8E5)
#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0xF8E6)
#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0xF8E7)
#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0xF8E8)
#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0xF8E9)
#define PROC_RECOVERY_MEM_PS_OR_MRPOR3_FILECODE (0xF8EA)
#define PROC_RECOVERY_MEM_PS_OR_AM3_MRPSORA3_FILECODE (0xF8EB)
#define PROC_RECOVERY_MEM_PS_OR_AM3_MRPUORA3_FILECODE (0xF8EC)
#define PROC_RECOVERY_MEM_PS_OR_C32_MRPUORC3_FILECODE (0xF8ED)
#define PROC_RECOVERY_MEM_PS_OR_C32_MRPRORC3_FILECODE (0xF8EE)
#define PROC_RECOVERY_MEM_PS_OR_C32_MRPLORC3_FILECODE (0xF8EF)
#define PROC_RECOVERY_MEM_PS_OR_G34_MRPUORG3_FILECODE (0xF8F0)
#define PROC_RECOVERY_MEM_PS_OR_G34_MRPRORG3_FILECODE (0xF8F1)
#define PROC_RECOVERY_MEM_PS_OR_G34_MRPLORG3_FILECODE (0xF8F2)
#endif // _FILECODE_H_

203
src/vendorcode/amd/agesa/f14/Include/GeneralServices.h
View File

@@ -1,203 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* General Services
*
* Provides Services similar to the external General Services API, except
* suited to use within AGESA components. Socket, Core and PCI identification.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Common
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _GENERAL_SERVICES_H_
#define _GENERAL_SERVICES_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
#define NUMBER_OF_EVENT_DATA_PARAMS 4
/**
* AMD Device id for MMIO check.
*/
#define AMD_DEV_VEN_ID 0x1022
#define AMD_DEV_VEN_ID_ADDRESS 0
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/**
* An AGESA Event Log entry.
*/
typedef struct {
AGESA_STATUS EventClass; ///< The severity of the event, its associated AGESA_STATUS.
UINT32 EventInfo; ///< Uniquely identifies the event.
UINT32 DataParam1; ///< Event specific additional data
UINT32 DataParam2; ///< Event specific additional data
UINT32 DataParam3; ///< Event specific additional data
UINT32 DataParam4; ///< Event specific additional data
} AGESA_EVENT;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
/**
* Get a specified Core's APIC ID.
*
* @param[in] StdHeader Header for library and services.
* @param[in] Socket The Core's Socket.
* @param[in] Core The Core id.
* @param[out] ApicAddress The Core's APIC ID.
* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
*
* @retval TRUE The core is present, APIC Id valid
* @retval FALSE The core is not present, APIC Id not valid.
*/
BOOLEAN
GetApicId (
IN AMD_CONFIG_PARAMS *StdHeader,
IN UINT32 Socket,
IN UINT32 Core,
OUT UINT8 *ApicAddress,
OUT AGESA_STATUS *AgesaStatus
);
/**
* Get Processor Module's PCI Config Space address.
*
* @param[in] StdHeader Header for library and services.
* @param[in] Socket The Core's Socket.
* @param[in] Module The Module in that Processor
* @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0)
* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
*
* @retval TRUE The core is present, PCI Address valid
* @retval FALSE The core is not present, PCI Address not valid.
*/
BOOLEAN
GetPciAddress (
IN AMD_CONFIG_PARAMS *StdHeader,
IN UINT32 Socket,
IN UINT32 Module,
OUT PCI_ADDR *PciAddress,
OUT AGESA_STATUS *AgesaStatus
);
/**
* "Who am I" for the current running core.
*
* @param[in] StdHeader Header for library and services.
* @param[out] Socket The current Core's Socket
* @param[out] Module The current Core's Processor Module
* @param[out] Core The current Core's core id.
* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
*
*/
VOID
IdentifyCore (
IN AMD_CONFIG_PARAMS *StdHeader,
OUT UINT32 *Socket,
OUT UINT32 *Module,
OUT UINT32 *Core,
OUT AGESA_STATUS *AgesaStatus
);
/**
* A boolean function determine executed CPU is BSP core.
*/
BOOLEAN
IsBsp (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
OUT AGESA_STATUS *AgesaStatus
);
/**
* This function logs AGESA events into the event log.
*/
VOID
PutEventLog (
IN AGESA_STATUS EventClass,
IN UINT32 EventInfo,
IN UINT32 DataParam1,
IN UINT32 DataParam2,
IN UINT32 DataParam3,
IN UINT32 DataParam4,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function gets event logs from the circular buffer.
*/
AGESA_STATUS
GetEventLog (
OUT AGESA_EVENT *EventRecord,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function gets event logs from the circular buffer without flushing the entry.
*/
BOOLEAN
PeekEventLog (
OUT AGESA_EVENT *EventRecord,
IN UINT16 Index,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*---------------------------------------------------------------------------------------*/
/**
* This routine programs the registers necessary to get the PCI MMIO mechanism
* up and functioning.
*/
VOID
InitializePciMmio (
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _GENERAL_SERVICES_H_

96
src/vendorcode/amd/agesa/f14/Include/GnbInterface.h
View File

@@ -1,96 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* GNB API definition.
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
* @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************
*
*/
#ifndef _GNBINTERFACE_H_
#define _GNBINTERFACE_H_
AGESA_STATUS
GnbInitAtReset (
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
GnbInitAtEarly (
IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
);
AGESA_STATUS
GnbInitAtPost (
IN OUT AMD_POST_PARAMS *PostParamsPtr
);
VOID
GnbInitDataStructAtEnvDef (
IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr,
IN AMD_ENV_PARAMS *EnvParamsPtr
);
AGESA_STATUS
GnbInitAtEnv (
IN AMD_ENV_PARAMS *EnvParamsPtr
);
AGESA_STATUS
GnbInitAtMid (
IN OUT AMD_MID_PARAMS *MidParamsPtr
);
AGESA_STATUS
GnbInitAtLate (
IN OUT AMD_LATE_PARAMS *LateParamsPtr
);
AGESA_STATUS
GnbInitAtPostAfterDram (
IN OUT AMD_POST_PARAMS *PostParamsPtr
);
AGESA_STATUS
AmdGnbRecovery (
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif

232
src/vendorcode/amd/agesa/f14/Include/GnbInterfaceStub.h
View File

@@ -1,232 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
*
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
* @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Reset Stub
*
*
*
* @param[in] StdHeader Standard configuration header
* @retval AGESA_STATUS Always succeeds
*/
AGESA_STATUS
GnbInitAtReset (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Early Stub
*
*
*
* @param[in,out] EarlyParamsPtr Pointer to early configuration params.
* @retval AGESA_STATUS Always succeeds
*/
AGESA_STATUS
GnbInitAtEarly (
IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Default constructor of GNB configuration at Env
*
*
*
* @param[in] GnbEnvConfigPtr Pointer to gnb env configuration params.
* @param[in] EnvParamsPtr Pointer to env configuration params.
*/
VOID
GnbInitDataStructAtEnvDef (
IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr,
IN AMD_ENV_PARAMS *EnvParamsPtr
)
{
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Env
*
*
*
* @param[in] EnvParamsPtr Pointer to env configuration params.
* @retval AGESA_STATUS Always succeeds
*/
AGESA_STATUS
GnbInitAtEnv (
IN AMD_ENV_PARAMS *EnvParamsPtr
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Post
*
*
*
* @param[in,out] PostParamsPtr Pointer to Post configuration params.
* @retval AGESA_STATUS Always succeeds
*/
AGESA_STATUS
GnbInitAtPost (
IN OUT AMD_POST_PARAMS *PostParamsPtr
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Mid post
*
*
*
* @param[in,out] MidParamsPtr Pointer to mid configuration params.
* @retval AGESA_STATUS Always succeeds
*/
AGESA_STATUS
GnbInitAtMid (
IN OUT AMD_MID_PARAMS *MidParamsPtr
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Late post
*
*
*
* @param[in,out] LateParamsPtr Pointer to late configuration params.
* @retval AGESA_STATUS Always succeeds
*/
AGESA_STATUS
GnbInitAtLate (
IN OUT AMD_LATE_PARAMS *LateParamsPtr
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* AmdGnbRecovery
*
*
*
* @param[in] StdHeader Standard configuration header
* @retval AGESA_STATUS Always succeeds
*/
AGESA_STATUS
AmdGnbRecovery (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Post after DRAM init
*
*
*
* @param[in] PostParamsPtr Pointer to post configuration parameters
* @retval Initialization status.
*/
AGESA_STATUS
GnbInitAtPostAfterDram (
IN OUT AMD_POST_PARAMS *PostParamsPtr
)
{
return AGESA_SUCCESS;
}

919
src/vendorcode/amd/agesa/f14/Include/Ids.h
View File

@@ -1,919 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD IDS Routines
*
* Contains AMD AGESA Integrated Debug Macros
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: IDS
* @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/* Macros to aid debugging */
/* These definitions expand to zero (0) bytes of code when disabled */
#ifndef _IDS_H_
#define _IDS_H_
#undef FALSE
#undef TRUE
#define FALSE 0
#define TRUE 1
// Proto type for optionsids.h
typedef UINT32 IDS_STATUS; ///< Status of IDS function.
#define IDS_SUCCESS ((IDS_STATUS) 0x00000000) ///< IDS Function is Successful.
#define IDS_UNSUPPORTED ((IDS_STATUS) 0xFFFFFFFF) ///< IDS Function is not existed.
#define IDS_STRINGIZE(a) #a ///< for define stringize macro
/**
* IDS Option Hook Points
*
* These are the values to indicate hook point in AGESA for IDS Options.
*
*/
typedef enum { //vv- for debug reference only
IDS_INIT_EARLY_BEFORE, ///< 00 Option Hook Point before AGESA function AMD_INIT_EARLY.
///< IDS Object is initialized.
///< Override CPU Core Leveling Mode.
///< Set P-State in Post
IDS_INIT_EARLY_AFTER, ///< 01 Option Hook Point after AGESA function AMD_INIT_EARLY.
IDS_INIT_LATE_BEFORE, ///< 02 Option Hook Point before AGESA function AMD_INIT_LATE.
///< It will be used to control the following tables.
///< ACPI P-State Table (_PSS, XPSS, _PCT, _PSD, _PPC)
///< ACPI SRAT Table
///< ACPI SLIT Table
///< ACPI WHEA Table
///< DMI Table
IDS_INIT_LATE_AFTER, ///< 03 Option Hook Point after AGESA function AMD_INIT_LATE.
IDS_INIT_MID_BEFORE, ///< 04 Option Hook Point before AGESA function AMD_INIT_MID.
IDS_INIT_MID_AFTER, ///< 05 Option Hook Point after AGESA function AMD_INIT_MID.
IDS_INIT_POST_BEFORE, ///< 06 Option Hook Point before AGESA function AMD_INIT_POST.
///< Control Interleaving and DRAM memory hole
///< Override the setting of ECC Control
///< Override the setting of Online Spare Rank
IDS_INIT_POST_AFTER, ///< 07 Option Hook Point after AGESA function AMD_INIT_POST.
IDS_INIT_RESET_BEFORE, ///< 08 Option Hook Point before AGESA function AMD_INIT_RESET.
IDS_INIT_RESET_AFTER, ///< 09 Option Hook Point after AGESA function AMD_INIT_RESET.
IDS_INIT_POST_MID, ///< 0a Option Hook Point after AGESA function AMD_INIT_POST.
IDS_BEFORE_S3_SAVE, ///< 0b override any settings before S3 save.
IDS_BEFORE_S3_RESTORE, ///< 0c override any settings before S3 restore
IDS_AFTER_S3_SAVE, ///< 0d Override any settings after S3 save
IDS_AFTER_S3_RESTORE, ///< 0e Override any settings after S3 restore
IDS_BEFORE_DQS_TRAINING, ///< 0f override any settings before DQS training
IDS_BEFORE_DRAM_INIT, ///< 10 override any settings before Dram initialization
IDS_BEFORE_MEM_FREQ_CHG, ///< 11 override settings before MemClk frequency change
IDS_BEFORE_WARM_RESET , ///< 12 Override PCI or MSR Registers Before Warm Reset
IDS_BEFORE_MEM_INIT, ///< 13 Override PCI or MSR Registers Before Memory Init
IDS_BEFORE_PCI_INIT, ///< 14 Override PCI or MSR Registers Before PCI Init
IDS_BEFORE_OS, ///< 15 Override PCI or MSR Registers Before booting to OS
IDS_UCODE, ///< 16 Enable or Disable microcode patching
IDS_BEFORE_AP_EARLY_HALT, ///< 17 Option Hook Point before AP early halt
IDS_PLATFORM_RSVD1 = 0x38, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD2 = 0x39, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD3 = 0x3a, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD4 = 0x3b, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD5 = 0x3c, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD6 = 0x3d, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD7 = 0x3e, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD8 = 0x3f, ///< from 0x38 to 0x3f will reserved for platform used
// All the above timing point is used by BVM, their value should never be changed
IDS_HT_CONTROL, ///< 40 Override the setting of HT Link Control
IDS_HT_TRISTATE, ///< 41 Enable or Disable HT Tri-state during an LDTSTP#
IDS_INIT_DRAM_TABLE, ///< 42 Generate override table for Dram Timing
///< Dram Controller, Drive Strength and DQS Timing
IDS_GET_DRAM_TABLE, ///< 43 Generate override table for Dram Timing
IDS_GANGING_MODE, ///< 44 override Memory Mode Unganged
IDS_POWERDOWN_MODE, ///< 45 override Power Down Mode
IDS_BURST_LENGTH32, ///< 46 override Burst Length32
IDS_ALL_MEMORY_CLOCK, ///< 47 override All Memory Clks Enable
IDS_ECC, ///< 48 override ECC parameter
IDS_ECCSYMBOLSIZE, ///< 49 override ECC symbol size
IDS_CPU_Early_Override, ///< 4a override CPU early parameter
IDS_CACHE_FLUSH_HLT, ///< 4b override Cache Flush Hlt
IDS_CHANNEL_INTERLEAVE, ///< 4c override Channel Interleave
IDS_MEM_ERROR_RECOVERY, ///< 4d override memory error recovery
IDS_MEM_RETRAIN_TIMES, ///< 4e override memory retrain times
IDS_MEM_SIZE_OVERLAY, ///< 4f Override the syslimit
IDS_HT_ASSIST, ///< 50 Override Probe Filter
IDS_CHECK_NEGATIVE_WL, ///< 51 Check for negative write leveling result
IDS_DLL_SHUT_DOWN, ///< 52 Check for Dll Shut Down
IDS_POR_MEM_FREQ, ///< 53 Entry to enable/disable MemClk frequency enforcement
IDS_PHY_DLL_STANDBY_CTRL, ///< 54 Enable/Disable Phy DLL standby feature
IDS_PLATFORMCFG_OVERRIDE, ///< 55 Hook for Override PlatformConfig structure
IDS_LOADCARD_ERROR_RECOVERY, ///< 56 Special error handling for load card support
IDS_MEM_IGNORE_ERROR, ///< 57 Ignore error and do not do fatal exit in memory
IDS_GNB_SMU_SERVICE_CONFIG, ///< 58 Config GNB SMU service
IDS_GNB_ORBDYNAMIC_WAKE, ///< 59 config GNB dynamic wake
IDS_GNB_PLATFORMCFG_OVERRIDE, ///< 5a override ids gnb platform config
IDS_GNB_LCLK_DPM_EN, ///< 5b override GNB LCLK DPM configuration
IDS_GNB_LCLK_DEEP_SLEEP, ///< 5c override GNB LCLK DPM deep sleep
IDS_GNB_CLOCK_GATING, ///< 5d Override GNB Clock gating config
IDS_NB_PSTATE_DIDVID, ///< 5e Override NB P-state settings
IDS_CPB_CTRL, ///< 5f Config the Core peformance boost feature
IDS_HTC_CTRL, ///< 60 Hook for Hardware Thermal Control
IDS_CC6_WORKAROUND, ///< 61 Hook for skip CC6 work around
IDS_MEM_MR0, ///< 62 Hook for override Memory Mr0 register
IDS_REG_TABLE, ///< 63 Hook for add IDS register table to the loop
IDS_NBBUFFERALLOCATIONATEARLY, ///< 64 Hook for override North bridge bufer allocation
IDS_BEFORE_S3_SPECIAL, ///< 65 Hook to bypass S3 special functions
IDS_SET_PCI_REGISTER_ENTRY, ///< 66 Hook to SetRegisterForPciEntry
IDS_ERRATUM463_WORKAROUND, ///< 67 Hook to Erratum 463 workaround
IDS_BEFORE_MEMCLR, ///< 68 Hook before set Memclr bit
IDS_OVERRIDE_IO_CSTATE, ///< 69 Hook for override io C-state setting
IDS_NBPSDIS_OVERRIDE, ///< 6a Hook for override NB pstate disable setting
IDS_NBPS_REG_OVERRIDE, ///< 6b Hook for override Memory NBps reg
IDS_LOW_POWER_PSTATE, ///< 6c Hook for disalbe Low power_Pstates feature
IDS_CST_CREATE, ///< 6d Hook for create _CST
IDS_CST_SIZE, ///< 6e Hook for get _CST size
IDS_ENFORCE_VDDIO, ///< 6f Hook to override VDDIO
IDS_SKIP_PERFORMANCE_OPT, ///< 70 Hook to skip performance optimization
IDS_INIT_MEM_REG_TABLE, ///< 71 Hook for init memory register table
IDS_SKIP_FUSED_MAX_RATE ///< 72 Hook to skip fused max rate cap
} AGESA_IDS_OPTION;
#include "OptionsIds.h"
#include "Filecode.h"
/* Initialize IDS controls */
#ifndef IDSOPT_IDS_ENABLED
#define IDSOPT_IDS_ENABLED FALSE
#endif
#ifndef IDSOPT_CONTROL_ENABLED
#define IDSOPT_CONTROL_ENABLED FALSE
#endif
#ifndef IDSOPT_TRACING_ENABLED
#define IDSOPT_TRACING_ENABLED FALSE
#endif
#ifndef IDSOPT_TRACE_USER_OPTIONS
#define IDSOPT_TRACE_USER_OPTIONS TRUE
#endif
#ifndef IDSOPT_PERF_ANALYSIS
#define IDSOPT_PERF_ANALYSIS FALSE
#endif
#ifndef IDSOPT_HEAP_CHECKING
#define IDSOPT_HEAP_CHECKING FALSE
#endif
#ifndef IDSOPT_ASSERT_ENABLED
#define IDSOPT_ASSERT_ENABLED FALSE
#endif
#ifndef IDSOPT_ERROR_TRAP_ENABLED
#define IDSOPT_ERROR_TRAP_ENABLED FALSE
#endif
#ifndef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
#define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
#endif
#ifndef IDSOPT_DEBUG_CODE_ENABLED
#define IDSOPT_DEBUG_CODE_ENABLED FALSE
#endif
#ifndef IDSOPT_C_OPTIMIZATION_DISABLED
#define IDSOPT_C_OPTIMIZATION_DISABLED FALSE
#endif
#if IDSOPT_IDS_ENABLED == FALSE
#undef IDSOPT_CONTROL_ENABLED
#undef IDSOPT_TRACING_ENABLED
#undef IDSOPT_PERF_ANALYSIS
#undef IDSOPT_HEAP_CHECKING
#undef IDSOPT_ASSERT_ENABLED
#undef IDSOPT_ERROR_TRAP_ENABLED
#undef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
#undef IDSOPT_DEBUG_CODE_ENABLED
#undef IDSOPT_TRACE_USER_OPTIONS
#define IDSOPT_CONTROL_ENABLED FALSE
#define IDSOPT_TRACING_ENABLED FALSE
#define IDSOPT_PERF_ANALYSIS FALSE
#define IDSOPT_HEAP_CHECKING FALSE
#define IDSOPT_ASSERT_ENABLED FALSE
#define IDSOPT_ERROR_TRAP_ENABLED FALSE
#define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
#define IDSOPT_DEBUG_CODE_ENABLED FALSE
#define IDSOPT_TRACE_USER_OPTIONS FALSE
#endif
/**
* Make a Progress Report to the User.
*
* This Macro is always enabled. The default action is to write the TestPoint value
* to an I/O port. The I/O port is 8 bits in size and the default address is 0x80.
* IBVs can change AGESA's default port by defining IDS_DEBUG_PORT to desired port
* in OptionsIds.h in their build tip.
*
* @param[in] TestPoint The value for display indicating progress
* @param[in,out] StdHeader Pointer of AMD_CONFIG_PARAMS
*
**/
#define AGESA_TESTPOINT(TestPoint, StdHeader)
#ifndef IDS_DEBUG_PORT
#define IDS_DEBUG_PORT 0x80
#endif
/**
* @def STOP_HERE
* (macro) - Causes program to halt. This is @b only for use during active debugging .
*
* Causes the program to halt and display the file number of the source of the
* halt (displayed in decimal).
*
**/
#if IDSOPT_IDS_ENABLED == TRUE
#ifdef STOP_CODE
#undef STOP_CODE
#endif
#define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
(((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
#define STOP_HERE
#else
#define STOP_HERE
#endif
/**
* @def ASSERT
* Test an assertion that the given statement is True.
*
* The statement is evaluated to a boolean value. If the statement is True,
* then no action is taken (no error). If the statement is False, a error stop
* is generated to halt the program. Used for testing for fatal errors that
* must be resolved before production. This is used to do parameter checks,
* bounds checking, range checks and 'sanity' checks.
*
* @param[in] conditional Assert that evaluating this conditional results in TRUE.
*
**/
#ifndef ASSERT
#if IDSOPT_ASSERT_ENABLED == TRUE
#ifdef STOP_CODE
#undef STOP_CODE
#endif
#define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
(((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
#define ASSERT(conditional)
#else
#define ASSERT(conditional)
#endif
#endif
#if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE
#undef IDSOPT_ERROR_TRAP_ENABLED
#define IDSOPT_ERROR_TRAP_ENABLED TRUE
#define IDS_CAR_CORRUPTION_CHECK(StdHeader)
#else
#define IDS_CAR_CORRUPTION_CHECK(StdHeader)
#endif
/**
* @def DEBUG_CODE
* Make the code active when IDSOPT_DEBUG_CODE_ENABLED enable
*
*/
#ifndef DEBUG_CODE
#if IDSOPT_DEBUG_CODE_ENABLED == TRUE
#define DEBUG_CODE(Code)
#else
#define DEBUG_CODE(Code)
#endif
#endif
/**
* @def IDS_ERROR_TRAP
* Trap AGESA Error events with stop code display.
*
* Works similarly to use of "ASSERT (FALSE);"
*
*/
#if IDSOPT_ERROR_TRAP_ENABLED == TRUE
#ifdef STOP_CODE
#undef STOP_CODE
#endif
#define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
(((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
#define IDS_ERROR_TRAP
#else
#define IDS_ERROR_TRAP
#endif
///give the extended Macro default value
#ifndef __IDS_EXTENDED__
#define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS
#define IDS_INITIAL_F10_PM_STEP
#define IDS_INITIAL_F12_PM_STEP
#define IDS_INITIAL_F14_PM_STEP
#define IDS_INITIAL_F15_PM_STEP
#define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader)
#define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader)
#define IDS_EXTENDED_HEAP_SIZE 0
#define IDS_EXT_INCLUDE_F10(file)
#define IDS_EXT_INCLUDE_F12(file)
#define IDS_EXT_INCLUDE_F14(file)
#define IDS_EXT_INCLUDE_F15(file)
#define IDS_EXT_INCLUDE(file)
#endif
#ifndef IDS_NUM_NV_ITEM
#define IDS_NUM_NV_ITEM (IDS_NUM_EXT_NV_ITEM)
#endif
#if IDSOPT_CONTROL_ENABLED == TRUE
#define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
#define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader)
#else
#define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
#define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader)
#endif
/**
* Macro to add a *skip* hook for IDS options
*
* The default minimal action is to do nothing and there is no any code to increase.
* For debug environments, IDS dispatcher function will be called to perform
* the detailed action and to skip AGESA code if necessary.
*
* @param[in] IdsOption IDS Option ID for this hook point
* @param[in, out] DataPtr Data Pointer to override
* @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS
*
*
**/
#if IDSOPT_CONTROL_ENABLED == TRUE
#define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
#else
#define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
#endif
/**
* Macro to add a heap manager routine
*
* when memory is allocated the heap manager actually allocates two extra dwords of data,
* one dword buffer before the actual memory, and one dword afterwards.
* a complete heap walk and check to be performed at any time.
* it would ASSERT if the heap is corrupt
*
* @param[in] StdHeader Pointer of AMD_CONFIG_PARAMS
*
*
**/
// Heap debug feature
#define SENTINEL_BEFORE_VALUE 0x64616548 // "Head"
#define SENTINEL_AFTER_VALUE 0x6C696154 // "Tail"
#if IDSOPT_IDS_ENABLED == TRUE
#if IDSOPT_HEAP_CHECKING == TRUE
#define SIZE_OF_SENTINEL 0
#define NUM_OF_SENTINEL 0
#define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
#define SET_SENTINEL_AFTER(NodePtr)
#define Heap_Check(stdheader)
#else
#define SIZE_OF_SENTINEL 0
#define NUM_OF_SENTINEL 0
#define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
#define SET_SENTINEL_AFTER(NodePtr)
#define Heap_Check(stdheader)
#endif
#else
#define SIZE_OF_SENTINEL 0
#define NUM_OF_SENTINEL 0
#define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
#define SET_SENTINEL_AFTER(NodePtr)
#define Heap_Check(stdheader)
#endif
//Note a is from 0 to 63
#define DEBUG_PRINT_SHIFT(a) ((UINT64)1 << a)
//If you change the Bitmap definition below, please change the Hash in ParseFilter of hdtout2008.pl accordingly
//Memory Masks
#define MEM_SETREG DEBUG_PRINT_SHIFT (0)
#define MEM_GETREG DEBUG_PRINT_SHIFT (1)
#define MEM_FLOW DEBUG_PRINT_SHIFT (2)
#define MEM_STATUS DEBUG_PRINT_SHIFT (3)
#define MEMORY_TRACE_RSV1 DEBUG_PRINT_SHIFT (4)
#define MEMORY_TRACE_RSV2 DEBUG_PRINT_SHIFT (5)
#define MEMORY_TRACE_RSV3 DEBUG_PRINT_SHIFT (6)
#define MEMORY_TRACE_RSV4 DEBUG_PRINT_SHIFT (7)
#define MEMORY_TRACE_RSV5 DEBUG_PRINT_SHIFT (8)
#define MEMORY_TRACE_RSV6 DEBUG_PRINT_SHIFT (9)
//CPU Masks
#define CPU_TRACE DEBUG_PRINT_SHIFT (10)
#define CPU_TRACE_RSV1 DEBUG_PRINT_SHIFT (11)
#define CPU_TRACE_RSV2 DEBUG_PRINT_SHIFT (12)
#define CPU_TRACE_RSV3 DEBUG_PRINT_SHIFT (13)
#define CPU_TRACE_RSV4 DEBUG_PRINT_SHIFT (14)
#define CPU_TRACE_RSV5 DEBUG_PRINT_SHIFT (15)
#define CPU_TRACE_RSV6 DEBUG_PRINT_SHIFT (16)
#define CPU_TRACE_RSV7 DEBUG_PRINT_SHIFT (17)
#define CPU_TRACE_RSV8 DEBUG_PRINT_SHIFT (18)
#define CPU_TRACE_RSV9 DEBUG_PRINT_SHIFT (19)
//GNB Masks
#define GNB_TRACE DEBUG_PRINT_SHIFT (20)
#define PCIE_MISC DEBUG_PRINT_SHIFT (21)
#define PCIE_PORTREG_TRACE DEBUG_PRINT_SHIFT (22)
#define PCIE_HOSTREG_TRACE DEBUG_PRINT_SHIFT (23)
#define GNB_TRACE_RSV2 DEBUG_PRINT_SHIFT (24)
#define NB_MISC DEBUG_PRINT_SHIFT (25)
#define GNB_TRACE_RSV3 DEBUG_PRINT_SHIFT (26)
#define GFX_MISC DEBUG_PRINT_SHIFT (27)
#define NB_SMUREG_TRACE DEBUG_PRINT_SHIFT (28)
#define GNB_TRACE_RSV1 DEBUG_PRINT_SHIFT (29)
//HT Masks
#define HT_TRACE DEBUG_PRINT_SHIFT (30)
#define HT_TRACE_RSV1 DEBUG_PRINT_SHIFT (31)
#define HT_TRACE_RSV2 DEBUG_PRINT_SHIFT (32)
#define HT_TRACE_RSV3 DEBUG_PRINT_SHIFT (33)
#define HT_TRACE_RSV4 DEBUG_PRINT_SHIFT (34)
#define HT_TRACE_RSV5 DEBUG_PRINT_SHIFT (35)
#define HT_TRACE_RSV6 DEBUG_PRINT_SHIFT (36)
#define HT_TRACE_RSV7 DEBUG_PRINT_SHIFT (37)
#define HT_TRACE_RSV8 DEBUG_PRINT_SHIFT (38)
#define HT_TRACE_RSV9 DEBUG_PRINT_SHIFT (39)
//FCH Masks
#define FCH_TRACE DEBUG_PRINT_SHIFT (40)
#define FCH_TRACE_RSV1 DEBUG_PRINT_SHIFT (41)
#define FCH_TRACE_RSV2 DEBUG_PRINT_SHIFT (42)
#define FCH_TRACE_RSV3 DEBUG_PRINT_SHIFT (43)
#define FCH_TRACE_RSV4 DEBUG_PRINT_SHIFT (44)
#define FCH_TRACE_RSV5 DEBUG_PRINT_SHIFT (45)
#define FCH_TRACE_RSV6 DEBUG_PRINT_SHIFT (46)
#define FCH_TRACE_RSV7 DEBUG_PRINT_SHIFT (47)
#define FCH_TRACE_RSV8 DEBUG_PRINT_SHIFT (48)
#define FCH_TRACE_RSV9 DEBUG_PRINT_SHIFT (49)
//Other Masks
#define MAIN_FLOW DEBUG_PRINT_SHIFT (50)
#define EVENT_LOG DEBUG_PRINT_SHIFT (51)
#define PERFORMANCE_ANALYSE DEBUG_PRINT_SHIFT (52)
//Ids Masks
#define IDS_TRACE DEBUG_PRINT_SHIFT (53)
#define IDS_REG DEBUG_PRINT_SHIFT (54)
#define IDS_TRACE_RSV2 DEBUG_PRINT_SHIFT (55)
#define IDS_TRACE_RSV3 DEBUG_PRINT_SHIFT (56)
//S3
#define S3_TRACE DEBUG_PRINT_SHIFT (57)
//Reserved
#define TRACE_RSV1 DEBUG_PRINT_SHIFT (58)
#define TRACE_RSV2 DEBUG_PRINT_SHIFT (59)
#define TRACE_RSV3 DEBUG_PRINT_SHIFT (60)
#define TRACE_RSV4 DEBUG_PRINT_SHIFT (61)
#define TRACE_RSV5 DEBUG_PRINT_SHIFT (62)
#define TRACE_RSV6 DEBUG_PRINT_SHIFT (63)
#define GNB_TRACE_DEFAULT 0
#define GNB_TRACE_REG 0
#define GNB_TRACE_ALL 0
#define CPU_TRACE_ALL 0
#define MEMORY_TRACE_ALL 0
#define HT_TRACE_ALL 0
#define FCH_TRACE_ALL 0
#define IDS_TRACE_ALL 0
#define OTHER_TRACE_ALL 0
#define TRACE_MASK_ALL (0ull)
#ifndef IDS_DEBUG_PRINT_MASK
#define IDS_DEBUG_PRINT_MASK 0
#endif
/**
* Macro to add HDT OUT
*
* The default minimal action is to do nothing and there is no any code to increase.
* For debug environments, the debug information can be displayed in HDT or other
* devices.
*
**/
#if IDSOPT_IDS_ENABLED == TRUE
#if IDSOPT_TRACING_ENABLED == TRUE
#define IDS_HDT_CONSOLE_INIT(x)
#define IDS_HDT_CONSOLE_EXIT(x)
#define IDS_HDT_CONSOLE_S3_EXIT(x)
#define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
#ifndef __GNUC__
#pragma warning(disable: 4127)
#define IDS_HDT_CONSOLE(f, s, ...)
#else
#define IDS_HDT_CONSOLE(f, s, ...) printk (BIOS_DEBUG, s, ##__VA_ARGS__);
#endif
#define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
#define IDS_HDT_CONSOLE_ASSERT(x)
#define IDS_FUNCLIST_ADDR NULL
#define IDS_FUNCLIST_EXTERN()
#define IDS_TIMEOUT_CTL(t)
#define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
#define CONSOLE(s, ...)
#else
#define IDS_HDT_CONSOLE_INIT(x)
#define IDS_HDT_CONSOLE_EXIT(x)
#define IDS_HDT_CONSOLE_S3_EXIT(x)
#define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
#define IDS_HDT_CONSOLE(f, s, ...)
#define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
#define IDS_HDT_CONSOLE_ASSERT(x)
#define IDS_FUNCLIST_ADDR NULL
#define IDS_FUNCLIST_EXTERN()
#define IDS_TIMEOUT_CTL(t)
#define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
#define CONSOLE(s, ...)
#endif
#else
#define IDS_HDT_CONSOLE_INIT(x)
#define IDS_HDT_CONSOLE_EXIT(x)
#define IDS_HDT_CONSOLE_S3_EXIT(x)
#define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
#define IDS_HDT_CONSOLE(f, s, ...)
#define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
#define IDS_HDT_CONSOLE_ASSERT(x)
#define IDS_FUNCLIST_ADDR NULL
#define IDS_FUNCLIST_EXTERN()
#define IDS_TIMEOUT_CTL(t)
#define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
#define CONSOLE(s, ...)
#endif
#define IDS_TRACE_SHOW_BLD_OPT_CFG IDSOPT_TRACE_USER_OPTIONS
#if IDSOPT_PERF_ANALYSIS == TRUE
#define IDS_PERF_TIMESTAMP(StdHeader, TestPoint)
#define IDS_PERF_ANALYSE(StdHeader)
#define IDS_PERF_TIME_MEASURE(StdHeader)
#else
#define IDS_PERF_TIMESTAMP(StdHeader, TestPoint)
#define IDS_PERF_ANALYSE(StdHeader)
#define IDS_PERF_TIME_MEASURE(StdHeader)
#endif
///For IDS feat use
#define IDS_FAMILY_ALL 0xFFFFFFFFFFFFFFFFull
#define IDS_BSP_ONLY TRUE
#define IDS_ALL_CORES FALSE
#define IDS_LATE_RUN_AP_TASK_ID PROC_IDS_CONTROL_IDSLIB_FILECODE
#define IDS_CALLOUT_INIT 0x00 ///< The function data of IDS callout function of initialization.
#define IDS_CALLOUT_GNB_PPFUSE_OVERRIDE 0x00 ///< The function data of IDS callout function of GNB pp fuse table.
#define IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG 0x00 ///< The function data of IDS callout function of GNB integrated table.
#define IDS_CALLOUT_GNB_NB_POWERGATE_CONFIG 0x00 ///< The function data of IDS callout function of GNB NB power gate config.
#define IDS_CALLOUT_GNB_PCIE_POWERGATE_CONFIG 0x00 ///< The function data of IDS callout function of GNB PCIE power gateconfig.
#define IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG 0x00 ///< The function data of IDS callout function of GNB pcie platform config.
#define IDS_CALLOUT_GNB_PCIE_PHY_CONFIG 0x00 ///< The function data of IDS callout function of GNB pcie PHY config.
#define IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE 0x00 ///< The function data of IDS callout function of GNB GMM register override
/// Function entry for HDT script to call
typedef struct _SCRIPT_FUNCTION {
UINTN FuncAddr; ///< Function address in ROM
CHAR8 FuncName[40]; ///< Function name
} SCRIPT_FUNCTION;
/// Data Structure for Mem ECC parameter override
typedef struct {
IN BOOLEAN CfgEccRedirection; ///< ECC Redirection
IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate
IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate
IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate
IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate
IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate
IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood
} ECC_OVERRIDE_STRUCT;
/**
* AGESA Test Points
*
* These are the values displayed to the user to indicate progress through boot.
* These can be used in a debug environment to stop the debugger at a specific
* test point:
* For SimNow!, this command
* bi 81 w vb 49
* will stop the debugger on one of the TracePoints (49 is the TP value in this example).
*
*/
typedef enum {
StartProcessorTestPoints, ///< 00 Entry used for range testing for @b Processor related TPs
// Memory test points
TpProcMemBeforeMemDataInit, ///< 01 .. Memory structure initialization (Public interface)
TpProcMemBeforeSpdProcessing, ///< 02 .. SPD Data processing (Public interface)
TpProcMemAmdMemAuto, ///< 03 .. Memory configuration (Public interface)
TpProcMemDramInit, ///< 04 .. DRAM initialization
TpProcMemSPDChecking, ///< 05 ..
TpProcMemModeChecking, ///< 06 ..
TpProcMemSpeedTclConfig, ///< 07 .. Speed and TCL configuration
TpProcMemSpdTiming, ///< 08 ..
TpProcMemDramMapping, ///< 09 ..
TpProcMemPlatformSpecificConfig, ///< 0A ..
TPProcMemPhyCompensation, ///< 0B ..
TpProcMemStartDcts, ///< 0C ..
TpProcMemBeforeDramInit, ///< 0D .. (Public interface)
TpProcMemPhyFenceTraining, ///< 0E ..
TpProcMemSynchronizeDcts, ///< 0F ..
TpProcMemSystemMemoryMapping, ///< 10 ..
TpProcMemMtrrConfiguration, ///< 11 ..
TpProcMemDramTraining, ///< 12 ..
TpProcMemBeforeAnyTraining, ///< 13 .. (Public interface)
TpProcMemWriteLevelizationTraining, ///< 14 ..
TpProcMemWlFirstPass, ///< 15 .. Below 800Mhz first pass start
TpProcMemWlSecondPass, ///< 16 .. Above 800Mhz second pass start
TpProcMemWlDimmConfig, ///< 17 .. Target DIMM configured
TpProcMemWlPrepDimms, ///< 18 .. Prepare DIMMS for WL
TpProcMemWlConfigDimms, ///< 19 .. Configure DIMMS for WL
TpProcMemReceiverEnableTraining, ///< 1A ..
TpProcMemRcvrStartSweep, ///< 1B .. Start sweep loop
TpProcMemRcvrSetDelay, ///< 1C .. Set receiver Delay
TpProcMemRcvrWritePattern, ///< 1D .. Write test pattern
TpProcMemRcvrReadPattern, ///< 1E .. Read test pattern
TpProcMemRcvrTestPattern, ///< 1F .. Compare test pattern
TpProcMemRcvrCalcLatency, ///< 20 .. Calculate MaxRdLatency per channel
TpProcMemReceiveDqsTraining, ///< 21 ..
TpProcMemRcvDqsSetDelay, ///< 22 .. Set Write Data delay
TpProcMemRcvDqsWritePattern, ///< 23 .. Write test pattern
TpProcMemRcvDqsStartSweep, ///< 24 .. Start read sweep
TpProcMemRcvDqsSetRcvDelay, ///< 25 .. Set Receive DQS delay
TpProcMemRcvDqsReadPattern, ///< 26 .. Read Test pattern
TpProcMemRcvDqsTstPattern, ///< 27 .. Compare Test pattern
TpProcMemRcvDqsResults, ///< 28 .. Update results
TpProcMemRcvDqsFindWindow, ///< 29 .. Start Find passing window
TpProcMemTransmitDqsTraining, ///< 2A ..
TpProcMemTxDqStartSweep, ///< 2B .. Start write sweep
TpProcMemTxDqSetDelay, ///< 2C .. Set Transmit DQ delay
TpProcMemTxDqWritePattern, ///< 2D .. Write test pattern
TpProcMemTxDqReadPattern, ///< 2E .. Read Test pattern
TpProcMemTxDqTestPattern, ///< 2F .. Compare Test pattern
TpProcMemTxDqResults, ///< 30 .. Update results
TpProcMemTxDqFindWindow, ///< 31 .. Start Find passing window
TpProcMemMaxRdLatencyTraining, ///< 32 ..
TpProcMemMaxRdLatStartSweep, ///< 33 .. Start sweep
TpProcMemMaxRdLatSetDelay, ///< 34 .. Set delay
TpProcMemMaxRdLatWritePattern, ///< 35 .. Write test pattern
TpProcMemMaxRdLatReadPattern, ///< 36 .. Read Test pattern
TpProcMemMaxRdLatTestPattern, ///< 37 .. Compare Test pattern
TpProcMemOnlineSpareInit, ///< 38 .. Online Spare init
TpProcMemBankInterleaveInit, ///< 39 .. Bank Interleave Init
TpProcMemNodeInterleaveInit, ///< 3A .. Node Interleave Init
TpProcMemChannelInterleaveInit, ///< 3B .. Channel Interleave Init
TpProcMemEccInitialization, ///< 3C .. ECC initialization
TpProcMemPlatformSpecificInit, ///< 3D .. Platform Specific Init
TpProcMemBeforeAgesaReadSpd, ///< 3E .. Before callout for "AgesaReadSpd"
TpProcMemAfterAgesaReadSpd, ///< 3F .. After callout for "AgesaReadSpd"
TpProcMemBeforeAgesaHookBeforeDramInit, ///< 40 .. Before optional callout "AgesaHookBeforeDramInit"
TpProcMemAfterAgesaHookBeforeDramInit, ///< 41 .. After optional callout "AgesaHookBeforeDramInit"
TpProcMemBeforeAgesaHookBeforeDQSTraining, ///< 42 .. Before optional callout "AgesaHookBeforeDQSTraining"
TpProcMemAfterAgesaHookBeforeDQSTraining, ///< 43 .. After optional callout "AgesaHookBeforeDQSTraining"
TpProcMemBeforeAgesaHookBeforeExitSelfRef, ///< 44 .. Before optional callout "AgesaHookBeforeDramInit"
TpProcMemAfterAgesaHookBeforeExitSelfRef, ///< 45 .. After optional callout "AgesaHookBeforeDramInit"
TpProcMemAfterMemDataInit, ///< 46 .. After MemDataInit
TpProcMemInitializeMCT, ///< 47 .. Before InitializeMCT
TpProcMemLvDdr3, ///< 48 .. Before LV DDR3
TpProcMemInitMCT, ///< 49 .. Before InitMCT
TpProcMemOtherTiming, ///< 4A.. Before OtherTiming
TpProcMemUMAMemTyping, ///< 4B .. Before UMAMemTyping
TpProcMemSetDqsEccTmgs, ///< 4C .. Before SetDqsEccTmgs
TpProcMemMemClr, ///< 4D .. Before MemClr
TpProcMemOnDimmThermal, ///< 4E .. Before On DIMM Thermal
TpProcMemDmi, ///< 4F .. Before DMI
TpProcMemEnd, ///< 50 .. End of memory code
// CPU test points
TpProcCpuEntryDmi, ///< 51 .. Entry point CreateDmiRecords
TpProcCpuEntryPstate, ///< 52 .. Entry point GenerateSsdt
TpProcCpuEntryPstateLeveling, ///< 53 .. Entry point PStateLeveling
TpProcCpuEntryPstateGather, ///< 54 .. Entry point PStateGatherData
TpProcCpuEntryWhea, ///< 55 .. Entry point CreateAcpiWhea
TpProcCpuEntrySrat, ///< 56 .. Entry point CreateAcpiSrat
TpProcCpuEntrySlit, ///< 57 .. Entry point CreateAcpiSlit
TpProcCpuProcessRegisterTables, ///< 58 .. Register table processing
TpProcCpuSetBrandID, ///< 59 .. Set brand ID
TpProcCpuLocalApicInit, ///< 5A .. Initialize local APIC
TpProcCpuLoadUcode, ///< 5B .. Load microcode patch
TpProcCpuBeforePMFeatureInit, ///< 5C .. BeforePM feature dispatch point
TpProcCpuPowerMgmtInit, ///< 5D .. Power Management table processing
TpProcCpuEarlyFeatureInit, ///< 5E .. Early feature dispatch point
TpProcCpuCoreLeveling, ///< 5F .. Core Leveling
TpProcCpuApMtrrSync, ///< 60 .. AP MTRR sync up
TpProcCpuPostFeatureInit, ///< 61 .. POST feature dispatch point
TpProcCpuFeatureLeveling, ///< 62 .. CPU Feature Leveling
TpProcCpuBeforeAllocateWheaBuffer, ///< 63 .. Before the WHEA init code calls out to allocate a buffer
TpProcCpuAfterAllocateWheaBuffer, ///< 64 .. After the WHEA init code calls out to allocate a buffer
TpProcCpuBeforeAllocateSratBuffer, ///< 65 .. Before the SRAT init code calls out to allocate a buffer
TpProcCpuAfterAllocateSratBuffer, ///< 66 .. After the SRAT init code calls out to allocate a buffer
TpProcCpuBeforeLocateSsdtBuffer, ///< 67 .. Before the P-state init code calls out to locate a buffer
TpProcCpuAfterLocateSsdtBuffer, ///< 68 .. After the P-state init code calls out to locate a buffer
TpProcCpuBeforeAllocateSsdtBuffer, ///< 69 .. Before the P-state init code calls out to allocate a buffer
TpProcCpuAfterAllocateSsdtBuffer, ///< 6A .. After the P-state init code calls out to allocate a buffer
// HT test points
TpProcHtEntry = 0x71, ///< 71 .. Coherent Discovery begin (Public interface)
TpProcHtTopology, ///< 72 .. Topology match, routing, begin
TpProcHtManualNc, ///< 73 .. Manual Non-coherent Init begin
TpProcHtAutoNc, ///< 74 .. Automatic Non-coherent init begin
TpProcHtOptGather, ///< 75 .. Optimization: Gather begin
TpProcHtOptRegang, ///< 76 .. Optimization: Regang begin
TpProcHtOptLinks, ///< 77 .. Optimization: Link Begin
TpProcHtOptSubLinks, ///< 78 .. Optimization: Sublinks begin
TpProcHtOptFinish, ///< 79 .. Optimization: Set begin
TpProcHtTrafficDist, ///< 7A .. Traffic Distribution begin
TpProcHtTuning, ///< 7B .. Misc Tuning Begin
TpProcHtDone, ///< 7C .. HT Init complete
TpProcHtApMapEntry, ///< 7D .. AP HT: Init Maps begin
TpProcHtApMapDone, ///< 7E .. AP HT: Complete
StartNbTestPoints = 0x90, ///< 90 Entry used for range testing for @b NorthBridge related TPs
TpNbxxx, ///< 91 .
EndNbTestPoints, ///< 92 End of TP range for NB
StartSbTestPoints = 0xB0, ///< B0 Entry used for range testing for @b SouthBridge related TPs
TpSbxxx, ///< B1 .
EndSbTestPoints, ///< B2 End of TP range for SB
// Interface test points
TpIfAmdInitResetEntry = 0xC0, ///< C0 .. Entry to AmdInitReset
TpIfAmdInitResetExit, ///< C1 .. Exiting from AmdInitReset
TpIfAmdInitRecoveryEntry, ///< C2 .. Entry to AmdInitRecovery
TpIfAmdInitRecoveryExit, ///< C3 .. Exiting from AmdInitRecovery
TpIfAmdInitEarlyEntry, ///< C4 .. Entry to AmdInitEarly
TpIfAmdInitEarlyExit, ///< C5 .. Exiting from AmdInitEarly
TpIfAmdInitPostEntry, ///< C6 .. Entry to AmdInitPost
TpIfAmdInitPostExit, ///< C7 .. Exiting from AmdInitPost
TpIfAmdInitEnvEntry, ///< C8 .. Entry to AmdInitEnv
TpIfAmdInitEnvExit, ///< C9 .. Exiting from AmdInitEnv
TpIfAmdInitMidEntry, ///< CA .. Entry to AmdInitMid
TpIfAmdInitMidExit, ///< CB .. Exiting from AmdInitMid
TpIfAmdInitLateEntry, ///< CC .. Entry to AmdInitLate
TpIfAmdInitLateExit, ///< CD .. Exiting from AmdInitLate
TpIfAmdS3SaveEntry, ///< CE .. Entry to AmdS3Save
TpIfAmdS3SaveExit, ///< CF .. Exiting from AmdS3Save
TpIfAmdInitResumeEntry, ///< D0 .. Entry to AmdInitResume
TpIfAmdInitResumeExit, ///< D1 .. Exiting from AmdInitResume
TpIfAmdS3LateRestoreEntry, ///< D2 .. Entry to AmdS3LateRestore
TpIfAmdS3LateRestoreExit, ///< D3 .. Exiting from AmdS3LateRestore
TpIfAmdLateRunApTaskEntry, ///< D4 .. Entry to AmdS3LateRestore
TpIfAmdLateRunApTaskExit, ///< D5 .. Exiting from AmdS3LateRestore
TpIfAmdReadEventLogEntry, ///< D6 .. Entry to AmdReadEventLog
TpIfAmdReadEventLogExit, ///< D7 .. Exiting from AmdReadEventLog
TpIfAmdGetApicIdEntry, ///< D8 .. Entry to AmdGetApicId
TpIfAmdGetApicIdExit, ///< D9 .. Exiting from AmdGetApicId
TpIfAmdGetPciAddressEntry, ///< DA .. Entry to AmdGetPciAddress
TpIfAmdGetPciAddressExit, ///< DB .. Exiting from AmdGetPciAddress
TpIfAmdIdentifyCoreEntry, ///< DC .. Entry to AmdIdentifyCore
TpIfAmdIdentifyCoreExit, ///< DD .. Exiting from AmdIdentifyCore
TpIfBeforeRunApFromIds, ///< DE .. After IDS calls out to run code on an AP
TpIfAfterRunApFromIds, ///< DF .. After IDS calls out to run code on an AP
TpIfBeforeGetIdsData, ///< E0 .. Before IDS calls out to get IDS data
TpIfAfterGetIdsData, ///< E1 .. After IDS calls out to get IDS data
TpIfBeforeAllocateHeapBuffer, ///< E2 .. Before the heap manager calls out to allocate a buffer
TpIfAfterAllocateHeapBuffer, ///< E3 .. After the heap manager calls out to allocate a buffer
TpIfBeforeDeallocateHeapBuffer, ///< E4 .. Before the heap manager calls out to deallocate a buffer
TpIfAfterDeallocateHeapBuffer, ///< E5 .. After the heap manager calls out to deallocate a buffer
TpIfBeforeLocateHeapBuffer, ///< E6 .. Before the heap manager calls out to locate a buffer
TpIfAfterLocateHeapBuffer, ///< E7 .. After the heap manager calls out to locate a buffer
TpIfBeforeRunApFromAllAps, ///< E8 .. Before the BSP calls out to run code on an AP
TpIfAfterRunApFromAllAps, ///< E9 .. After the BSP calls out to run code on an AP
TpIfBeforeRunApFromAllCore0s, ///< EA .. Before the BSP calls out to run code on an AP
TpIfAfterRunApFromAllCore0s, ///< EB .. After the BSP calls out to run code on an AP
TpIfBeforeAllocateS3SaveBuffer, ///< EC .. Before the S3 save code calls out to allocate a buffer
TpIfAfterAllocateS3SaveBuffer, ///< ED .. After the S3 save code calls out to allocate a buffer
TpIfBeforeAllocateMemoryS3SaveBuffer, ///< EE .. Before the memory S3 save code calls out to allocate a buffer
TpIfAfterAllocateMemoryS3SaveBuffer, ///< EF .. After the memory S3 save code calls out to allocate a buffer
TpIfBeforeLocateS3PciBuffer, ///< F0 .. Before the memory code calls out to locate a buffer
TpIfAfterLocateS3PciBuffer, ///< F1 .. After the memory code calls out to locate a buffer
TpIfBeforeLocateS3CPciBuffer, ///< F2 .. Before the memory code calls out to locate a buffer
TpIfAfterLocateS3CPciBuffer, ///< F3 .. After the memory code calls out to locate a buffer
TpIfBeforeLocateS3MsrBuffer, ///< F4 .. Before the memory code calls out to locate a buffer
TpIfAfterLocateS3MsrBuffer, ///< F5 .. After the memory code calls out to locate a buffer
TpIfBeforeLocateS3CMsrBuffer, ///< F6 .. Before the memory code calls out to locate a buffer
TpIfAfterLocateS3CMsrBuffer, ///< F7 .. After the memory code calls out to locate a buffer
TpPerfUnit, ///< F8 .. The Unit of performance measure.
EndAgesaTps = 0xFF, ///< Last defined AGESA TP
} AGESA_TP;
///Ids Feat description
typedef enum {
IDS_FEAT_UCODE_UPDATE = 0x0000, ///< Feat for Ucode Update
IDS_FEAT_TARGET_PSTATE, ///< Feat for Target Pstate
IDS_FEAT_POSTPSTATE, ///< Feat for Post Pstate
IDS_FEAT_ECC_CTRL, ///< Feat for Ecc Control
IDS_FEAT_ECC_SYMBOL_SIZE, ///< Feat for Ecc symbol size
IDS_FEAT_DCT_ALLMEMCLK, ///< Feat for all memory clock
IDS_FEAT_DCT_GANGMODE, ///< Feat for Dct gang mode
IDS_FEAT_DCT_BURSTLENGTH, ///< Feat for dct burst length
IDS_FEAT_DCT_POWERDOWN, ///< Feat for dct power down
IDS_FEAT_DCT_DLLSHUTDOWN, ///< Feat for dct dll shut down
IDS_FEAT_PROBE_FILTER, ///< Feat for probe filter
IDS_FEAT_HDTOUT, ///< Feat for hdt out
IDS_FEAT_HT_SETTING, ///< Feat for Ht setting
IDS_FEAT_GNB_PLATFORMCFG, ///< Feat for override GNB platform config
IDS_FEAT_CPB_CTRL, ///< Feat for Config the Core peformance boost feature
IDS_FEAT_HTC_CTRL, ///< Feat for Hardware Thermal Control
IDS_FEAT_MEMORY_MAPPING, ///< Feat for Memory Mapping
IDS_FEAT_POWER_POLICY, ///< Feat for Power Policy
IDS_FEAT_END = 0xFF ///< End of Common feat
} IDS_FEAT;
typedef IDS_STATUS IDS_COMMON_FUNC (
IN OUT VOID *DataPtr,
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN IDS_NV_ITEM *IdsNvPtr
);
typedef IDS_COMMON_FUNC *PIDS_COMMON_FUNC;
/// Data Structure of IDS Feature block
typedef struct _IDS_FEAT_STRUCT {
IDS_FEAT IdsFeat; ///< Ids Feat ID
BOOLEAN IsBsp; ///< swith for Bsp check
AGESA_IDS_OPTION IdsOption; ///< IDS option
UINT64 CpuFamily; ///<
PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function
} IDS_FEAT_STRUCT;
/// Data Structure of IDS option
typedef struct _IDS_OPTION_STRUCT {
AGESA_IDS_OPTION idsoption; ///< IDS option
PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function
} IDS_OPTION_STRUCT;
/// Data Structure of IDS option table
typedef struct _IDS_OPTION_STRUCT_TBL {
UINT8 version; ///<Version of IDS option table
UINT16 size; ///<Size of IDS option table
CONST IDS_OPTION_STRUCT *pIdsOptionStruct; ///<pointer to array of structure
} IDS_OPTION_STRUCT_TBL;
#endif // _IDS_H_

123
src/vendorcode/amd/agesa/f14/Include/IdsHt.h
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@@ -1,123 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD IDS HyperTransport Definitions
*
* Contains AMD AGESA Integrated Debug HT related items.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: IDS
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _IDS_HT_H_
#define _IDS_HT_H_
// Frequency equates for call backs which take an actual frequency setting
#define HT_FREQUENCY_200M 0
#define HT_FREQUENCY_400M 2
#define HT_FREQUENCY_600M 4
#define HT_FREQUENCY_800M 5
#define HT_FREQUENCY_1000M 6
#define HT_FREQUENCY_1200M 7
#define HT_FREQUENCY_1400M 8
#define HT_FREQUENCY_1600M 9
#define HT_FREQUENCY_1800M 10
#define HT_FREQUENCY_2000M 11
#define HT_FREQUENCY_2200M 12
#define HT_FREQUENCY_2400M 13
#define HT_FREQUENCY_2600M 14
#define HT_FREQUENCY_2800M 17
#define HT_FREQUENCY_3000M 18
#define HT_FREQUENCY_3200M 19
#define HT_FREQUENCY_3600M 20
/**
* HT IDS: HT Link Port Override params.
*
* Provide an absolute override of HT Link Port settings. No checking is done that
* the settings obey limits or capabilities, this responsibility rests with the user.
*
* Rules for values of structure items:
* - Socket
* - HT_LIST_TERMINAL == end of port override list, rest of item is not accessed
* - HT_LIST_MATCH_ANY == Match Any Socket
* - 0 .. 7 == The matching socket
* - Link
* - HT_LIST_MATCH_ANY == Match Any package link (that is not the internal links)
* - HT_LIST_MATCH_INTERNAL_LINK == Match the internal links
* - 0 .. 7 == The matching package link. 0 .. 3 are the ganged links or sublink 0's, 4 .. 7 are the sublink1's.
* - Frequency
* - HT_LIST_TERMINAL == Do not override the frequency, AUTO setting
* - HT_FREQUENCY_200M .. HT_FREQUENCY_3600M = The frequency value to use
* - Widthin
* - HT_LIST_TERMINAL == Do not override the width, AUTO setting
* - 2, 4, 8, 16, 32 == The width value to use
* - Widthout
* - HT_LIST_TERMINAL == Do not override the width, AUTO setting
* - 2, 4, 8, 16, 32 == The width value to use
*/
typedef struct {
// Match Fields
UINT8 Socket; ///< The Socket which this port is on.
UINT8 Link; ///< The port for this package link on that socket.
// Override fields
UINT8 Frequency; ///< Absolutely override the port's frequency.
UINT8 WidthIn; ///< Absolutely override the port's width.
UINT8 WidthOut; ///< Absolutely override the port's width.
} HTIDS_PORT_OVERRIDE;
/**
* A list of port overrides to search.
*/
typedef HTIDS_PORT_OVERRIDE *HTIDS_PORT_OVERRIDE_LIST;
VOID
HtIdsGetPortOverride (
IN BOOLEAN IsSourcePort,
IN OUT PORT_DESCRIPTOR *Port0,
IN OUT PORT_DESCRIPTOR *Port1,
IN OUT HTIDS_PORT_OVERRIDE_LIST *PortOverrideList,
IN STATE_DATA *State
);
typedef
VOID
F_HtIdsGetPortOverride (
IN BOOLEAN IsSourcePort,
IN OUT PORT_DESCRIPTOR *Port0,
IN OUT PORT_DESCRIPTOR *Port1,
IN OUT HTIDS_PORT_OVERRIDE_LIST *PortOverrideList,
IN STATE_DATA *State
);
typedef F_HtIdsGetPortOverride* PF_HtIdsGetPortOverride;
#endif // _IDS_HT_H

89
src/vendorcode/amd/agesa/f14/Include/OptionDmi.h
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@@ -1,89 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD DMI option API.
*
* Contains structures and values used to control the DMI option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_DMI_H_
#define _OPTION_DMI_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_DMI_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN OUT DMI_INFO **DmiPtr
);
typedef AGESA_STATUS OPTION_DMI_RELEASE_BUFFER (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
#define DMI_STRUCT_VERSION 0x01
/// DMI option configuration. Determine the item of structure when compiling.
typedef struct {
UINT16 OptDmiVersion; ///< Dmi version.
OPTION_DMI_FEATURE *DmiFeature; ///< Feature main routine, otherwise dummy.
OPTION_DMI_RELEASE_BUFFER *DmiReleaseBuffer; ///< Release buffer
UINT16 NumEntries; ///< Number of entry.
VOID *((*FamilyList)[]); ///< Family service.
} OPTION_DMI_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_DMI_H_

138
src/vendorcode/amd/agesa/f14/Include/OptionFamily12hEarlySample.h
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@@ -1,138 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Family 12h 'early sample' support
*
* This file defines the required structures for family 12h pre-production processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 37456 $ @e \$Date: 2010-09-04 04:17:05 +0800 (Sat, 04 Sep 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_FAMILY_12H_EARLY_SAMPLE_H_
#define _OPTION_FAMILY_12H_EARLY_SAMPLE_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/**
* Return the appropriate values of certain NB P-state related registers.
*
* @param[in,out] FCRxFE00_6000 The value of FCRxFE006000.
* @param[in,out] FCRxFE00_6002 The value of FCRxFE006002.
* @param[in,out] FCRxFE00_7006 The value of FCRxFE007006.
* @param[in,out] FCRxFE00_7009 The value of FCRxFE007009.
* @param[in] MainPll The main PLL frequency.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
*/
typedef VOID F_F12_ES_NB_PSTATE_INIT (
IN OUT VOID *FCRxFE00_6000,
IN OUT VOID *FCRxFE00_6002,
IN OUT VOID *FCRxFE00_7006,
IN OUT VOID *FCRxFE00_7009,
IN UINT32 MainPll,
IN AMD_CONFIG_PARAMS *StdHeader
);
/// Reference to a Method.
typedef F_F12_ES_NB_PSTATE_INIT *PF_F12_ES_NB_PSTATE_INIT;
/**
* Return the appropriate value of a certain NB P-state related register.
*
* @param[in,out] FCRxFE00_6000 The value of FCRxFE006000.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
*/
typedef VOID F_F12_ES_POWER_PLANE_INIT (
IN OUT VOID *FCRxFE00_6000,
IN AMD_CONFIG_PARAMS *StdHeader
);
/// Reference to a Method.
typedef F_F12_ES_POWER_PLANE_INIT *PF_F12_ES_POWER_PLANE_INIT;
/**
* Implements an early sample workaround required for C6
*
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
*/
typedef VOID F_F12_ES_C6_INIT (
IN AMD_CONFIG_PARAMS *StdHeader
);
/// Reference to a Method.
typedef F_F12_ES_C6_INIT *PF_F12_ES_C6_INIT;
/// Hook points in the core functionality necessary for
/// providing support for pre-production CPUs.
typedef struct {
PF_F12_ES_POWER_PLANE_INIT F12PowerPlaneInitHook; ///< Allows for override of a certain processor register value during power plane init
PF_F12_ES_NB_PSTATE_INIT F12NbPstateInitHook; ///< Allows for override of certain processor register values for proper NB P-state init
} F12_ES_CORE_SUPPORT;
/// Hook points in the C6 feature necessary for
/// providing support for pre-production CPUs.
typedef struct {
PF_F12_ES_C6_INIT F12InitializeC6; ///< Hook for erratum 453 workaround
} F12_ES_C6_SUPPORT;
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
#endif // _OPTION_FAMILY_12H_EARLY_SAMPLE_H_

170
src/vendorcode/amd/agesa/f14/Include/OptionFamily14hEarlySample.h
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@@ -1,170 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Family 14h 'early sample' support
*
* This file defines the required structures for family 14h pre-production processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 37018 $ @e \$Date: 2010-08-28 05:46:16 +0800 (Sat, 28 Aug 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_FAMILY_14H_EARLY_SAMPLE_H_
#define _OPTION_FAMILY_14H_EARLY_SAMPLE_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/**
* Return the correct early init table pointer.
*
* @param[in,out] Table The early init table pointer.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
*/
typedef VOID F_F14_ES_GET_EARLY_INIT_TABLE (
IN OUT CONST VOID **Table,
IN AMD_CONFIG_PARAMS *StdHeader
);
/// Reference to a Method.
typedef F_F14_ES_GET_EARLY_INIT_TABLE *PF_F14_ES_GET_EARLY_INIT_TABLE;
/**
* Return the appropriate values of certain NB P-state related registers.
*
* @param[in,out] FCRxFE00_6000 The value of FCRxFE006000.
* @param[in,out] FCRxFE00_6002 The value of FCRxFE006002.
* @param[in,out] FCRxFE00_7006 The value of FCRxFE007006.
* @param[in,out] FCRxFE00_7009 The value of FCRxFE007009.
* @param[in] MainPll The main PLL frequency.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
*/
typedef VOID F_F14_ES_NB_PSTATE_INIT (
IN OUT VOID *FCRxFE00_6000,
IN OUT VOID *FCRxFE00_6002,
IN OUT VOID *FCRxFE00_7006,
IN OUT VOID *FCRxFE00_7009,
IN UINT32 MainPll,
IN AMD_CONFIG_PARAMS *StdHeader
);
/// Reference to a Method.
typedef F_F14_ES_NB_PSTATE_INIT *PF_F14_ES_NB_PSTATE_INIT;
/**
* Return the appropriate value of a certain NB P-state related register.
*
* @param[in,out] FCRxFE00_6000 The value of FCRxFE006000.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
*/
typedef VOID F_F14_ES_POWER_PLANE_INIT (
IN OUT VOID *FCRxFE00_6000,
IN AMD_CONFIG_PARAMS *StdHeader
);
/// Reference to a Method.
typedef F_F14_ES_POWER_PLANE_INIT *PF_F14_ES_POWER_PLANE_INIT;
/**
* Returns whether or not the processor should enable the C6 feature.
*
* @param[in,out] IsEnabled Whether or not to enable C6
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
*/
typedef VOID F_F14_ES_IS_C6_SUPPORTED (
IN OUT BOOLEAN *IsEnabled,
IN AMD_CONFIG_PARAMS *StdHeader
);
/// Reference to a Method.
typedef F_F14_ES_IS_C6_SUPPORTED *PF_F14_ES_IS_C6_SUPPORTED;
/**
* Implements an early sample workaround required for C6
*
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
*/
typedef VOID F_F14_ES_C6_INIT (
IN AMD_CONFIG_PARAMS *StdHeader
);
/// Reference to a Method.
typedef F_F14_ES_C6_INIT *PF_F14_ES_C6_INIT;
/// Hook points in the core functionality necessary for
/// providing support for pre-production CPUs.
typedef struct {
PF_F14_ES_GET_EARLY_INIT_TABLE F14GetEarlyInitTableHook; ///< Early init table pointer override
PF_F14_ES_POWER_PLANE_INIT F14PowerPlaneInitHook; ///< Allows for override of a certain processor register value during power plane init
PF_F14_ES_NB_PSTATE_INIT F14NbPstateInitHook; ///< Allows for override of certain processor register values for proper NB P-state init
} F14_ES_CORE_SUPPORT;
/// Hook points in the C6 feature necessary for
/// providing support for pre-production CPUs.
typedef struct {
PF_F14_ES_IS_C6_SUPPORTED F14IsC6SupportedHook; ///< C6 enablement override
PF_F14_ES_C6_INIT F14InitializeC6; ///< Hook for erratum 453 workaround
} F14_ES_C6_SUPPORT;
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
#endif // _OPTION_FAMILY_14H_EARLY_SAMPLE_H_

81
src/vendorcode/amd/agesa/f14/Include/OptionGfxRecovery.h
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@@ -1,81 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD GFX Recovery option API.
*
* Contains structures and values used to control the GfxRecovery option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_GFX_RECOVERY_H_
#define _OPTION_GFX_RECOVERY_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_GFX_RECOVERY_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
#define GFX_RECOVERY_STRUCT_VERSION 0x01
/// The Option Configuration of GFX Recovery
typedef struct {
UINT16 OptGfxRecoveryVersion; ///< The version number of GFX Recovery
OPTION_GFX_RECOVERY_FEATURE *GfxRecoveryFeature; ///< The Option Feature of GFX Recovery
} OPTION_GFX_RECOVERY_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_GFX_RECOVERY_H_

97
src/vendorcode/amd/agesa/f14/Include/OptionGnb.h
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@@ -1,97 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD ALIB option API.
*
* Contains structures and values used to control the ALIB option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_GNB_H_
#define _OPTION_GNB_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_GNB_FEATURE (
IN AMD_CONFIG_PARAMS *StdHeader
);
/// The Option Configuration of ALIB
typedef struct {
UINT64 Type; ///< Type
OPTION_GNB_FEATURE *GnbFeature; ///< The GNB Feature
} OPTION_GNB_CONFIGURATION;
/// The Build time options configuration
typedef struct {
BOOLEAN IgfxModeAsPcieEp; ///< Itegrated Gfx mode Pcie EP or Legacy
BOOLEAN LclkDeepSleepEn; ///< Default for LCLK deep sleep
BOOLEAN LclkDpmEn; ///< Default for LCLK DPM
BOOLEAN GmcPowerGateStutterOnly; ///< Force GMC power gate to stutter only
BOOLEAN SmuSclkClockGatingEnable;///< Control SMU SCLK gating
BOOLEAN PcieAspmBlackListEnable; ///< Control Pcie Aspm Black List
UINT32 LinkReceiverDetectionPooling; ///< Receiver pooling detection time in us.
UINT32 LinkL0Pooling; ///< Pooling for link to get to L0 in us
UINT32 LinkGpioResetAssertionTime; ///< Gpio reset assertion time in us
UINT32 LinkResetToTrainingTime; ///< Time duration between deassert GPIO reset and release training in us ///
UINT8 TrainingAlgorithm; ///< Training algorithm (see PCIE_TRAINING_ALGORITHM)
} GNB_BUILD_OPTIONS;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_GNB_H_

354
src/vendorcode/amd/agesa/f14/Include/OptionMemory.h
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@@ -1,354 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Memory option API.
*
* Contains structures and values used to control the Memory option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_MEMORY_H_
#define _OPTION_MEMORY_H_
/* Memory Includes */
#include "mm.h"
#include "mn.h"
#include "mt.h"
#include "ma.h"
#include "mp.h"
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
#define MAX_FF_TYPES 6 ///< Maximum number of DDR Form factors (UDIMMs, RDIMMMs, SODIMMS) supported
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/*
* STANDARD MEMORY FEATURE FUNCTION POINTER
*/
typedef BOOLEAN OPTION_MEM_FEATURE_NB (
IN OUT MEM_NB_BLOCK *NBPtr
);
typedef BOOLEAN MEM_TECH_FEAT (
IN OUT MEM_TECH_BLOCK *TechPtr
);
typedef UINT8 MEM_TABLE_FEAT (
IN OUT MEM_TABLE_ALIAS **MTPtr
);
#define MEM_FEAT_BLOCK_NB_STRUCT_VERSION 0x01
/**
* MEMORY FEATURE BLOCK - This structure serves as a vector table for standard
* memory feature implementation functions. It contains vectors for all of the
* features that are supported by the various Northbridge devices supported by
* AGESA.
*/
typedef struct _MEM_FEAT_BLOCK_NB {
UINT16 OptMemFeatVersion; ///< Version of memory feature block.
OPTION_MEM_FEATURE_NB *OnlineSpare; ///< Online spare support.
OPTION_MEM_FEATURE_NB *InterleaveBanks; ///< Bank (Chip select) interleaving support.
OPTION_MEM_FEATURE_NB *UndoInterleaveBanks; ///< Undo Bank (Chip Select) interleaving.
OPTION_MEM_FEATURE_NB *CheckInterleaveNodes; ///< Check for Node interleaving support.
OPTION_MEM_FEATURE_NB *InterleaveNodes; ///< Node interleaving support.
OPTION_MEM_FEATURE_NB *InterleaveChannels; ///< Channel interleaving support.
OPTION_MEM_FEATURE_NB *InterleaveRegion; ///< Interleave Region support.
OPTION_MEM_FEATURE_NB *CheckEcc; ///< Check for ECC support.
OPTION_MEM_FEATURE_NB *InitEcc; ///< ECC support.
OPTION_MEM_FEATURE_NB *Training; ///< Choose the type of training (Parallel, standard or hardcoded).
OPTION_MEM_FEATURE_NB *LvDdr3; ///< Low voltage DDR3 dimm support
OPTION_MEM_FEATURE_NB *OnDimmThermal; ///< On-Dimm thermal management
MEM_TECH_FEAT *DramInit; ///< Choose the type of Dram init (hardware based or software based).
OPTION_MEM_FEATURE_NB *ExcludeDIMM; ///< Exclude a dimm.
OPTION_MEM_FEATURE_NB *InitEarlySampleSupport; ///< Initialize early sample support.
OPTION_MEM_FEATURE_NB *InitCPG; ///< Continuous pattern generation.
OPTION_MEM_FEATURE_NB *InitHwRxEn; ///< Hardware Receiver Enable Training Initilization.
} MEM_FEAT_BLOCK_NB;
typedef AGESA_STATUS MEM_MAIN_FLOW_CONTROL (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
);
typedef BOOLEAN OPTION_MEM_FEATURE_MAIN (
IN MEM_MAIN_DATA_BLOCK *MMPtr
);
typedef BOOLEAN MEM_NB_CONSTRUCTOR (
IN OUT MEM_NB_BLOCK *NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
CONST IN MEM_FEAT_BLOCK_NB *FeatPtr,
IN MEM_SHARED_DATA *mmSharedPtr, ///< Pointer to Memory scratchpad
IN UINT8 NodeID
);
typedef BOOLEAN MEM_TECH_CONSTRUCTOR (
IN OUT MEM_TECH_BLOCK *TechPtr,
IN OUT MEM_NB_BLOCK *NBPtr
);
typedef VOID MEM_INITIALIZER (
IN OUT MEM_DATA_STRUCT *MemPtr
);
typedef AGESA_STATUS MEM_PLATFORM_CFG (
IN struct _MEM_DATA_STRUCT *MemData,
IN UINT8 SocketID,
IN CH_DEF_STRUCT *CurrentChannel
);
typedef BOOLEAN MEM_IDENDIMM_CONSTRUCTOR (
IN OUT MEM_NB_BLOCK *NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
);
typedef VOID MEM_TECH_TRAINING_FEAT (
IN OUT MEM_TECH_BLOCK *TechPtr,
IN UINT8 Pass
);
typedef BOOLEAN MEM_RESUME_CONSTRUCTOR (
IN OUT VOID *S3NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
);
typedef AGESA_STATUS MEM_PLAT_SPEC_CFG (
IN struct _MEM_DATA_STRUCT *MemData,
IN OUT CH_DEF_STRUCT *CurrentChannel,
IN OUT MEM_PS_BLOCK *PsPtr
);
typedef AGESA_STATUS MEM_FLOW_CFG (
IN OUT MEM_MAIN_DATA_BLOCK *MemData
);
#define MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION 0x01
/**
* MAIN FEATURE BLOCK - This structure serves as vector table for memory features
* that shared between all northbridge devices.
*/
typedef struct _MEM_FEAT_BLOCK_MAIN {
UINT16 OptMemFeatVersion; ///< Version of main feature block.
OPTION_MEM_FEATURE_MAIN *Training; ///< Training features.
OPTION_MEM_FEATURE_MAIN *ExcludeDIMM; ///< Exclude a dimm.
OPTION_MEM_FEATURE_MAIN *OnlineSpare; ///< On-line spare.
OPTION_MEM_FEATURE_MAIN *InterleaveNodes; ///< Node interleave.
OPTION_MEM_FEATURE_MAIN *InitEcc; ///< Initialize ECC on all nodes if they all support it.
OPTION_MEM_FEATURE_MAIN *MemClr; ///< Memory Clear.
OPTION_MEM_FEATURE_MAIN *MemDmi; ///< Memory DMI Support.
OPTION_MEM_FEATURE_MAIN *LvDDR3; ///< Low voltage DDR3 support.
OPTION_MEM_FEATURE_MAIN *UmaAllocation; ///< Uma Allocation.
OPTION_MEM_FEATURE_MAIN *MemSave; ///< Memory Context Save
OPTION_MEM_FEATURE_MAIN *MemRestore; ///< Memory Context Restore
} MEM_FEAT_BLOCK_MAIN;
#define MEM_NB_SUPPORT_STRUCT_VERSION 0x01
#define MEM_TECH_FEAT_BLOCK_STRUCT_VERSION 0x01
#define MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION 0x01
#define MEM_TECH_LRDIMM_STRUCT_VERSION 0x01
/**
* MEMORY TECHNOLOGY FEATURE BLOCK - This structure serves as a vector table for standard
* memory feature implementation functions. It contains vectors for all of the
* features that are supported by the various Technology features supported by
* AGESA.
*/
typedef struct _MEM_TECH_FEAT_BLOCK {
UINT16 OptMemTechFeatVersion; ///< Version of memory Tech feature block.
MEM_TECH_FEAT *EnterHardwareTraining; ///<Enter HW WL Training
MEM_TECH_FEAT *SwWLTraining; ///<SW Write Levelization training
MEM_TECH_FEAT *HwBasedWLTrainingPart1; ///<HW based write levelization Training Part 1
MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart1; ///<HW based DQS receiver Enabled Training Part 1
MEM_TECH_FEAT *HwBasedWLTrainingPart2; ///<HW based write levelization Training Part 2
MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart2; ///<HW based DQS receiver Enabled Training Part 2
MEM_TECH_FEAT *TrainExitHwTrn; ///<Exit HW WL Training
MEM_TECH_FEAT *NonOptimizedSWDQSRecEnTrainingPart1; ///< Non-Optimized Software based receiver Enable Training part 1
MEM_TECH_FEAT *OptimizedSwDqsRecEnTrainingPart1; ///< Optimized Software based receiver Enable Training part 1
MEM_TECH_FEAT *NonOptimizedSRdWrPosTraining; ///< Non-Optimized Rd Wr Position training
MEM_TECH_FEAT *OptimizedSRdWrPosTraining; ///< Optimized Rd Wr Position training
MEM_TECH_FEAT *MaxRdLatencyTraining; ///< MaxReadLatency Training
} MEM_TECH_FEAT_BLOCK;
/**
* MEMORY TECHNOLOGY LRDIMM BLOCK - This structure serves as a vector table for standard
* memory feature implementation functions. It contains vectors for all of the
* features that are supported by the various LRDIMM features supported by
* AGESA.
*/
typedef struct _MEM_TECH_LRDIMM {
UINT16 OptMemTechLrdimmVersion; ///< Version of memory Tech feature block.
MEM_TECH_FEAT *MemTInitializeLrdimm; ///< LRDIMM initialization
} MEM_TECH_LRDIMM;
/**
* MEMORY NORTHBRIDGE SUPPORT STRUCT - This structure groups the Northbridge dependent
* options together in a list to provide a single access point for all code to use
* and to ensure that everything corresponding to the same NB type is grouped together.
*
* The Technology Block pointers are not included in this structure because DRAM technology
* needs to be decoupled from the northbridge type.
*
*/
typedef struct _MEM_NB_SUPPORT {
UINT16 MemNBSupportVersion; ///< Version of northbridge support.
MEM_NB_CONSTRUCTOR *MemConstructNBBlock; ///< NorthBridge block constructor.
MEM_INITIALIZER *MemNInitDefaults; ///< Default value initialization for MEM_DATA_STRUCT.
CONST MEM_FEAT_BLOCK_NB *MemFeatBlock; ///< Memory feature block.
MEM_RESUME_CONSTRUCTOR *MemS3ResumeConstructNBBlock; ///< S3 memory initialization northbridge block constructor.
MEM_IDENDIMM_CONSTRUCTOR *MemIdentifyDimmConstruct; ///< Constructor for address to dimm identification.
} MEM_NB_SUPPORT;
/*
* MEMORY Non-Training FEATURES - This structure serves as a vector table for standard
* memory non-training feature implementation functions. It contains vectors for all of the
* features that are supported by the various Technology devices supported by
* AGESA.
*/
/**
* MAIN TRAINING SEQUENCE LIST - This structure serves as vector table for memory features
* that shared between all northbridge devices.
*/
typedef struct _MEM_FEAT_TRAIN_SEQ {
UINT16 OptMemTrainingSequenceListVersion; ///< Version of main feature block.
OPTION_MEM_FEATURE_NB *TrainingSequence; ///< Training Sequence function.
OPTION_MEM_FEATURE_NB *TrainingSequenceEnabled; ///< Enable function.
CONST MEM_TECH_FEAT_BLOCK *MemTechFeatBlock; ///< Memory feature block.
} MEM_FEAT_TRAIN_SEQ;
/**
* PLATFORM SPECIFIC CONFIGURATION BLOCK - This structure groups various PSC table
* entries which are used by PSC engine
*/
typedef struct _MEM_PSC_TABLE_BLOCK {
PSC_TBL_ENTRY **TblEntryOfMaxFreq; ///< Table entry of MaxFreq.
PSC_TBL_ENTRY **TblEntryOfDramTerm; ///< Table entry of Dram Term.
PSC_TBL_ENTRY **TblEntryOfODTPattern; ///< Table entry of ODT Pattern.
PSC_TBL_ENTRY **TblEntryOfSAO; ///< Table entry of Slow access mode, AddrTmg and ODC..
PSC_TBL_ENTRY **TblEntryOfMR0WR; ///< Table entry of MR0[WR].
PSC_TBL_ENTRY **TblEntryOfMR0CL; ///< Table entry of MR0[CL].
PSC_TBL_ENTRY **TblEntryOfRC2IBT; ///< Table entry of RC2 IBT.
PSC_TBL_ENTRY **TblEntryOfRC10OpSpeed; ///< Table entry of RC10[operating speed].
PSC_TBL_ENTRY **TblEntryOfLRIBT;///< Table entry of LRDIMM IBT
PSC_TBL_ENTRY **TblEntryOfLRNPR; ///< Table entry of LRDIMM F0RC13[NumPhysicalRanks].
PSC_TBL_ENTRY **TblEntryOfLRNLR; ///< Table entry of LRDIMM F0RC13[NumLogicalRanks].
PSC_TBL_ENTRY **TblEntryOfGen; ///< Table entry of CLKDis map and CKE, ODT as well as ChipSel tri-state map.
} MEM_PSC_TABLE_BLOCK;
typedef BOOLEAN MEM_PSC_FLOW (
IN OUT MEM_NB_BLOCK *NBPtr,
IN MEM_PSC_TABLE_BLOCK *EntryOfTables
);
/**
* PLATFORM SPECIFIC CONFIGURATION FLOW BLOCK - Pointers to the sub-engines of platform
* specific configuration.
*/
typedef struct _MEM_PSC_FLOW_BLOCK {
MEM_PSC_TABLE_BLOCK *EntryOfTables; ///<Entry of NB specific MEM_PSC_TABLE_BLOCK
MEM_PSC_FLOW *MaxFrequency; ///< Sub-engine which performs "Max Frequency" value extraction.
MEM_PSC_FLOW *DramTerm; ///< Sub-engine which performs "Dram Term" value extraction.
MEM_PSC_FLOW *ODTPattern; ///< Sub-engine which performs "ODT Pattern" value extraction.
MEM_PSC_FLOW *SAO; ///< Sub-engine which performs "Slow access mode, AddrTmg and ODC" value extraction.
MEM_PSC_FLOW *MR0WrCL; ///< Sub-engine which performs "MR0[WR] and MR0[CL]" value extraction.
MEM_PSC_FLOW *RC2IBT; ///< Sub-engine "RC2 IBT" value extraction.
MEM_PSC_FLOW *RC10OpSpeed; ///< Sub-engine "RC10[operating speed]" value extraction.
MEM_PSC_FLOW *LRIBT; ///< Sub-engine "LRDIMM IBT" value extraction.
MEM_PSC_FLOW *LRNPR; ///< Sub-engine "LRDIMM F0RC13[NumPhysicalRanks]" value extraction.
MEM_PSC_FLOW *LRNLR; ///< Sub-engine "LRDIMM F0RC13[NumLogicalRanks]" value extraction.
} MEM_PSC_FLOW_BLOCK;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
/* Feature Default Return */
BOOLEAN MemFDefRet (
IN OUT MEM_NB_BLOCK *NBPtr
);
BOOLEAN MemMDefRet (
IN MEM_MAIN_DATA_BLOCK *MMPtr
);
BOOLEAN MemMDefRetFalse (
IN MEM_MAIN_DATA_BLOCK *MMPtr
);
/* Table Feature Default Return */
UINT8 MemFTableDefRet (
IN OUT MEM_TABLE_ALIAS **MTPtr
);
BOOLEAN MemNIdentifyDimmConstructorRetDef (
IN OUT MEM_NB_BLOCK *NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
);
/* S3 Feature Default Return */
BOOLEAN MemFS3DefConstructorRet (
IN OUT VOID *S3NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
);
BOOLEAN
MemProcessConditionalOverrides (
IN PSO_TABLE *PlatformMemoryConfiguration,
IN OUT MEM_NB_BLOCK *NBPtr,
IN UINT8 PsoAction,
IN UINT8 Dimm
);
#endif // _OPTION_MEMORY_H_

169
src/vendorcode/amd/agesa/f14/Include/OptionMultiSocket.h
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@@ -1,169 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Multi-socket option API.
*
* Contains structures and values used to control the multi-socket option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_MULTISOCKET_H_
#define _OPTION_MULTISOCKET_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/**
* This function loops through all possible socket locations, gathering the number
* of power management steps each populated socket requires, and returns the
* highest number.
*
* @param[out] NumSystemSteps Maximum number of system steps required
* @param[in] StdHeader Config handle for library and services
*
*/
typedef VOID OPTION_MULTISOCKET_PM_STEPS (
OUT UINT8 *NumSystemSteps,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function loops through all possible socket locations, starting core 0 of
* each populated socket to perform the passed in AP_TASK. After starting all
* other core 0s, the BSC will perform the AP_TASK as well. This must be run by
* the system BSC only.
*
* @param[in] TaskPtr Function descriptor
* @param[in] StdHeader Config handle for library and services
* @param[in] ConfigParams AMD entry point's CPU parameter structure
*
*/
typedef VOID OPTION_MULTISOCKET_PM_CORE0_TASK (
IN VOID *TaskPtr,
IN AMD_CONFIG_PARAMS *StdHeader,
IN VOID *ConfigParams
);
/**
* This function loops through all possible socket locations, comparing the
* maximum NB frequencies to determine the slowest. This function also
* determines if all coherent NB frequencies are equivalent.
*
* @param[in] NbPstate NB P-state number to check (0 = fastest)
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[out] SystemNbCofNumerator NB frequency numerator for the system in MHz
* @param[out] SystemNbCofDenominator NB frequency denominator for the system
* @param[out] SystemNbCofsMatch Whether or not all NB frequencies are equivalent
* @param[out] NbPstateIsEnabledOnAllCPUs Whether or not NbPstate is valid on all CPUs
* @param[in] StdHeader Config handle for library and services
*
* @retval TRUE At least one processor has NbPstate enabled.
* @retval FALSE NbPstate is disabled on all CPUs
*/
typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF (
IN UINT32 NbPstate,
IN PLATFORM_CONFIGURATION *PlatformConfig,
OUT UINT32 *SystemNbCofNumerator,
OUT UINT32 *SystemNbCofDenominator,
OUT BOOLEAN *SystemNbCofsMatch,
OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function loops through all possible socket locations, checking whether
* any populated sockets require NB COF VID programming.
*
* @param[in] StdHeader Config handle for library and services
*
*/
typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF_UPDATE (
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function loops through all possible socket locations, collecting any
* power management initialization errors that may have occurred. These errors
* are transferred from the core 0s of the socket in which the errors occurred
* to the BSC's heap. The BSC's heap is then searched for the most severe error
* that occurred, and returns it. This function must be called by the BSC only.
*
* @param[in] StdHeader Config handle for library and services
*
*/
typedef AGESA_STATUS OPTION_MULTISOCKET_PM_GET_EVENTS (
IN AMD_CONFIG_PARAMS *StdHeader
);
#define MULTISOCKET_STRUCT_VERSION 0x01
/**
* Provide build configuration of cpu multi-socket or single socket support.
*
*/
typedef struct {
UINT16 OptMultiSocketVersion; ///< Table version
OPTION_MULTISOCKET_PM_STEPS *GetNumberOfSystemPmSteps; ///< Method: Get number of power mgt tasks
OPTION_MULTISOCKET_PM_CORE0_TASK *BscRunCodeOnAllSystemCore0s; ///< Method: Perform tasks on Core 0 of each processor
OPTION_MULTISOCKET_PM_NB_COF *GetSystemNbPstateSettings; ///< Method: Find the limiting Northbridge frequency in the system.
OPTION_MULTISOCKET_PM_NB_COF_UPDATE *GetSystemNbCofVidUpdate; ///< Method: Determine if any Northbridges in the system need to update their COF/VID.
OPTION_MULTISOCKET_PM_GET_EVENTS *BscRetrievePmEarlyInitErrors; ///< Method: Gathers error information from all Core 0s.
} OPTION_MULTISOCKET_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_MULTISOCKET_H_

115
src/vendorcode/amd/agesa/f14/Include/OptionPstate.h
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@@ -1,115 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD ACPI PState option API.
*
* Contains structures and values used to control the PStates option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_PSTATE_H_
#define _OPTION_PSTATE_H_
#include "cpuPstateTables.h"
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_SSDT_FEATURE (
IN AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN OUT VOID **AcpiPstatePtr
);
typedef UINT32 OPTION_ACPI_FEATURE (
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN PSTATE_LEVELING *PStateLevelingBuffer,
IN OUT VOID **AcpiPStatePtr,
IN UINT8 LocalApicId,
IN AMD_CONFIG_PARAMS *StdHeader
);
typedef AGESA_STATUS OPTION_PSTATE_GATHER (
IN AMD_CONFIG_PARAMS *StdHeader,
IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr
);
typedef AGESA_STATUS OPTION_PSTATE_LEVELING (
IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
#define PSTATE_STRUCT_VERSION 0x01
/// Indirection vectors for POST/PEI PState code
typedef struct {
UINT16 OptPstateVersion; ///< revision of this structure
OPTION_PSTATE_GATHER *PstateGather; ///< vector for data gathering routine
OPTION_PSTATE_LEVELING *PstateLeveling; ///< vector for leveling routine
} OPTION_PSTATE_POST_CONFIGURATION;
/// Indirection vectors for LATE/DXE PState code
typedef struct {
UINT16 OptPstateVersion; ///< revision of this structure
OPTION_SSDT_FEATURE *SsdtFeature; ///< vector for routine to generate SSDT
OPTION_ACPI_FEATURE *PstateFeature; ///< vector for routine to generate ACPI PState Objects
OPTION_ACPI_FEATURE *CstateFeature; ///< vector for routine to generate ACPI CState Objects
BOOLEAN CfgPstatePpc; ///< boolean for creating _PPC method
BOOLEAN CfgPstatePct; ///< boolean for creating _PCT method
BOOLEAN CfgPstatePsd; ///< boolean for creating _PSD method
BOOLEAN CfgPstatePss; ///< boolean for creating _PSS method
BOOLEAN CfgPstateXpss; ///< boolean for creating _XPSS method
} OPTION_PSTATE_LATE_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_PSTATE_H_

96
src/vendorcode/amd/agesa/f14/Include/OptionSlit.h
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@@ -1,96 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD SLIT option API.
*
* Contains structures and values used to control the SLIT option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_SLIT_H_
#define _OPTION_SLIT_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/**
* Create the ACPI System Locality Distance Information Table.
*
*/
typedef AGESA_STATUS OPTION_SLIT_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN OUT VOID **SlitPtr
);
/**
* Clean up DRAM used during SLIT creation.
*
*/
typedef AGESA_STATUS OPTION_SLIT_RELEASE_BUFFER (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
#define SLIT_STRUCT_VERSION 0x01
/// The Option Configuration of SLIT
typedef struct {
UINT16 OptSlitVersion; ///< The version number of SLIT
OPTION_SLIT_FEATURE *SlitFeature; ///< The Option Feature of SLIT
OPTION_SLIT_RELEASE_BUFFER *SlitReleaseBuffer; ///< Release buffer
} OPTION_SLIT_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_SLIT_H_

82
src/vendorcode/amd/agesa/f14/Include/OptionSrat.h
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@@ -1,82 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD SRAT option API.
*
* Contains structures and values used to control the SRAT option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_SRAT_H_
#define _OPTION_SRAT_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_SRAT_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN OUT VOID **SratPtr
);
#define SRAT_STRUCT_VERSION 0x01
/// The Option Configuration of SRAT
typedef struct {
UINT16 OptSratVersion; ///< The version number of SRAT
OPTION_SRAT_FEATURE *SratFeature; ///< The Option Feature of SRAT
} OPTION_SRAT_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_SRAT_H_

83
src/vendorcode/amd/agesa/f14/Include/OptionWhea.h
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@@ -1,83 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD WHEA option API.
*
* Contains structures and values used to control the WHEA option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_WHEA_H_
#define _OPTION_WHEA_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_WHEA_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN OUT VOID **WheaMcePtr,
IN OUT VOID **WheaCmcPtr
);
#define WHEA_STRUCT_VERSION 0x01
/// The Option Configuration of WHEA
typedef struct {
UINT16 OptWheaVersion; ///< The version number of WHEA
OPTION_WHEA_FEATURE *WheaFeature; ///< The Option Feature of WHEA
} OPTION_WHEA_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_WHEA_H_

71
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@@ -1,71 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AGESA options structures
*
* Contains options control structures for the AGESA build options
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTIONS_H_
#define _OPTIONS_H_
/**
* Provide topology limits for loops and runtime, based on supported families.
*/
typedef struct {
UINT32 PlatformNumberOfSockets; ///< The limit to the number of processors based on
///< supported families and other build options.
UINT32 PlatformNumberOfModules; ///< The limit to the number of modules in a processor, based
///< on supported families.
} OPTIONS_CONFIG_TOPOLOGY;
/**
* Dispatch Table.
*
* The push high dispatcher uses this table to find what entries are currently in the build image.
*/
typedef struct {
UINT32 FunctionId; ///< The function id specified.
IMAGE_ENTRY EntryPoint; ///< The corresponding entry point to call.
} DISPATCH_TABLE;
#endif // _OPTIONS_H_

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src/vendorcode/amd/agesa/f14/Include/OptionsHt.h
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@@ -1,112 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD HyperTransport option API.
*
* Contains option pre-compile logic. This file is used by the options
* installer and internally by the HT code initializers.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_HT_H_
#define _OPTION_HT_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/**
* Provide HT build option results
*/
typedef struct {
CONST BOOLEAN IsUsingRecoveryHt; ///< Manual BUID Swap List processing should assume that HT Recovery was used.
CONST BOOLEAN IsSetHtCrcFlood; ///< Enable setting of HT CRC Flood.
///< Build-time only customizable - @BldCfgItem{BLDCFG_SET_HTCRC_SYNC_FLOOD}
CONST BOOLEAN IsUsingUnitIdClumping; ///< Enable automatically HT Spec compliant Unit Id Clumping.
///< Build-time only customizable - @BldCfgItem{BLDCFG_USE_UNIT_ID_CLUMPING}
CONST AMD_HT_INTERFACE *HtOptionPlatformDefaults; ///< A set of build time options for HT constructor.
CONST VOID *HtOptionInternalInterface; ///< Use this internal interface initializer.
CONST VOID *HtOptionInternalFeatures; ///< Use this internal feature set initializer.
CONST VOID *HtOptionFamilyNorthbridgeList; ///< Use this list of northbridge initializers.
CONST UINT8 *CONST *HtOptionBuiltinTopologies; ///< Use this list of built-in topologies.
} OPTION_HT_CONFIGURATION;
typedef AGESA_STATUS
F_OPTION_HT_INIT_RESET (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
);
typedef F_OPTION_HT_INIT_RESET *PF_OPTION_HT_INIT_RESET;
typedef AGESA_STATUS
F_OPTION_HT_RESET_CONSTRUCTOR (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
);
typedef F_OPTION_HT_RESET_CONSTRUCTOR *PF_OPTION_HT_RESET_CONSTRUCTOR;
/**
* Provide HT reset initialization build option results
*/
typedef struct {
PF_OPTION_HT_INIT_RESET HtInitReset; ///< Method: HT reset initialization.
PF_OPTION_HT_RESET_CONSTRUCTOR HtResetConstructor; ///< Method: HT reset initialization.
} OPTION_HT_INIT_RESET;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_HT_H_

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src/vendorcode/amd/agesa/f14/Include/OptionsPage.h
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@@ -1,375 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Create outline and references for Build Configuration and Options Component mainpage documentation.
*
* Design guides, maintenance guides, and general documentation, are
* collected using this file onto the documentation mainpage.
* This file contains doxygen comment blocks, only.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Documentation
* @e \$Revision: 35380 $ @e \$Date: 2010-07-22 00:37:18 +0800 (Thu, 22 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/**
* @page optionmain Build Configuration and Options Documentation
*
* Additional documentation for the Build Configuration and Options component consists of
*
* - Introduction and Overview to Build Options
* - @subpage platforminstall "Platform Build Options"
* - @subpage bldcfg "Build Configuration Item Cross Reference"
* - @subpage examplecustomizations "Customization Examples"
* - Maintenance Guides:
* - For debug of the Options system, use compiler options
* @n <tt> /P /EP /C /FAs </tt> @n
* PreProcessor output is produced in an .i file in the directory where the project
* file is located.
* - Design Guides:
* - add here >>>
*
*/
/**
* @page platforminstall Platform Build Options.
*
* Build options are boolean constants. The purpose of build options is to remove code
* from the build to reduce the overall code size present in the ROM image. Unless
* otherwise specified, the default action is to include all options. If a build option is
* not specifically listed as disabled, then it is included into the build.
*
* The documented build options are imported from a user controlled file for
* processing. The build options for all platform solutions are listed below:
*
* @anchor BLDOPT_REMOVE_UDIMMS_SUPPORT
* @li @e BLDOPT_REMOVE_UDIMMS_SUPPORT @n
* If unbuffered DIMMs are NOT expected to be required in the system, the code that
* handles unbuffered DIMMs can be removed from the build.
*
* @anchor BLDOPT_REMOVE_RDIMMS_SUPPORT
* @li @e BLDOPT_REMOVE_RDIMMS_SUPPORT @n
* If registered DIMMs are NOT expected to be required in the system, the code
* that handles registered DIMMs can be removed from the build.
*
* @anchor BLDOPT_REMOVE_LRDIMMS_SUPPORT
* @li @e BLDOPT_REMOVE_LRDIMMS_SUPPORT @n
* If Load Reduced DIMMs are NOT expected to be required in the system, the code
* that handles Load Reduced DIMMs can be removed from the build.
*
* @note The above three options operate independently from each other; however, at
* least one of the unbuffered , registered or load reduced DIMM options must be present in the build.
*
* @anchor BLDOPT_REMOVE_ECC_SUPPORT
* @li @e BLDOPT_REMOVE_ECC_SUPPORT @n
* Use this option to remove the code for Error Checking & Correction.
*
* @anchor BLDOPT_REMOVE_BANK_INTERLEAVE
* @li @e BLDOPT_REMOVE_BANK_INTERLEAVE @n
* Interleaving is a mechanism to do performance fine tuning. This option
* interleaves memory between banks on a DIMM.
*
* @anchor BLDOPT_REMOVE_DCT_INTERLEAVE
* @li @e BLDOPT_REMOVE_DCT_INTERLEAVE @n
* Interleaving is a mechanism to do performance fine tuning. This option
* interleaves memory from two DRAM controllers.
*
* @anchor BLDOPT_REMOVE_NODE_INTERLEAVE
* @li @e BLDOPT_REMOVE_NODE_INTERLEAVE @n
* Interleaving is a mechanism to do performance fine tuning. This option
* interleaves memory from two HyperTransport nodes.
*
* @anchor BLDOPT_REMOVE_PARALLEL_TRAINING
* @li @e BLDOPT_REMOVE_PARALLEL_TRAINING @n
* For multi-socket systems, training memory in parallel can reduce the time
* needed to boot.
*
* @anchor BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
* @li @e BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT @n
* Online Spare support is removed by this option.
*
* @anchor BLDOPT_REMOVE_MULTISOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_MULTISOCKET_SUPPORT @n
* Many systems use only a single socket and may benefit in code space to remove
* this code. However, certain processors have multiple HyperTransport nodes
* within a single socket. For these processors, the multi-node support is
* required and this option has no effect.
*
* @anchor BLDOPT_REMOVE_ACPI_PSTATES
* @li @e BLDOPT_REMOVE_ACPI_PSTATES @n
* This option removes the code that generates the ACPI tables used in power
* management.
*
* @anchor BLDOPT_REMOVE_SRAT
* @li @e BLDOPT_REMOVE_SRAT @n
* This option removes the code that generates the SRAT tables used in performance
* tuning.
*
* @anchor BLDOPT_REMOVE_SLIT
* @li @e BLDOPT_REMOVE_SLIT @n
* This option removes the code that generates the SLIT tables used in performance
* tuning.
*
* @anchor BLDOPT_REMOVE_WHEA
* @li @e BLDOPT_REMOVE_WHEA @n
* This option removes the code that generates the WHEA tables used in error
* handling and reporting.
*
* @anchor BLDOPT_REMOVE_DMI
* @li @e BLDOPT_REMOVE_DMI @n
* This option removes the code that generates the DMI tables used in system
* management.
*
* @anchor BLDOPT_REMOVE_DQS_TRAINING
* @li @e BLDOPT_REMOVE_DQS_TRAINING @n
* This option removes the code used in memory performance tuning.
*
* @anchor BLDOPT_REMOVE_EARLY_SAMPLES
* @li @e BLDOPT_REMOVE_EARLY_SAMPLES @n
* Special support for Early Samples is included. Default setting is FALSE.
*
* @anchor BLDOPT_REMOVE_HT_ASSIST
* @li @e BLDOPT_REMOVE_HT_ASSIST @n
* This option removes the code which implements the HT Assist feature.
*
* @anchor BLDOPT_REMOVE_ATM_MODE
* @li @e BLDOPT_REMOVE_ATM_MODE @n
* This option removes the code which implements the ATM feature.
*
* @anchor BLDOPT_REMOVE_MSG_BASED_C1E
* @li @e BLDOPT_REMOVE_MSG_BASED_C1E @n
* This option removes the code which implements the Message Based C1e feature.
*
* @anchor BLDOPT_REMOVE_C6_STATE
* @li @e BLDOPT_REMOVE_C6_STATE @n
* This option removes the code which implements the C6 C-state feature.
*
* @anchor BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
* @li @e BLDOPT_REMOVE_MEM_RESTORE_SUPPORT @n
* This option removes the memory context restore feature.
*
* @anchor BLDOPT_REMOVE_FAMILY_10_SUPPORT
* @li @e BLDOPT_REMOVE_FAMILY_10_SUPPORT @n
* If the package contains support for family 10h processors, remove that support.
*
* @anchor BLDOPT_REMOVE_FAMILY_12_SUPPORT
* @li @e BLDOPT_REMOVE_FAMILY_12_SUPPORT @n
* If the package contains support for family 10h processors, remove that support.
*
* @anchor BLDOPT_REMOVE_FAMILY_14_SUPPORT
* @li @e BLDOPT_REMOVE_FAMILY_14_SUPPORT @n
* If the package contains support for family 14h processors, remove that support.
*
* @anchor BLDOPT_REMOVE_FAMILY_15_SUPPORT
* @li @e BLDOPT_REMOVE_FAMILY_15_SUPPORT @n
* If the package contains support for family 15h processors, remove that support.
*
* @anchor BLDOPT_REMOVE_AM3_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_AM3_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for AM3 sockets.
*
* @anchor BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for ASB2 sockets.
*
* @anchor BLDOPT_REMOVE_C32_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_C32_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for C32 sockets.
*
* @anchor BLDOPT_REMOVE_FM1_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_FM1_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for FM1 sockets.
*
* @anchor BLDOPT_REMOVE_FP1_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_FP1_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for FP1 sockets.
*
* @anchor BLDOPT_REMOVE_FS1_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_FS1_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for FS1 sockets.
*
* @anchor BLDOPT_REMOVE_FT1_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_FT1_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for FT1 sockets.
*
* @anchor BLDOPT_REMOVE_G34_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_G34_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for G34 sockets.
*
* @anchor BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for S1G3 sockets.
*
* @anchor BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for S1G4 sockets.
*/
/**
* @page examplecustomizations Customization Examples
*
* The Addendum \<plat\>Options.c file for each platform contains the minimum required
* customizations for that platform. That is, it contains settings which would be needed
* to boot a SimNow! bsd for that platform.
* However, each individual product based on that platform will have customizations necessary for
* that hardware. Since the actual customizations needed vary so much, they are not included in
* the \<plat\>Options.c. This section provides examples of useful customizations that you can use or
* modify to suit your needs.
*
* @par
*
* Source for the examples shown can be found at Addendum\\Examples. @n
*
* - @ref DeemphasisExamples "Deemphasis List Examples"
* - @ref FrequencyLimitExamples "Frequency Limit Examples"
* - @ref PerfPerWattHt "A performance-per-watt optimization Example"
*
* @anchor DeemphasisExamples
* @par Deemphasis List Examples
*
* These examples customize PLATFORM_CONFIGURATION.PlatformDeemphasisList.
* Source for the deemphasis list examples can be found in DeemphasisExamples.c. @n
* @dontinclude DeemphasisExamples.c
* <ul>
* <li>
* The following deemphasis list provides an example for a 2P MCM Max Performance configuration.
* High Speed HT frequencies are supported. There is only one non-coherent chain. Note the technique of
* putting specified link matches before all uses of match any. It often works well to specify the non-coherent links
* and use match any for the coherent links.
* @skip DinarDeemphasisList
* @until {
* The non-coherent chain can run up to 2600 MHz. The chain is located on Socket 0, package Link 2.
* @until {
* @line }
* @line {
* @line }
* The coherent links can run up to 3200 MHz.
* @until HT_FREQUENCY_MAX
* @line }
* end of list:
* @until }
* Make this list the build time customized deemphasis list.
* @line define
*
* </li><li>
*
* The following deemphasis list provides an example for a 4P MCM Max Performance configuration.
* This system has a backplane with connectors for CPU cards and an IO board. So trace lengths are long.
* There can be one to four IO Chains, depending on the IO board.
* @skipline DoubloonDeemphasisList
* @until DoubloonDeemphasisList
*
* </li><li>
*
* The following deemphasis list further illustrates complex coherent system deemphasis. This is the same
* Dinar system as in an earlier example, but this time all the coherent links are explicitly customized (as
* might be needed if each link has unique characterization). For this example, we skip the non-coherent chains.
* (A real system would have to include them, see example above.)
* @skip DinarPerLinkDeemphasisList
* @until {
* Provide deemphasis settings for the 16 bit, ganged, links, Socket 0 links 0, 1 and Socket 1 links 1 and 2.
* Provide entries to customize all HT3 frequencies at which the links may run. This example covers all HT3 speeds.
* @until {
* @until DcvLevelMinus6
* @until DcvLevelMinus6
* @until DcvLevelMinus6
* @until DcvLevelMinus6
* Link 3 on both sockets connects different internal die: sublink 0 connects the internal node zeroes, and
* sublink 1 connects the internal node ones. So the link is unganged and both sublinks must be specifically
* customized.
* @until {
* @until DcvLevelMinus6
* @until DcvLevelMinus6
* @until DcvLevelMinus6
* @until DcvLevelMinus6
* end of list:
* @until define
*
* </ul>
*
* @anchor FrequencyLimitExamples
* @par Frequency Limit Examples
*
* These examples customize AMD_HT_INTERFACE.CpuToCpuPcbLimitsList and AMD_HT_INTERFACE.IoPcbLimitsList.
* Source for the frequency limit examples can be found in FrequencyLimitExamples.c. @n
* @dontinclude FrequencyLimitExamples.c
* <ul>
* <li>
* The following list provides an example for limiting all coherent links to non-extended frequencies,
* that is, to 2600 MHz or less.
* @skipline NonExtendedCpuToCpuLimitList
* @until {
* Provide the limit customization. Match links from any socket, any package link, to any socket, any package link. Width is not limited.
* @until HT_FREQUENCY_LIMIT_2600M
* End of list:
* @until ;
* Customize the build to use this cpu to cpu frequency limit.
* @until NonExtendedCpuToCpuLimitList
* @n </li>
* <li>
* The following list provides an example for limiting all coherent links to HT 1 frequencies,
* that is, to 1000 MHz or less. This is sometimes useful for test and debug.
* @skipline Ht1CpuToCpuLimitList
* @until Ht1CpuToCpuLimitList
* @n </li>
* <li>
* The following list provides an example for limiting all non-coherent links to 2400 MHz or less.
* The chain is matched by host processor Socket and package Link. The depth can be used to select a particular device
* to device link on the chain. In this example, the chain consists of a single cave device and depth can be set to match any.
* @skipline No2600MhzIoLimitList
* @until No2600MhzIoLimitList
* @n </li>
* <li>
* The following list provides an example for limiting all non-coherent links to the minimum HT 3 frequency,
* that is, to 1200 MHz or less. This can be useful for test and debug.
* @skipline MinHt3IoLimitList
* @until MinHt3IoLimitList
* @n </li>
*
* </ul>
*
* @anchor PerfPerWattHt
* @par Performance-per-Watt Optimization Example
*
* This example customizes AMD_HT_INTERFACE.SkipRegangList.
* Source for the Performance-per-watt Optimization example can be found in PerfPerWatt.c. @n
* @dontinclude PerfPerWatt.c
* To implement a performance-per-watt optimization for MCM processors, use the skip regang structure shown. @n
* @skipline PerfPerWatt
* @until PerfPerWatt
*
*/

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/* $NoKeywords:$ */
/**
* @file
*
* AMD Platform Specific Memory Configuration
*
* Contains Definitions and Macros for control of AGESA Memory code on a per platform basis
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 35415 $ @e \$Date: 2010-07-22 06:10:32 +0800 (Thu, 22 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _PLATFORM_MEMORY_CONFIGURATION_H_
#define _PLATFORM_MEMORY_CONFIGURATION_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
#ifndef PSO_ENTRY
#define PSO_ENTRY UINT8
#endif
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* PLATFORM SPECIFIC MEMORY DEFINITIONS
*----------------------------------------------------------------------------------------
*/
///
/// Memory Speed and DIMM Population Masks
///
///< DDR Speed Masks
///< Specifies the DDR Speed on a memory channel
///
#define ANY_SPEED 0xFFFFFFFF
#define DDR400 ((UINT32) 1 << (DDR400_FREQUENCY / 66))
#define DDR533 ((UINT32) 1 << (DDR533_FREQUENCY / 66))
#define DDR667 ((UINT32) 1 << (DDR667_FREQUENCY / 66))
#define DDR800 ((UINT32) 1 << (DDR800_FREQUENCY / 66))
#define DDR1066 ((UINT32) 1 << (DDR1066_FREQUENCY / 66))
#define DDR1333 ((UINT32) 1 << (DDR1333_FREQUENCY / 66))
#define DDR1600 ((UINT32) 1 << (DDR1600_FREQUENCY / 66))
#define DDR1866 ((UINT32) 1 << (DDR1866_FREQUENCY / 66))
///
///< DIMM POPULATION MASKS
///< Specifies the DIMM Population on a channel (can be added together to specify configuration).
///< ex. SR_DIMM0 + SR_DIMM1 : Single Rank Dimm in slot 0 AND Slot 1
///< SR_DIMM0 + DR_DIMM0 + SR_DIMM1 +DR_DIMM1 : Single OR Dual rank in Slot 0 AND Single OR Dual rank in Slot 1
///
#define ANY_ 0xFF ///< Any dimm configuration the current channel
#define SR_DIMM0 0x0001 ///< Single rank dimm in slot 0 on the current channel
#define SR_DIMM1 0x0010 ///< Single rank dimm in slot 1 on the current channel
#define SR_DIMM2 0x0100 ///< Single rank dimm in slot 2 on the current channel
#define SR_DIMM3 0x1000 ///< Single rank dimm in slot 3 on the current channel
#define DR_DIMM0 0x0002 ///< Dual rank dimm in slot 0 on the current channel
#define DR_DIMM1 0x0020 ///< Dual rank dimm in slot 1 on the current channel
#define DR_DIMM2 0x0200 ///< Dual rank dimm in slot 2 on the current channel
#define DR_DIMM3 0x2000 ///< Dual rank dimm in slot 3 on the current channel
#define QR_DIMM0 0x0004 ///< Quad rank dimm in slot 0 on the current channel
#define QR_DIMM1 0x0040 ///< Quad rank dimm in slot 1 on the current channel
#define QR_DIMM2 0x0400 ///< Quad rank dimm in slot 2 on the current channel
#define QR_DIMM3 0x4000 ///< Quad rank dimm in slot 3 on the current channel
#define ANY_DIMM0 0x000F ///< Any Dimm combination in slot 0 on the current channel
#define ANY_DIMM1 0x00F0 ///< Any Dimm combination in slot 1 on the current channel
#define ANY_DIMM2 0x0F00 ///< Any Dimm combination in slot 2 on the current channel
#define ANY_DIMM3 0xF000 ///< Any Dimm combination in slot 3 on the current channel
///
///< Number of Dimms on the current channel
///< This is a mask used to indicate the number of dimms in a channel
///< They can be added to indicate multiple conditions (i.e 1 OR 2 Dimms)
///
#define ANY_NUM 0xFF ///< Any number of Dimms
#define NO_DIMM 0x00 ///< No Dimms present
#define ONE_DIMM 0x01 ///< One dimm Poulated on the current channel
#define TWO_DIMM 0x02 ///< Two dimms Poulated on the current channel
#define THREE_DIMM 0x04 ///< Three dimms Poulated on the current channel
#define FOUR_DIMM 0x08 ///< Four dimms Poulated on the current channel
/*----------------------------------------------------------------------------------------
*
* Platform Specific Override Definitions for Socket, Channel and Dimm
* This indicates where a platform override will be applied.
*
*----------------------------------------------------------------------------------------
*/
///
///< SOCKET MASKS
///< Indicates associated processor sockets to apply override settings
///
#define ANY_SOCKET 0xFF ///< Apply to all sockets
#define SOCKET0 0x01 ///< Apply to socket 0
#define SOCKET1 0x02 ///< Apply to socket 1
#define SOCKET2 0x04 ///< Apply to socket 2
#define SOCKET3 0x08 ///< Apply to socket 3
#define SOCKET4 0x10 ///< Apply to socket 4
#define SOCKET5 0x20 ///< Apply to socket 5
#define SOCKET6 0x40 ///< Apply to socket 6
#define SOCKET7 0x80 ///< Apply to socket 7
///
///< CHANNEL MASKS
///< Indicates Memory channels where override should be applied
///
#define ANY_CHANNEL 0xFF ///< Apply to all Memory channels
#define CHANNEL_A 0x01 ///< Apply to Channel A
#define CHANNEL_B 0x02 ///< Apply to Channel B
#define CHANNEL_C 0x04 ///< Apply to Channel C
#define CHANNEL_D 0x08 ///< Apply to Channel D
///
/// DIMM MASKS
/// Indicates Dimm Slots where override should be applied
///
#define ALL_DIMMS 0xFF ///< Apply to all dimm slots
#define DIMM0 0x01 ///< Apply to Dimm Slot 0
#define DIMM1 0x02 ///< Apply to Dimm Slot 1
#define DIMM2 0x04 ///< Apply to Dimm Slot 2
#define DIMM3 0x08 ///< Apply to Dimm Slot 3
///
/// REGISTER ACCESS MASKS
/// Not supported as an at this time
///
#define ACCESS_NB0 0x0
#define ACCESS_NB1 0x1
#define ACCESS_NB2 0x2
#define ACCESS_NB3 0x3
#define ACCESS_NB4 0x4
#define ACCESS_PHY 0x5
#define ACCESS_DCT_XT 0x6
/*----------------------------------------------------------------------------------------
*
* Platform Specific Overriding Table Definitions
*
*----------------------------------------------------------------------------------------
*/
#define PSO_END 0 ///< Table End
#define PSO_CKE_TRI 1 ///< CKE Tristate Map
#define PSO_ODT_TRI 2 ///< ODT Tristate Map
#define PSO_CS_TRI 3 ///< CS Tristate Map
#define PSO_MAX_DIMMS 4 ///< Max Dimms per channel
#define PSO_CLK_SPEED 5 ///< Clock Speed
#define PSO_DIMM_TYPE 6 ///< Dimm Type
#define PSO_MEMCLK_DIS 7 ///< MEMCLK Disable Map
#define PSO_MAX_CHNLS 8 ///< Max Channels per Socket
#define PSO_BUS_SPEED 9 ///< Max Memory Bus Speed
#define PSO_MAX_CHIPSELS 10 ///< Max Chipsel per Channel
#define PSO_MEM_TECH 11 ///< Channel Memory Type
#define PSO_WL_SEED 12 ///< DDR3 Write Levelization Seed delay
#define PSO_RXEN_SEED 13 ///< Hardwared based RxEn seed
#define PSO_NO_LRDIMM_CS67_ROUTING 14 ///< CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
/*----------------------------------
* CONDITIONAL PSO SPECIFIC ENTRIES
*---------------------------------*/
// Condition Types
#define CONDITIONAL_PSO_MIN 100 ///< Start of Conditional Entry Types
#define PSO_CONDITION_AND 100 ///< And Block - Start of Conditional block
#define PSO_CONDITION_LOC 101 ///< Location - Specify Socket, Channel, Dimms to be affected
#define PSO_CONDITION_SPD 102 ///< SPD - Specify a specific SPD value on a Dimm on the channel
#define PSO_CONDITION_REG 103 // Reserved
#define PSO_CONDITION_MAX 103 ///< End Of Condition Entry Types
// Action Types
#define PSO_ACTION_MIN 120 ///< Start of Action Entry Types
#define PSO_ACTION_ODT 120 ///< ODT values to override
#define PSO_ACTION_ADDRTMG 121 ///< Address/Timing values to override
#define PSO_ACTION_ODCCONTROL 122 ///< ODC Control values to override
#define PSO_ACTION_SLEWRATE 123 ///< Slew Rate value to override
#define PSO_ACTION_REG 124 // Reserved
#define PSO_ACTION_SPEEDLIMIT 125 ///< Memory Bus speed Limit based on configuration
#define PSO_ACTION_MAX 125 ///< End of Action Entry Types
#define CONDITIONAL_PSO_MAX 139 ///< End of Conditional Entry Types
/*----------------------------------------------------------------------------------------
* CONDITIONAL OVERRIDE TABLE MACROS
*----------------------------------------------------------------------------------------
*/
#define MEMCLK_DIS_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
PSO_MEMCLK_DIS, 10, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map
#define CKE_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map) \
PSO_CKE_TRI, 4, SocketID, ChannelID, Bit0Map, Bit1Map
#define ODT_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \
PSO_ODT_TRI, 6, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map
#define CS_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
PSO_CS_TRI, 10, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map
#define NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) \
PSO_MAX_DIMMS, 3, SocketID, ChannelID, NumberOfDimmSlotsPerChannel
#define NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) \
PSO_MAX_CHIPSELS, 3, SocketID, ChannelID, NumberOfChipSelectsPerChannel
#define NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) \
PSO_MAX_CHNLS, 3, SocketID, ANY_CHANNEL, NumberOfChannelsPerSocket
#define OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, TimingMode, BusSpeed) \
PSO_BUS_SPEED, 10, SocketID, ChannelID, TimingMode, (TimingMode >> 8), (TimingMode >> 16), (TimingMode >> 24), \
BusSpeed, (BusSpeed >> 8), (BusSpeed >> 16), (BusSpeed >> 24)
#define DRAM_TECHNOLOGY(SocketID, MemTechType) \
PSO_MEM_TECH, 6, SocketID, ANY_CHANNEL, MemTechType, (MemTechType >> 8), (MemTechType >> 16), (MemTechType >> 24)
#define WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
Byte6Seed, Byte7Seed, ByteEccSeed) \
PSO_WL_SEED, 11, SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
Byte6Seed, Byte7Seed, ByteEccSeed
#define HW_RXEN_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
Byte6Seed, Byte7Seed, ByteEccSeed) \
PSO_RXEN_SEED, 20, SocketID, ChannelID, Byte0Seed, (Byte0Seed >> 8), Byte1Seed, (Byte1Seed >> 8), Byte2Seed, (Byte2Seed >> 8), \
Byte3Seed, (Byte3Seed >> 8), Byte4Seed, (Byte4Seed >> 8), Byte5Seed, (Byte5Seed >> 8), Byte6Seed, (Byte6Seed >> 8), \
Byte7Seed, (Byte7Seed >> 8), ByteEccSeed, (ByteEccSeed >> 8)
#define NO_LRDIMM_CS67_ROUTING(SocketID, ChannelID) \
PSO_NO_LRDIMM_CS67_ROUTING, 3, SocketID, ChannelID, TRUE
/*----------------------------------------------------------------------------------------
* CONDITIONAL OVERRIDE TABLE MACROS
*----------------------------------------------------------------------------------------
*/
#define CONDITION_AND \
PSO_CONDITION_AND, 0
#define COND_LOC(SocketMsk, ChannelMsk, DimmMsk) \
PSO_CONDITION_LOC, 3, SocketMsk, ChannelMsk, DimmMsk
#define COND_SPD(Byte, Mask, Value) \
PSO_CONDITION_SPD, 3, Byte, Mask, Value
#define COND_REG(Access, Offset, Mask, Value) \
PSO_CONDITION_REG, 11, Access, (Offset & 0x0FF), (Offset >> 8), \
((Mask) & 0x0FF), (((Mask) >> 8) & 0x0FF), (((Mask) >> 16) & 0x0FF), (((Mask) >> 24) & 0x0FF), \
((Value) & 0x0FF), (((Value) >> 8) & 0x0FF), (((Value) >> 16) & 0x0FF), (((Value) >> 24) & 0x0FF)
#define ACTION_ODT(Frequency, Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt) \
PSO_ACTION_ODT, 9, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), ((Frequency >> 24)& 0x0FF), \
Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt
#define ACTION_ADDRTMG(Frequency, DimmConfig, AddrTmg) \
PSO_ACTION_ADDRTMG, 10, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
(AddrTmg & 0x0FF), ((AddrTmg >> 8)& 0x0FF), ((AddrTmg >> 16)& 0x0FF), ((AddrTmg >> 24)& 0x0FF)
#define ACTION_ODCCTRL(Frequency, DimmConfig, OdcCtrl) \
PSO_ACTION_ODCCONTROL, 10, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
(OdcCtrl & 0x0FF), ((OdcCtrl >> 8)& 0x0FF), ((OdcCtrl >> 16)& 0x0FF), ((OdcCtrl >> 24)& 0x0FF)
#define ACTION_SLEWRATE(Frequency, DimmConfig, SlewRate) \
PSO_ACTION_SLEWRATE, 10, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
(SlewRate & 0x0FF), ((SlewRate >> 8)& 0x0FF), ((SlewRate >> 16)& 0x0FF), ((SlewRate >> 24)& 0x0FF)
#define ACTION_SPEEDLIMIT(DimmConfig, Dimms, SpeedLimit15, SpeedLimit135, SpeedLimit125) \
PSO_ACTION_SPEEDLIMIT, 9, \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), Dimms, \
(SpeedLimit15 & 0x0FF), ((SpeedLimit15 >> 8)& 0x0FF), \
(SpeedLimit135 & 0x0FF), ((SpeedLimit135 >> 8)& 0x0FF), \
(SpeedLimit125 & 0x0FF), ((SpeedLimit125 >> 8)& 0x0FF)
/*----------------------------------------------------------------------------------------
* END OF CONDITIONAL OVERRIDE TABLE MACROS
*----------------------------------------------------------------------------------------
*/
#endif // _PLATFORM_MEMORY_CONFIGURATION_H_

162
src/vendorcode/amd/agesa/f14/Include/Topology.h
View File

@@ -1,162 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Topology interface definitions.
*
* Contains AMD AGESA internal interface for topology related data which
* is consumed by code other than HyperTransport init (and produced by
* HyperTransport init.)
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _TOPOLOGY_H_
#define _TOPOLOGY_H_
// Defines for limiting data structure maximum allocation and limit checking.
#define MAX_NODES 8
#define MAX_SOCKETS MAX_NODES
#define MAX_DIES 2
// Defines useful with package link
#define HT_LIST_MATCH_INTERNAL_LINK_0 0xFA
#define HT_LIST_MATCH_INTERNAL_LINK_1 0xFB
#define HT_LIST_MATCH_INTERNAL_LINK_2 0xFC
/**
* Hop Count Table.
* This is a heap data structure. The Hops array is filled as a size x size matrix.
* The unused space, if any, is all at the end.
*/
typedef struct {
UINT8 Size; ///< The row and column size of actual hop count data */
UINT8 Hops[MAX_NODES * MAX_NODES]; ///< Room for a dynamic two dimensional array of [size][size] */
} HOP_COUNT_TABLE;
/**
* Socket and Module to Node Map Item.
* Provide the Node Id and core id range for each module in each processor.
*/
typedef struct {
UINT8 Node; ///< The module's Node id.
UINT8 LowCore; ///< The lowest processor core id for this module.
UINT8 HighCore; ///< The highest processor core id for this module.
UINT8 EnabledComputeUnits; ///< The value of Enabled for this processor module.
UINT8 DualCoreComputeUnits; ///< The value of DualCore for this processor module.
} SOCKET_DIE_TO_NODE_ITEM;
/**
* Socket and Module to Node Map.
* This type is a pointer to the actual map, it can be used for a struct item or
* for typecasting a heap buffer pointer.
*/
typedef SOCKET_DIE_TO_NODE_ITEM (*SOCKET_DIE_TO_NODE_MAP)[MAX_SOCKETS][MAX_DIES];
/**
* Node id to Socket Die Map Item.
*/
typedef struct {
UINT8 Socket; ///< socket of the processor containing the Node.
UINT8 Die; ///< the module in the processor which is Node.
} NODE_TO_SOCKET_DIE_ITEM;
/**
* Node id to Socket Die Map.
*/
typedef NODE_TO_SOCKET_DIE_ITEM (*NODE_TO_SOCKET_DIE_MAP)[MAX_NODES];
/**
* Provide AP core with socket and node context at start up.
* This information is posted to the AP cores using a register as a mailbox.
*/
typedef struct {
UINT32 Node:4; ///< The node id of Core's node.
UINT32 Socket:4; ///< The socket of this Core's node.
UINT32 Module:2; ///< The internal module number for Core's node.
UINT32 ModuleType:2; ///< Single Module = 0, Multi-module = 1.
UINT32 :20; ///< Reserved
} AP_MAIL_INFO_FIELDS;
/**
* AP info fields can be written and read to a register.
*/
typedef union {
UINT32 Info; ///< Just a number for register access, or opaque passing.
AP_MAIL_INFO_FIELDS Fields; ///< access to the info fields.
} AP_MAIL_INFO;
/**
* Provide AP core with system degree and system core number at start up.
* This information is posted to the AP cores using a register as a mailbox.
*/
typedef struct {
UINT32 SystemDegree:3; ///< The number of connected links
UINT32 :3; ///< Reserved
UINT32 HeapIndex:6; ///< The zero-based system core number
UINT32 :20; ///< Reserved
} AP_MAIL_EXT_INFO_FIELDS;
/**
* AP info fields can be written and read to a register.
*/
typedef union {
UINT32 Info; ///< Just a number for register access, or opaque passing.
AP_MAIL_EXT_INFO_FIELDS Fields; ///< access to the info fields.
} AP_MAIL_EXT_INFO;
/**
* AP Info mailbox set.
*/
typedef struct {
AP_MAIL_INFO ApMailInfo; ///< The AP mail info
AP_MAIL_EXT_INFO ApMailExtInfo; ///< The extended AP mail info
} AP_MAILBOXES;
/**
* Provide a northbridge to package mapping for link assignments.
*
*/
typedef struct {
UINT8 Link; ///< The Node's link
UINT8 Module; ///< The internal module position of Node
UINT8 PackageLink; ///< The corresponding package link
} PACKAGE_HTLINK_MAP_ITEM;
/**
* A Processor's complete set of link assignments
*/
typedef PACKAGE_HTLINK_MAP_ITEM (*PACKAGE_HTLINK_MAP)[];
#endif // _TOPOLOGY_H_

138
src/vendorcode/amd/agesa/f14/Legacy/Proc/Dispatcher.c
View File

@@ -1,138 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD binary block interface
*
* Contains the block entry function dispatcher
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Legacy
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Dispatcher.h"
#include "Options.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE LEGACY_PROC_DISPATCHER_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
extern CONST DISPATCH_TABLE DispatchTable[];
extern AMD_MODULE_HEADER mCpuModuleID;
/*---------------------------------------------------------------------------------------*/
/**
* The Dispatcher is the entry point into the AGESA software. It takes a function
* number as entry parameter in order to invoke the published function
*
* @param[in,out] ConfigPtr
*
* @return AGESA Status.
*
*/
AGESA_STATUS
CALLCONV
AmdAgesaDispatcher (
IN OUT VOID *ConfigPtr
)
{
AGESA_STATUS Status;
MODULE_ENTRY ModuleEntry;
DISPATCH_TABLE *Entry;
Status = AGESA_UNSUPPORTED;
ModuleEntry = NULL;
Entry = (DISPATCH_TABLE *) DispatchTable;
while (Entry->FunctionId != 0) {
if ((((AMD_CONFIG_PARAMS *) ConfigPtr)->Func) == Entry->FunctionId) {
Status = Entry->EntryPoint (ConfigPtr);
break;
}
Entry++;
}
// 2. Try next dispatcher if possible, and we have not already got status back
if ((mCpuModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) {
ModuleEntry = (MODULE_ENTRY) mCpuModuleID.NextBlock->ModuleDispatcher;
if (ModuleEntry != NULL) {
Status = (*ModuleEntry) (ConfigPtr);
}
}
return (Status);
}
/*---------------------------------------------------------------------------------------*/
/**
* The host environment interface of callout.
*
* @param[in] Func
* @param[in] Data
* @param[in,out] ConfigPtr
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
CALLCONV
AmdAgesaCallout (
IN UINT32 Func,
IN UINTN Data,
IN OUT VOID *ConfigPtr
)
{
UINT32 Result;
Result = AGESA_UNSUPPORTED;
if (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr == NULL) {
return Result;
}
Result = (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr) (Func, Data, ConfigPtr);
return (Result);
}

3
src/vendorcode/amd/agesa/f14/Legacy/Proc/Makefile.inc
View File

@@ -1,3 +0,0 @@
libagesa-y += Dispatcher.c
libagesa-y += agesaCallouts.c
libagesa-y += hobTransfer.c

403
src/vendorcode/amd/agesa/f14/Legacy/Proc/agesaCallouts.c
View File

@@ -1,403 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD CPU AGESA Callout Functions
*
* Contains code to set / get useful platform information.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Common
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Dispatcher.h"
#include "cpuServices.h"
#include "Ids.h"
#include "Filecode.h"
#define FILECODE LEGACY_PROC_AGESACALLOUTS_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
AGESA_STATUS
AgesaGetIdsData (
IN UINTN Data,
IN OUT IDS_CALLOUT_STRUCT *IdsCalloutData
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S - (AGESA ONLY)
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
*
* Call the host environment interface to do the warm or cold reset.
*
* @param[in] ResetType Warm or Cold Reset is requested
* @param[in,out] StdHeader Config header
*
*/
VOID
AgesaDoReset (
IN UINTN ResetType,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
WARM_RESET_REQUEST Request;
// Clear warm request bit and set state bits to the current post stage
GetWarmResetFlag (StdHeader, &Request);
Request.RequestBit = FALSE;
Request.StateBits = Request.PostStage;
SetWarmResetFlag (StdHeader, &Request);
Status = AmdAgesaCallout (AGESA_DO_RESET, (UINT32)ResetType, (VOID *) StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
*
* Call the host environment interface to allocate buffer in main system memory.
*
* @param[in] FcnData
* @param[in,out] AllocParams Heap manager parameters
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaAllocateBuffer (
IN UINTN FcnData,
IN OUT AGESA_BUFFER_PARAMS *AllocParams
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_ALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) AllocParams);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to deallocate buffer in main system memory.
*
* @param[in] FcnData
* @param[in,out] DeallocParams Heap Manager parameters
*
* @return The AGESA Status returned from the callout.
*/
AGESA_STATUS
AgesaDeallocateBuffer (
IN UINTN FcnData,
IN OUT AGESA_BUFFER_PARAMS *DeallocParams
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_DEALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) DeallocParams);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
*
* Call the host environment interface to Locate buffer Pointer in main system memory
*
* @param[in] FcnData
* @param[in,out] LocateParams Heap manager parameters
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaLocateBuffer (
IN UINTN FcnData,
IN OUT AGESA_BUFFER_PARAMS *LocateParams
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_LOCATE_BUFFER, (UINT32)FcnData, (VOID *) LocateParams);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to launch APs
*
* @param[in] ApicIdOfCore
* @param[in,out] LaunchApParams
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaRunFcnOnAp (
IN UINTN ApicIdOfCore,
IN AP_EXE_PARAMS *LaunchApParams
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_RUNFUNC_ONAP, (UINT32)ApicIdOfCore, (VOID *) LaunchApParams);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to read an SPD's content.
*
* @param[in] FcnData
* @param[in,out] ReadSpd
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaReadSpd (
IN UINTN FcnData,
IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_READ_SPD, (UINT32)FcnData, ReadSpd);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to read an SPD's content.
*
* @param[in] FcnData
* @param[in,out] ReadSpd
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaReadSpdRecovery (
IN UINTN FcnData,
IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_READ_SPD_RECOVERY, (UINT32)FcnData, ReadSpd);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] FcnData
* @param[in,out] MemData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaHookBeforeDramInitRecovery (
IN UINTN FcnData,
IN OUT MEM_DATA_STRUCT *MemData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, (UINT32)FcnData, MemData);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] FcnData
* @param[in,out] MemData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaHookBeforeDramInit (
IN UINTN FcnData,
IN OUT MEM_DATA_STRUCT *MemData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DRAM_INIT, (UINT32)FcnData, MemData);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] FcnData
* @param[in,out] MemData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaHookBeforeDQSTraining (
IN UINTN FcnData,
IN OUT MEM_DATA_STRUCT *MemData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DQS_TRAINING, (UINT32)FcnData, MemData);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] FcnData
* @param[in,out] MemData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaHookBeforeExitSelfRefresh (
IN UINTN FcnData,
IN OUT MEM_DATA_STRUCT *MemData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_EXIT_SELF_REF, (UINT32)FcnData, MemData);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] Data
* @param[in,out] IdsCalloutData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaGetIdsData (
IN UINTN Data,
IN OUT IDS_CALLOUT_STRUCT *IdsCalloutData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_GET_IDS_INIT_DATA, (UINT32)Data, IdsCalloutData);
return Status;
}
/*----------------------------------------------------------------------------------------*/
/**
* PCIE slot reset control
*
*
*
* @param[in] FcnData Function data
* @param[in] ResetInfo Reset information
* @retval Status Agesa status
*/
AGESA_STATUS
AgesaPcieSlotResetControl (
IN UINTN FcnData,
IN PCIe_SLOT_RESET_INFO *ResetInfo
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_GNB_PCIE_SLOT_RESET, (UINT32) FcnData, ResetInfo);
return Status;
}

395
src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c
View File

@@ -1,395 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Hob Transfer functions.
*
* Contains code that copy Heap to temp memory or main memory.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuRegisters.h"
#include "GeneralServices.h"
#include "cpuServices.h"
#include "cpuCacheInit.h"
#include "cpuFamilyTranslation.h"
#include "heapManager.h"
//#include "cpuLateInit.h"
#include "cpuEnvInit.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE LEGACY_PROC_HOBTRANSFER_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P U B L I C F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
extern BUILD_OPT_CFG UserOptions;
/* -----------------------------------------------------------------------------*/
/**
*
* CopyHeapToTempRamAtPost
*
* This function copies BSP heap content to RAM
*
* @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
*
* @retval AGESA_STATUS
*
*/
AGESA_STATUS
CopyHeapToTempRamAtPost (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 *BaseAddressInCache;
UINT8 *BaseAddressInTempMem;
UINT8 *Source;
UINT8 *Destination;
UINT8 AlignTo16ByteInCache;
UINT8 AlignTo16ByteInTempMem;
UINT8 Ignored;
UINT32 SizeOfNodeData;
UINT32 TotalSize;
UINT32 HeapRamFixMtrr;
UINT32 HeapRamVariableMtrr;
UINT32 HeapInCacheOffset;
UINT64 MsrData;
UINT64 VariableMtrrBase;
UINT64 VariableMtrrMask;
UINTN AmdHeapRamAddress;
AGESA_STATUS IgnoredStatus;
BUFFER_NODE *HeapInCache;
BUFFER_NODE *HeapInTempMem;
HEAP_MANAGER *HeapManagerInCache;
HEAP_MANAGER *HeapManagerInTempMem;
CACHE_INFO *CacheInfoPtr;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
AmdHeapRamAddress = (UINTN) UserOptions.CfgHeapDramAddress;
//
//If the user define address above 1M, Mem Init has already set
//whole available memory as WB cacheable.
//
if (AmdHeapRamAddress < 0x100000) {
// Region below 1MB
// Fixed MTRR region
// turn on modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
if (AmdHeapRamAddress >= 0xC0000) {
//
// 0xC0000 ~ 0xFFFFF
//
HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX4k_C0000 + (((AmdHeapRamAddress >> 16) & 0x3) * 2));
MsrData = AMD_MTRR_FIX4K_UC_DRAM;
LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader);
LibAmdMsrWrite ((HeapRamFixMtrr + 1), &MsrData, StdHeader);
} else if (AmdHeapRamAddress >= 0x80000) {
//
// 0x80000~0xBFFFF
//
HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX16k_80000 + ((AmdHeapRamAddress >> 17) & 0x1));
MsrData = AMD_MTRR_FIX16K_UC_DRAM;
LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader);
} else {
//
// 0x0 ~ 0x7FFFF
//
LibAmdMsrRead (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
MsrData = MsrData & (~(0xFF << (8 * ((AmdHeapRamAddress >> 16) & 0x7))));
MsrData = MsrData | (AMD_MTRR_FIX64K_UC_DRAM << (8 * ((AmdHeapRamAddress >> 16) & 0x7)));
LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
}
// Turn on MTRR enable bit and turn off modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x40000;
MsrData &= 0xFFFFFFFFFFF7FFFF;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
} else {
// Region above 1MB
// Variable MTRR region
// Get family specific cache Info
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, StdHeader);
// Find an empty MTRRphysBase/MTRRphysMask
for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE;
HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0;
HeapRamVariableMtrr--) {
LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
if ((VariableMtrrBase == 0) && (VariableMtrrMask == 0)) {
break;
}
}
if (HeapRamVariableMtrr < AMD_MTRR_VARIABLE_BASE0) {
// All variable MTRR is used.
ASSERT (FALSE);
}
// Set variable MTRR base and mask
// If the address ranges of two or more MTRRs overlap
// and if at least one of the memory types is UC, the UC memory type is used.
VariableMtrrBase = (UINT64) (AmdHeapRamAddress & CacheInfoPtr->HeapBaseMask);
VariableMtrrMask = CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK;
LibAmdMsrWrite (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
LibAmdMsrWrite ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
}
// Copying Heap content
if (IsBsp (StdHeader, &IgnoredStatus)) {
TotalSize = sizeof (HEAP_MANAGER);
SizeOfNodeData = 0;
AlignTo16ByteInTempMem = 0;
BaseAddressInCache = (UINT8 *) StdHeader->HeapBasePtr;
HeapManagerInCache = (HEAP_MANAGER *) BaseAddressInCache;
HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset;
HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset);
BaseAddressInTempMem = (UINT8 *) (intptr_t) (UserOptions.CfgHeapDramAddress);
HeapManagerInTempMem = (HEAP_MANAGER *) BaseAddressInTempMem;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
// copy heap from cache to temp memory.
// only heap with persist great than HEAP_LOCAL_CACHE will be copied.
// Note: Only copy heap with persist greater than HEAP_LOCAL_CACHE.
while (HeapInCacheOffset != AMD_HEAP_INVALID_HEAP_OFFSET) {
if (HeapInCache->Persist > HEAP_LOCAL_CACHE) {
AlignTo16ByteInCache = HeapInCache->PadSize;
AlignTo16ByteInTempMem = (UINT8) ((0x10 - (((UINTN) (VOID *) HeapInTempMem + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF);
SizeOfNodeData = HeapInCache->BufferSize - AlignTo16ByteInCache;
TotalSize = (UINT32) (TotalSize + sizeof (BUFFER_NODE) + SizeOfNodeData + AlignTo16ByteInTempMem);
Source = (UINT8 *) HeapInCache + sizeof (BUFFER_NODE) + AlignTo16ByteInCache;
Destination = (UINT8 *) HeapInTempMem + sizeof (BUFFER_NODE) + AlignTo16ByteInTempMem;
LibAmdMemCopy (HeapInTempMem, HeapInCache, sizeof (BUFFER_NODE), StdHeader);
LibAmdMemCopy (Destination, Source, SizeOfNodeData, StdHeader);
HeapInTempMem->OffsetOfNextNode = TotalSize;
HeapInTempMem->BufferSize = SizeOfNodeData + AlignTo16ByteInTempMem;
HeapInTempMem->PadSize = AlignTo16ByteInTempMem;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
}
HeapInCacheOffset = HeapInCache->OffsetOfNextNode;
HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset);
}
// initialize heap manager
if (TotalSize == sizeof (HEAP_MANAGER)) {
// heap is empty
HeapManagerInTempMem->UsedSize = sizeof (HEAP_MANAGER);
HeapManagerInTempMem->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET;
HeapManagerInTempMem->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER);
} else {
// heap is NOT empty
HeapManagerInTempMem->UsedSize = TotalSize;
HeapManagerInTempMem->FirstActiveBufferOffset = sizeof (HEAP_MANAGER);
HeapManagerInTempMem->FirstFreeSpaceOffset = TotalSize;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize - SizeOfNodeData - AlignTo16ByteInTempMem - sizeof (BUFFER_NODE));
HeapInTempMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
}
// heap signature
HeapManagerInCache->Signature = 0x00000000;
HeapManagerInTempMem->Signature = HEAP_SIGNATURE_VALID;
// Free space node
HeapInTempMem->BufferSize = (UINT32) (AMD_HEAP_SIZE_PER_CORE - TotalSize);
HeapInTempMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
}
return AGESA_SUCCESS;
}
/* -----------------------------------------------------------------------------*/
/**
*
* CopyHeapToMainRamAtPost
*
* This function copies Temp Ram heap content to Main Ram
*
* @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
*
* @retval AGESA_STATUS
*
*/
AGESA_STATUS
CopyHeapToMainRamAtPost (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 *BaseAddressInTempMem;
UINT8 *BaseAddressInMainMem;
UINT8 *Source;
UINT8 *Destination;
UINT8 AlignTo16ByteInTempMem;
UINT8 AlignTo16ByteInMainMem;
UINT8 Ignored;
UINT32 SizeOfNodeData;
UINT32 TotalSize;
UINT32 HeapInTempMemOffset;
UINT32 HeapRamVariableMtrr;
UINT64 VariableMtrrBase;
UINT64 VariableMtrrMask;
AGESA_STATUS IgnoredStatus;
BUFFER_NODE *HeapInTempMem;
BUFFER_NODE *HeapInMainMem;
HEAP_MANAGER *HeapManagerInTempMem;
HEAP_MANAGER *HeapManagerInMainMem;
AGESA_BUFFER_PARAMS AgesaBuffer;
CACHE_INFO *CacheInfoPtr;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
if (IsBsp (StdHeader, &IgnoredStatus)) {
TotalSize = sizeof (HEAP_MANAGER);
SizeOfNodeData = 0;
AlignTo16ByteInMainMem = 0;
BaseAddressInTempMem = (UINT8 *) StdHeader->HeapBasePtr;
HeapManagerInTempMem = (HEAP_MANAGER *) StdHeader->HeapBasePtr;
HeapInTempMemOffset = HeapManagerInTempMem->FirstActiveBufferOffset;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset);
AgesaBuffer.StdHeader = *StdHeader;
AgesaBuffer.BufferHandle = AMD_HEAP_IN_MAIN_MEMORY_HANDLE;
AgesaBuffer.BufferLength = AMD_HEAP_SIZE_PER_CORE;
if (AgesaAllocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) {
return AGESA_ERROR;
}
BaseAddressInMainMem = (UINT8 *) AgesaBuffer.BufferPointer;
HeapManagerInMainMem = (HEAP_MANAGER *) BaseAddressInMainMem;
HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize);
LibAmdMemFill (BaseAddressInMainMem, 0x00, AMD_HEAP_SIZE_PER_CORE, StdHeader);
// copy heap from temp memory to main memory.
// only heap with persist great than HEAP_TEMP_MEM will be copied.
// Note: Only copy heap buffers with persist greater than HEAP_TEMP_MEM.
while (HeapInTempMemOffset != AMD_HEAP_INVALID_HEAP_OFFSET) {
if (HeapInTempMem->Persist > HEAP_TEMP_MEM) {
AlignTo16ByteInTempMem = HeapInTempMem->PadSize;
AlignTo16ByteInMainMem = (UINT8) ((0x10 - (((UINTN) (VOID *) HeapInMainMem + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF);
SizeOfNodeData = HeapInTempMem->BufferSize - AlignTo16ByteInTempMem;
TotalSize = (UINT32) (TotalSize + sizeof (BUFFER_NODE) + SizeOfNodeData + AlignTo16ByteInMainMem);
Source = (UINT8 *) HeapInTempMem + sizeof (BUFFER_NODE) + AlignTo16ByteInTempMem;
Destination = (UINT8 *) HeapInMainMem + sizeof (BUFFER_NODE) + AlignTo16ByteInMainMem;
LibAmdMemCopy (HeapInMainMem, HeapInTempMem, sizeof (BUFFER_NODE), StdHeader);
LibAmdMemCopy (Destination, Source, SizeOfNodeData, StdHeader);
HeapInMainMem->OffsetOfNextNode = TotalSize;
HeapInMainMem->BufferSize = SizeOfNodeData + AlignTo16ByteInMainMem;
HeapInMainMem->PadSize = AlignTo16ByteInMainMem;
HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize);
}
HeapInTempMemOffset = HeapInTempMem->OffsetOfNextNode;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset);
}
// initialize heap manager
if (TotalSize == sizeof (HEAP_MANAGER)) {
// heap is empty
HeapManagerInMainMem->UsedSize = sizeof (HEAP_MANAGER);
HeapManagerInMainMem->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET;
HeapManagerInMainMem->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER);
} else {
// heap is NOT empty
HeapManagerInMainMem->UsedSize = TotalSize;
HeapManagerInMainMem->FirstActiveBufferOffset = sizeof (HEAP_MANAGER);
HeapManagerInMainMem->FirstFreeSpaceOffset = TotalSize;
HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize - SizeOfNodeData - AlignTo16ByteInMainMem - sizeof (BUFFER_NODE));
HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize);
}
// heap signature
HeapManagerInTempMem->Signature = 0x00000000;
HeapManagerInMainMem->Signature = HEAP_SIGNATURE_VALID;
// Free space node
HeapInMainMem->BufferSize = AMD_HEAP_SIZE_PER_CORE - TotalSize;
HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
}
// if address of heap in temp memory is above 1M, then we must used one variable MTRR.
if (StdHeader->HeapBasePtr >= (void *) 0x100000) {
// Find out which variable MTRR was used in CopyHeapToTempRamAtPost.
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, StdHeader);
for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE;
HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0;
HeapRamVariableMtrr--) {
LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
if ((VariableMtrrBase == ((UINT64) (intptr_t) (StdHeader->HeapBasePtr) & CacheInfoPtr->HeapBaseMask)) &&
(VariableMtrrMask == (CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK))) {
break;
}
}
if (HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0) {
// Clear variable MTRR which set in CopyHeapToTempRamAtPost.
VariableMtrrBase = 0;
VariableMtrrMask = 0;
LibAmdMsrWrite (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
LibAmdMsrWrite ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
}
}
return AGESA_SUCCESS;
}

121
src/vendorcode/amd/agesa/f14/MainPage.h
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@@ -1,121 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Create outline and references for mainpage documentation.
*
* Design guides, maintenance guides, and general documentation, are
* collected using this file onto the documentation mainpage.
* This file contains doxygen comment blocks, only.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Documentation
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/**
* @mainpage
*
* The design and maintenance documentation for AGESA Sample Code is organized as
* follows. On this page, you can reference design guides, maintenance guides, and
* general documentation. Detailed Data Structure, Function, and Interface documentation
* may be found using the Data Structures or Files tabs. See Related Pages for a
* Release content summary, and, if this is not a production release, lists of To Do's,
* Deprecated items, etc.
*
* @subpage starthere "Start Here - Initial Porting and Integration."
*
* @subpage optionmain "Build Configuration and Options Guides and Documentation."
*
* @subpage commonmain "Processor Common Component Guides and Documentation."
*
* @subpage cpumain "CPU Component Guides and Documentation."
*
* @subpage htmain "HT Component Guides and Documentation."
*
* @subpage memmain "MEM Component Guides and Documentation."
*
* @subpage gnbmain "GNB Component Documentation."
*
* @subpage idsmain "IDS Component Guides and Documentation."
*
* @subpage recoverymain "Recovery Component Guides and Documentation."
*
*/
/**
* @page starthere Initial Porting and Integration
*
* @par Basic Check List
*
* <ul>
* <li> Copy the \<plat\>Options.c file from the Addendum directory to the platform tip build directory.
* AMD recommends the use of a sub-directory named AGESA to contain these files and the build output files.
* <li> Copy the OptionsIds.h content in the spec to OptionsIds.h in the platform build tip directory
* and make changes to enable the IDS support desired. It is highly recommended to set the following for
* initial integration and development:@n
* @code
* #define IDSOPT_IDS_ENABLED TRUE
* #define IDSOPT_ERROR_TRAP_ENABLED TRUE
* #define IDSOPT_ASSERT_ENABLED TRUE
* @endcode
* <li> Edit and modify the option selections in those two files to meet the needs of the specific platform.
* <li> Set the environment variable AGESA_ROOT to the root folder of the AGESA code.
* <li> Set the environment variable AGESA_OptsDir the platform build tip AGESA directory.
* <li> Generate the doxygen documentation or locate the file arch2008.chm within your AGESA release package.
* </ul>
*
* @par Debugging Using ASSERT and IDS_ERROR_TRAP
*
* While AGESA code uses ::ASSERT and ::IDS_ERROR_TRAP to check for internal errors, these macros can also
* catch and assist debug of wrapper and platform BIOS issues.
*
* When an ::ASSERT fails or an ::IDS_ERROR_TRAP is executed, the AGESA code will enter a halt loop and display a
* Stop Code. A Stop Code is eight hex digits. The first (most significant) four are the FILECODE.
* FILECODEs can be looked up in Filecode.h to determine which file contains the stop macro. Each file has a
* unique code value.
* The least significant digits are the line number in that file.
* For example, 0210 means the macro is on line two hundred ten.
* (see ::IdsErrorStop for more details on stop code display.)
*
* Enabling ::ASSERT and ::IDS_ERROR_TRAP ensure errors are caught and also provide a useful debug assist.
* Comments near each macro use will describe the nature of the error and typical wrapper errors or other
* root causes.
*
* After your wrapper consistently executes ::ASSERT and ::IDS_ERROR_TRAP stop free, you can disable them in
* OptionsIds.h, except for regression testing. IDS is not expected to be enabled in production BIOS builds.
*
*/

46
src/vendorcode/amd/agesa/f14/Makefile.inc
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@@ -1,46 +0,0 @@
#*****************************************************************************
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# * Neither the name of Advanced Micro Devices, Inc. nor the names of
# its contributors may be used to endorse or promote products derived
# from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#*****************************************************************************
# AGESA V5 Files
AGESA_ROOT = src/vendorcode/amd/agesa/f14
AGESA_AUTOINCLUDES := $(shell find $(AGESA_ROOT)/Proc -type d -exec echo -n "-I"{}" " \;)
AGESA_INC = -I$(src)/vendorcode/amd/include
AGESA_INC += -I$(AGESA_ROOT)
AGESA_INC += -I$(AGESA_ROOT)/../common
AGESA_INC += -I$(AGESA_ROOT)/Include
AGESA_INC += -I$(src)/mainboard/$(MAINBOARDDIR) # OptionsIds.h
BUILDOPTS_INCLUDES = -I$(AGESA_ROOT)/Config $(AGESA_INC) $(AGESA_AUTOINCLUDES)
CPPFLAGS_x86_32 += $(AGESA_INC)
CPPFLAGS_x86_64 += $(AGESA_INC)
#######################################################################
subdirs-y += Legacy/Proc
subdirs-y += $(dir $(shell cd $(dir); find Proc -name Makefile.inc))

238
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14C6State.c
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@@ -1,238 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 C6 C-state feature support functions.
*
* Provides the functions necessary to initialize the C6 feature.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F14
* @e \$Revision: 37004 $ @e \$Date: 2010-08-28 02:23:00 +0800 (Sat, 28 Aug 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuRegisters.h"
#include "cpuEarlyInit.h"
#include "cpuFeatures.h"
#include "cpuC6State.h"
#include "cpuF14PowerMgmt.h"
#include "OptionFamily14hEarlySample.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_F14C6STATE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
extern F14_ES_C6_SUPPORT F14EarlySampleC6Support;
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Is C6 supported on this CPU
*
* @param[in] C6Services Pointer to this CPU's C6 family services.
* @param[in] Socket This core's zero-based socket number.
* @param[in] StdHeader Config Handle for library, services.
*
* @retval TRUE C6 state is supported.
* @retval FALSE C6 state is not supported.
*
*/
BOOLEAN
STATIC
F14IsC6Supported (
IN C6_FAMILY_SERVICES *C6Services,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 PciRegister;
BOOLEAN IsEnabled;
PCI_ADDR PciAddress;
IsEnabled = TRUE;
PciAddress.AddressValue = CPU_STATE_PM_CTRL1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
if ((((CPU_STATE_PM_CTRL1_REGISTER *) &PciRegister)->CoreC6Cap == 0) &&
(((CPU_STATE_PM_CTRL1_REGISTER *) &PciRegister)->PkgC6Cap == 0)) {
IsEnabled = FALSE;
}
F14EarlySampleC6Support.F14IsC6SupportedHook (&IsEnabled, StdHeader);
return IsEnabled;
}
/*---------------------------------------------------------------------------------------*/
/**
* Enable C6 on a family 14h CPU.
*
* @param[in] C6Services Pointer to this CPU's C6 family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @return AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F14InitializeC6 (
IN C6_FAMILY_SERVICES *C6Services,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 i;
UINT32 MaxEnabledPstate;
UINT32 PciRegister;
UINT64 MsrReg;
PCI_ADDR PciAddress;
for (i = MSR_PSTATE_7; i > MSR_PSTATE_0; i--) {
LibAmdMsrRead (i, &MsrReg, StdHeader);
if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) {
break;
}
}
MaxEnabledPstate = i - MSR_PSTATE_0;
if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
// Program D18F4x1AC[CoreC6Dis] to 0.
// Program D18F4x1AC[PkgC6Dis] to 0.
PciAddress.AddressValue = CPU_STATE_PM_CTRL1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
((CPU_STATE_PM_CTRL1_REGISTER *) &PciRegister)->CoreC6Dis = 0;
((CPU_STATE_PM_CTRL1_REGISTER *) &PciRegister)->PkgC6Dis = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
F14EarlySampleC6Support.F14InitializeC6 (StdHeader);
} else {
// Ensure D18F2x118[C6DramLock] and D18F4x12C[C6Base] are programmed.
PciAddress.AddressValue = MEM_CFG_LOW_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
ASSERT (((MEM_CFG_LOW_REGISTER *) &PciRegister)->C6DramLock == 1);
PciAddress.AddressValue = C6_BASE_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
ASSERT (((C6_BASE_REGISTER *) &PciRegister)->C6Base != 0);
// If PC6 is supported, program D18F4x1AC[PstateIdCoreOffExit] to
// the index of lowest-performance Pstate with MSRC001_00[6B:64]
// [PstateEn] == 1 on core 0.
PciAddress.AddressValue = CPU_STATE_PM_CTRL1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
if (((CPU_STATE_PM_CTRL1_REGISTER *) &PciRegister)->PkgC6Cap == 1) {
((CPU_STATE_PM_CTRL1_REGISTER *) &PciRegister)->PstateIdCoreOffExit = MaxEnabledPstate;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
}
// Program D18F4x118 to 0000_0101h.
PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR;
PciRegister = 0x00000101;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
}
return AGESA_SUCCESS;
}
/*---------------------------------------------------------------------------------------*/
/**
* Reload microcode patch for a family 14h CPU after memory is initialized.
*
* @param[in] StdHeader Config Handle for library, services.
*
*/
VOID
STATIC
F14ReloadMicrocodePatchAfterMemInit (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrValue;
// To load a microcode patch while using the cache as general storage,
// the following steps are followed:
// 1. Program MSRC001_102B[L2AllocDcFlushVictim]=1.
// 2. Load the microcode patch.
// 3. Program MSRC001_102B[L2AllocDcFlushVictim]=0.
LibAmdMsrRead (MSR_BU_CFG3, &MsrValue, StdHeader);
MsrValue = MsrValue | BIT7;
LibAmdMsrWrite (MSR_BU_CFG3, &MsrValue, StdHeader);
// Reload microcode patches.
LoadMicrocodePatch (StdHeader);
LibAmdMsrRead (MSR_BU_CFG3, &MsrValue, StdHeader);
MsrValue = MsrValue & ~((UINT64)BIT7);
LibAmdMsrWrite (MSR_BU_CFG3, &MsrValue, StdHeader);
}
CONST C6_FAMILY_SERVICES ROMDATA F14C6Support =
{
0,
F14IsC6Supported,
F14InitializeC6,
F14ReloadMicrocodePatchAfterMemInit
};

285
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14IoCstate.c
View File

@@ -1,285 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 IO C-state feature support functions.
*
* Provides the functions necessary to initialize the IO C-state feature.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F14
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuRegisters.h"
#include "cpuServices.h"
#include "cpuFeatures.h"
#include "cpuIoCstate.h"
#include "cpuF14PowerMgmt.h"
#include "cpuLateInit.h"
#include "cpuApicUtilities.h"
#include "CommonReturns.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_F14IOCSTATE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
STATIC
F14InitializeIoCstateOnCore (
IN VOID *CstateBaseMsr,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Enable IO Cstate on a family 14h CPU.
* Implement steps 1 to 3 of BKDG section 2.5.4.2.9 BIOS Requirements for Initialization
*
* @param[in] IoCstateServices Pointer to this CPU's IO Cstate family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @return AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F14InitializeIoCstate (
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 i;
UINT32 MaxEnabledPstate;
UINT32 PciRegister;
UINT64 MsrReg;
AP_TASK TaskPtr;
PCI_ADDR PciAddress;
if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
for (i = MSR_PSTATE_7; i > MSR_PSTATE_0; i--) {
LibAmdMsrRead (i, &MsrReg, StdHeader);
if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) {
break;
}
}
MaxEnabledPstate = i - MSR_PSTATE_0;
// Initialize MSRC001_0073[CstateAddr] on each core to a region of
// the IO address map with 8 consecutive available addresses.
MsrReg = 0;
((CSTATE_ADDRESS_MSR *) &MsrReg)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
ASSERT ((((CSTATE_ADDRESS_MSR *) &MsrReg)->CstateAddr != 0) &&
(((CSTATE_ADDRESS_MSR *) &MsrReg)->CstateAddr <= 0xFFF8));
TaskPtr.FuncAddress.PfApTaskI = F14InitializeIoCstateOnCore;
TaskPtr.DataTransfer.DataSizeInDwords = 2;
TaskPtr.DataTransfer.DataPtr = &MsrReg;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
// Program D18F4x1A8[PService] to the index of lowest-performance
// P-state with MSRC001_00[6B:64][PstateEn]==1 on core 0.
PciAddress.AddressValue = CPU_STATE_PM_CTRL0_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
((CPU_STATE_PM_CTRL0_REGISTER *) &PciRegister)->PService = MaxEnabledPstate;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
// Program D18F4x1AC[CstPminEn] to 1.
PciAddress.AddressValue = CPU_STATE_PM_CTRL1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
((CPU_STATE_PM_CTRL1_REGISTER *) &PciRegister)->CstPminEn = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
}
return AGESA_SUCCESS;
}
/*---------------------------------------------------------------------------------------*/
/**
* Enable C-State on a family 14h core.
*
* @param[in] CstateBaseMsr MSR value to write to C001_0073 as determined by core 0.
* @param[in] StdHeader Config Handle for library, services.
*
*/
VOID
STATIC
F14InitializeIoCstateOnCore (
IN VOID *CstateBaseMsr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
// Initialize MSRC001_0073[CstateAddr] on each core
LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
* Returns the size of CST object
*
* @param[in] IoCstateServices IO Cstate services.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data
* @param[in] StdHeader Config Handle for library, services.
*
* @retval CstObjSize Size of CST Object
*
*/
UINT32
STATIC
F14GetAcpiCstObj (
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return (CST_HEADER_SIZE + CST_BODY_SIZE);
}
/*---------------------------------------------------------------------------------------*/
/**
* Routine to generate the C-State ACPI objects
*
* @param[in] IoCstateServices IO Cstate services.
* @param[in] LocalApicId Local Apic Id for each core.
* @param[in] **PstateAcpiBufferPtr Pointer to the Acpi Buffer Pointer.
* @param[in] StdHeader Config Handle for library, services.
*
*/
VOID
STATIC
F14CreateAcpiCstObj (
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
IN UINT8 LocalApicId,
IN OUT VOID **PstateAcpiBufferPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrData;
CST_HEADER_STRUCT *CstHeaderPtr;
CST_BODY_STRUCT *CstBodyPtr;
// Read from MSR C0010073 to obtain CstateAddr
LibAmdMsrRead (MSR_CSTATE_ADDRESS, &MsrData, StdHeader);
ASSERT ((((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr != 0) &&
(((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr <= 0xFFF8));
// Typecast the pointer
CstHeaderPtr = (CST_HEADER_STRUCT *) *PstateAcpiBufferPtr;
// Set CST Header
CstHeaderPtr->NameOpcode = NAME_OPCODE;
CstHeaderPtr->CstName_a__ = CST_NAME__;
CstHeaderPtr->CstName_a_C = CST_NAME_C;
CstHeaderPtr->CstName_a_S = CST_NAME_S;
CstHeaderPtr->CstName_a_T = CST_NAME_T;
// Typecast the pointer
CstHeaderPtr++;
CstBodyPtr = (CST_BODY_STRUCT *) CstHeaderPtr;
// Set CST Body
CstBodyPtr->PkgOpcode = PACKAGE_OPCODE;
CstBodyPtr->PkgLength = CST_LENGTH;
CstBodyPtr->PkgElements = CST_NUM_OF_ELEMENTS;
CstBodyPtr->BytePrefix = BYTE_PREFIX_OPCODE;
CstBodyPtr->Count = CST_COUNT;
CstBodyPtr->PkgOpcode2 = PACKAGE_OPCODE;
CstBodyPtr->PkgLength2 = CST_PKG_LENGTH;
CstBodyPtr->PkgElements2 = CST_PKG_ELEMENTS;
CstBodyPtr->BufferOpcode = BUFFER_OPCODE;
CstBodyPtr->BufferLength = CST_SUBPKG_LENGTH;
CstBodyPtr->BufferElements = CST_SUBPKG_ELEMENTS;
CstBodyPtr->BufferOpcode2 = BUFFER_OPCODE;
CstBodyPtr->GdrOpcode = GENERIC_REG_DESCRIPTION;
CstBodyPtr->GdrLength = CST_GDR_LENGTH;
CstBodyPtr->AddrSpaceId = GDR_ASI_SYSTEM_IO;
CstBodyPtr->RegBitWidth = 0x08;
CstBodyPtr->RegBitOffset = 0x00;
CstBodyPtr->AddressSize = GDR_ASZ_BYTE_ACCESS;
CstBodyPtr->RegisterAddr = ((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr + 1;
CstBodyPtr->EndTag = 0x0079;
CstBodyPtr->BytePrefix2 = BYTE_PREFIX_OPCODE;
CstBodyPtr->Type = CST_C2_TYPE;
CstBodyPtr->WordPrefix = WORD_PREFIX_OPCODE;
CstBodyPtr->Latency = 0x64;
CstBodyPtr->DWordPrefix = DWORD_PREFIX_OPCODE;
CstBodyPtr->Power = 0;
CstBodyPtr++;
//Update the pointer
*PstateAcpiBufferPtr = CstBodyPtr;
}
CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F14IoCstateSupport =
{
0,
(PF_IO_CSTATE_IS_SUPPORTED) CommonReturnTrue,
F14InitializeIoCstate,
F14GetAcpiCstObj,
F14CreateAcpiCstObj,
(PF_IO_CSTATE_IS_CSD_GENERATED) CommonReturnFalse
};

273
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c
View File

@@ -1,273 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 Microcode patch.
*
* Fam14 Microcode Patch rev 0500000B for 5000 or equivalent.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x14
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuEarlyInit.h"
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
// Patch code 0500000B for 5000 and equivalent
CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500000B =
{{
0x10, 0x20, 0x01, 0x06, 0x0b, 0x00, 0x00, 0x05,
0x01, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x50, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa,
0x67, 0xe5, 0x52, 0x3e, 0x6b, 0x1c, 0x70, 0x69,
0xd9, 0x1c, 0x8d, 0xab, 0xab, 0xc4, 0xce, 0xc5,
0x4f, 0xc9, 0x2d, 0x81, 0xeb, 0x2b, 0x49, 0x14,
0x39, 0xc9, 0xea, 0xd1, 0x6e, 0x83, 0x4c, 0x14,
0x6c, 0x57, 0x06, 0xf8, 0xcf, 0xa5, 0xb4, 0x4a,
0xab, 0x40, 0x63, 0x38, 0x0c, 0x32, 0x56, 0x28,
0x46, 0xe5, 0x2c, 0x62, 0x26, 0x54, 0xf7, 0xa2,
0x45, 0xfe, 0xcb, 0x20, 0x01, 0xb1, 0x6d, 0x5d,
0xbc, 0xe8, 0xf9, 0xe0, 0x4e, 0x11, 0x94, 0x1f,
0x20, 0x90, 0x31, 0x33, 0x23, 0x09, 0xb4, 0xa4,
0xc8, 0x88, 0xa4, 0x93, 0xee, 0x36, 0xe4, 0x18,
0xb8, 0xbd, 0x66, 0x5a, 0x69, 0x03, 0x9c, 0xc0,
0xc9, 0x44, 0x38, 0x29, 0xbe, 0xba, 0x4d, 0xa7,
0x42, 0xac, 0xe3, 0x6a, 0xf9, 0xfa, 0xa9, 0x04,
0xec, 0x93, 0x47, 0xf0, 0x1f, 0x49, 0xf1, 0xe7,
0x69, 0x24, 0x4c, 0x88, 0x1e, 0xad, 0xc3, 0x57,
0xec, 0x45, 0xd4, 0xeb, 0xd1, 0xdf, 0xdc, 0x04,
0x3b, 0xc1, 0xb0, 0x8d, 0xa1, 0x3a, 0x4d, 0x79,
0x4b, 0xad, 0x70, 0x9b, 0x3d, 0xcf, 0x7a, 0x8d,
0xe1, 0xc2, 0xdb, 0x53, 0x0b, 0xbd, 0xf8, 0x94,
0x7c, 0x2c, 0x4d, 0x50, 0xdf, 0x90, 0x31, 0x52,
0x8f, 0xb4, 0xd6, 0x1e, 0x37, 0x3c, 0x98, 0x2b,
0x26, 0x8f, 0x0a, 0x9c, 0x15, 0x8f, 0x62, 0x83,
0x11, 0xbf, 0xc1, 0x74, 0xd7, 0x35, 0xa4, 0x82,
0xba, 0xd3, 0xcb, 0xb6, 0xa0, 0xca, 0x7e, 0x23,
0xaa, 0x12, 0x77, 0x24, 0xdb, 0xfb, 0x82, 0x4f,
0x94, 0xee, 0xbe, 0xcd, 0x7a, 0x69, 0x63, 0xf6,
0x7d, 0x31, 0xb7, 0x9a, 0xfa, 0xe5, 0xb3, 0x1d,
0x39, 0xdb, 0x40, 0xba, 0x1b, 0xaf, 0xa9, 0xc9,
0x24, 0xea, 0x78, 0x47, 0xf2, 0x19, 0x2b, 0x63,
0x07, 0xe1, 0x4c, 0xa8, 0xdb, 0xff, 0x34, 0x07,
0xe8, 0x1d, 0x75, 0xcc, 0x99, 0x41, 0xd1, 0x03,
0xa4, 0xb9, 0x58, 0x53, 0xba, 0x80, 0x5c, 0xac,
0x44, 0x26, 0xe2, 0xa7, 0xbf, 0x4f, 0xd9, 0x52,
0xed, 0x36, 0xbc, 0xc3, 0xed, 0x39, 0x60, 0xc6,
0x5d, 0x19, 0x4a, 0x4f, 0xea, 0x5b, 0x94, 0xee,
0x8c, 0x63, 0x96, 0x61, 0x0e, 0xfd, 0x09, 0x7a,
0xdb, 0xc1, 0x9c, 0x31, 0xc2, 0x64, 0xac, 0xbe,
0xc6, 0x5a, 0x6b, 0x14, 0x60, 0x99, 0xd1, 0x39,
0xda, 0xfc, 0x70, 0x2c, 0x96, 0x49, 0x5d, 0xb9,
0xf1, 0xa4, 0x72, 0xcf, 0x4c, 0xa7, 0x7b, 0x4a,
0xaa, 0x09, 0xf0, 0x36, 0xef, 0x6b, 0x7a, 0x76,
0xe5, 0x8a, 0x69, 0x33, 0xb0, 0x34, 0x67, 0x61,
0x85, 0xc9, 0xf9, 0x6e, 0x71, 0x84, 0xc5, 0x9b,
0x1a, 0xdf, 0x56, 0x6d, 0x8a, 0xde, 0x25, 0x2c,
0x6e, 0xcb, 0x94, 0x47, 0x86, 0x7c, 0x9d, 0x1e,
0x40, 0xf3, 0xa1, 0x6b, 0xbc, 0x61, 0x68, 0x39,
0x2e, 0x70, 0x4f, 0x65, 0x62, 0xe4, 0xba, 0xb6,
0xf8, 0x69, 0x9b, 0x12, 0xd9, 0x88, 0xea, 0x02,
0x42, 0x32, 0xa5, 0x51, 0x1e, 0x7c, 0x75, 0xe9,
0xf2, 0xa6, 0x10, 0x87, 0x4e, 0xa3, 0x9a, 0xba,
0x8f, 0xc7, 0x9f, 0x30, 0xd8, 0x8c, 0x22, 0x14,
0xac, 0x15, 0x02, 0xd1, 0xf5, 0x28, 0xf1, 0xf7,
0x34, 0x76, 0x89, 0x02, 0xd5, 0x71, 0x41, 0xbf,
0x22, 0x13, 0xb6, 0x2d, 0xa9, 0x55, 0xf8, 0x5d,
0x86, 0xf1, 0x80, 0xae, 0xa1, 0xa0, 0x82, 0xaf,
0x89, 0x67, 0xcc, 0xf7, 0xc3, 0x5b, 0x67, 0x7c,
0x7a, 0x53, 0xa7, 0x8a, 0xcd, 0x21, 0x75, 0x07,
0x1f, 0xa5, 0xbd, 0x0a, 0x0a, 0xcc, 0xc0, 0x6b,
0x22, 0xc7, 0x53, 0xbc, 0xbf, 0x7e, 0xaf, 0x89,
0x52, 0x72, 0x11, 0xd1, 0x59, 0x8b, 0x6d, 0xbd,
0xd5, 0x01, 0xeb, 0x75, 0x5b, 0x37, 0x03, 0x43,
0x3f, 0x84, 0x8d, 0x54, 0x18, 0x53, 0x22, 0x4c,
0x85, 0xfc, 0x2b, 0x70, 0x4e, 0xd9, 0x78, 0xcd,
0xb0, 0xa1, 0x16, 0x0f, 0x08, 0xbd, 0x65, 0xd0,
0x92, 0x61, 0x62, 0x69, 0x1e, 0xbb, 0xf0, 0xa5,
0x7a, 0x9c, 0x1b, 0x7a, 0x68, 0xa9, 0xe8, 0x0a,
0x17, 0x9d, 0x89, 0x3f, 0x48, 0x25, 0xd6, 0xe7,
0xb8, 0xb9, 0x79, 0x2f, 0x53, 0x42, 0x12, 0xf4,
0xc6, 0x83, 0x8d, 0x25, 0xf1, 0x43, 0x9d, 0x33,
0x94, 0x99, 0xde, 0x49, 0x21, 0x93, 0xfc, 0x21,
0xf0, 0x49, 0x5d, 0x0e, 0x2f, 0x76, 0xaf, 0x18,
0xa3, 0xd1, 0x70, 0xdb, 0x9c, 0x35, 0x5c, 0x87,
0x42, 0x76, 0x80, 0x4e, 0xd2, 0x8d, 0x71, 0x98,
0x78, 0xeb, 0x7d, 0xfa, 0x39, 0x83, 0xd2, 0x4e,
0xfe, 0xde, 0xc4, 0x8b, 0xef, 0x5f, 0xce, 0xf0,
0x80, 0xdf, 0x18, 0x3c, 0xe2, 0xb7, 0xdc, 0xb0,
0xf1, 0xc5, 0x42, 0xa7, 0x2c, 0x84, 0x9e, 0x4c,
0xdd, 0x8c, 0x9c, 0x4a, 0xda, 0xf1, 0xcf, 0x18,
0xc1, 0xb6, 0x6d, 0x40, 0x57, 0x3e, 0x26, 0x44,
0xc7, 0xe7, 0xda, 0x9c, 0x0e, 0x3d, 0x80, 0x05,
0xf8, 0x07, 0x5f, 0xfc, 0x72, 0x9b, 0x50, 0xe5,
0x79, 0xaa, 0xf3, 0xd0, 0x7a, 0x0e, 0xb2, 0xd8,
0xb5, 0x82, 0x5a, 0x04, 0x00, 0x8c, 0xd4, 0xb2,
0x51, 0xc0, 0xb8, 0xec, 0xa5, 0x90, 0x21, 0xc3,
0x1e, 0x17, 0x9b, 0x19, 0x26, 0xe9, 0x2a, 0x21,
0x75, 0xe3, 0xa6, 0xd7, 0xd0, 0x5c, 0xb6, 0x36,
0x8f, 0x51, 0x45, 0xe4, 0x85, 0x5f, 0xbf, 0xee,
0xc4, 0x13, 0x38, 0xf0, 0x89, 0x1d, 0x61, 0xfa,
0x01, 0x9e, 0xa6, 0xda, 0xd4, 0x7b, 0xa5, 0xa3,
0x1a, 0x44, 0x1e, 0xa7, 0xca, 0x14, 0xb1, 0xc2,
0xd0, 0x35, 0x03, 0xca, 0xf8, 0x18, 0x04, 0x24,
0xae, 0xb1, 0xc2, 0xc2, 0x98, 0x3a, 0xd6, 0xdf,
0xfb, 0x3c, 0x0d, 0x72, 0xdb, 0x85, 0x81, 0x4c,
0x6f, 0xe5, 0x91, 0x20, 0xa1, 0x99, 0xb7, 0x07,
0xde, 0x7c, 0x37, 0x0a, 0x18, 0x1d, 0x90, 0xa7,
0x88, 0x7b, 0x15, 0xdc, 0x77, 0x86, 0xb2, 0xd9,
0x90, 0xe9, 0x5c, 0x58, 0x51, 0x33, 0x06, 0x95,
0xad, 0xbf, 0xdf, 0xc7, 0x4d, 0xcb, 0xec, 0x9f,
0x6d, 0x00, 0xfa, 0x8f, 0x38, 0x4c, 0x56, 0x7e,
0x1a, 0x09, 0x16, 0xd6, 0x2d, 0x4d, 0x50, 0xf5,
0x54, 0x12, 0x8c, 0x64, 0x25, 0x07, 0xa7, 0xe2,
0xeb, 0x48, 0xbd, 0x50, 0x84, 0x8e, 0x90, 0xb6,
0x43, 0x00, 0x87, 0x63, 0x78, 0x73, 0xd1, 0xd5,
0xf1, 0x80, 0xd8, 0x44, 0xbe, 0x8e, 0x45, 0xd6,
0xec, 0xbc, 0xc5, 0xab, 0x97, 0x69, 0x38, 0xaa,
0x23, 0x63, 0x76, 0xaa, 0x13, 0x7d, 0xa3, 0x82,
0x83, 0x81, 0xdf, 0x53, 0x2e, 0x04, 0x69, 0x0f,
0x6f, 0x41, 0x1d, 0x46, 0x96, 0x4d, 0x5b, 0x27,
0xc9, 0x7b, 0x56, 0x8d, 0x86, 0x46, 0xd5, 0x74,
0xaa, 0x16, 0x2d, 0x6d, 0x1a, 0xf6, 0xcf, 0x57,
0x7c, 0xca, 0x3a, 0x98, 0x70, 0x61, 0xa5, 0x74,
0x6b, 0x06, 0x44, 0x96, 0xcf, 0x46, 0x20, 0x9a,
0x39, 0xcb, 0xf0, 0x84, 0x50, 0x93, 0xf0, 0xce,
0x64, 0xe3, 0xaf, 0xdc, 0x1b, 0x21, 0x5f, 0xce,
0xed, 0xb6, 0x85, 0xd4, 0x5c, 0x52, 0x71, 0x8c,
0x05, 0xe0, 0x14, 0x76, 0xa1, 0x6e, 0xdc, 0x63,
0x1c, 0xf7, 0xc1, 0x38, 0x29, 0xf3, 0x3e, 0xd2,
0xb1, 0xb4, 0xc7, 0xd5, 0x8f, 0x63, 0xbc, 0x25,
0xe2, 0x59, 0xb8, 0xf1, 0x51, 0x10, 0x3b, 0xec,
0x49, 0x3a, 0xfc, 0x4a, 0x29, 0x7e, 0x1d, 0xa4,
0xc4, 0xa3, 0xc1, 0x51, 0x90, 0x0e, 0x10, 0x94,
0x1b, 0x60, 0xdd, 0xd0, 0x89, 0xf9, 0x76, 0xa6,
0x1a, 0x7b, 0xba, 0x90, 0x85, 0x35, 0xea, 0xf9,
0xca, 0x53, 0xd5, 0xa1, 0x87, 0x95, 0x52, 0xc2,
0xc2, 0xa8, 0xc8, 0xb8, 0xe7, 0x05, 0xbf, 0x19,
0xb0, 0x46, 0xe8, 0x44, 0x77, 0x80, 0x8f, 0xe0,
0xee, 0xfd, 0x5b, 0xe2, 0x74, 0xed, 0x32, 0xab,
0x0b, 0x54, 0xa7, 0x48, 0x8e, 0xc6, 0xa0, 0x09,
0xf1, 0x62, 0x1b, 0xd1, 0x30, 0xa1, 0x9b, 0x3e,
0x3d, 0x4b, 0xd0, 0x34, 0xb7, 0x7f, 0x51, 0x83,
0x14, 0xa7, 0x36, 0xdd, 0xbc, 0x24, 0x74, 0x8d,
0x92, 0xd6, 0x3b, 0x99, 0xec, 0x71, 0x59, 0xa5,
0xa7, 0x72, 0x05, 0x83, 0x83, 0xb8, 0x88, 0x33,
0xba, 0x7c, 0x51, 0x2c, 0x4f, 0x20, 0x33, 0xff,
0x6a, 0x5e, 0x24, 0x9d, 0x93, 0x66, 0xc2, 0x0e,
0x72, 0x5f, 0xdb, 0x50, 0x32, 0x00, 0x84, 0x9f,
0x96, 0x86, 0xa7, 0x71, 0x62, 0x55, 0x78, 0x36,
0x56, 0x2d, 0x94, 0x48, 0x46, 0xc2, 0x76, 0xaf,
0x4b, 0x2a, 0x0a, 0xb6, 0x18, 0x0e, 0xf6, 0xa6,
0xa8, 0xb2, 0x94, 0x9a, 0x39, 0xfd, 0xfa, 0x9a,
0x6a, 0x19, 0x83, 0x1e, 0x78, 0x85, 0x59, 0x6b,
0xdf, 0xf4, 0x93, 0x44, 0x2e, 0x01, 0x61, 0xe9,
0x98, 0xa6, 0x28, 0xc9, 0x66, 0x9e, 0x1d, 0xb2,
0xe2, 0x44, 0x16, 0xdc, 0x86, 0xca, 0xf0, 0x03,
0x2e, 0xd1, 0x5d, 0x06, 0x30, 0xa3, 0x27, 0xc2,
0x84, 0x42, 0x70, 0x25, 0x0f, 0xd2, 0x4e, 0x02,
0x90, 0x88, 0xe6, 0x90, 0x83, 0xac, 0x42, 0x00,
0x61, 0x05, 0x1e, 0x46, 0xfa, 0xae, 0x91, 0xd9,
0xe8, 0xa3, 0x28, 0xfb, 0x7c, 0xd6, 0x38, 0x77,
0x9c, 0xfc, 0xbd, 0xb4, 0x74, 0x07, 0x7c, 0x60,
0xa5, 0xf2, 0xe8, 0xc7, 0x83, 0xfa, 0x0f, 0x47,
0xf8, 0x63, 0xe7, 0x3e, 0x95, 0x34, 0x16, 0xce,
0x24, 0x93, 0x0e, 0xd4, 0x14, 0xe7, 0x01, 0x48,
0xeb, 0x7d, 0xfe, 0x6f, 0x20, 0xcd, 0x42, 0x79,
0xb4, 0x0b, 0xa0, 0x6e, 0xe7, 0x5b, 0x68, 0xba,
0x21, 0x56, 0x65, 0x3a, 0x51, 0xa2, 0xec, 0x3b,
0xb1, 0xec, 0x61, 0xf8, 0x70, 0x65, 0x5c, 0x9b,
0xf6, 0xd4, 0xb1, 0xe0, 0xd4, 0x73, 0x92, 0x54,
0x6f, 0x6f, 0xf8, 0x17, 0x24, 0x10, 0x82, 0xba,
0x2e, 0x95, 0xbd, 0x69, 0x9f, 0xb3, 0xb0, 0xf0,
0x57, 0x15, 0x8c, 0x2f, 0x44, 0x4e, 0x83, 0xc9,
0xf3, 0xa1, 0xc9, 0x39, 0xe8, 0x3c, 0xb0, 0xa7,
0x51, 0x69, 0xce, 0x4b, 0xb2, 0x70, 0x3e, 0x8e,
0xcf, 0x3e, 0x3a, 0x95, 0x5e, 0x18, 0x43, 0xc9,
0xde, 0x4e, 0x47, 0xbb, 0x6e, 0x0c, 0x83, 0x3b,
0xaf, 0x58, 0x67, 0x06, 0xd6, 0x52, 0xd5, 0x89,
0xb7, 0x1c, 0xb9, 0xd9, 0xa3, 0x95, 0x81, 0x92,
0x8b, 0x32, 0x43, 0xb9, 0xf8, 0x99, 0x2e, 0x70,
0xc9, 0x1e, 0x9a, 0x3a, 0xaa, 0x97, 0xd8, 0xcc,
0x2f, 0xd2, 0x69, 0xdc, 0x69, 0xab, 0x63, 0xc0,
0x5f, 0xd5, 0xb6, 0xb8, 0x8b, 0x8d, 0x6c, 0x15,
0x56, 0x0a, 0xe6, 0x92, 0xb5, 0x25, 0x4b, 0x24,
0x1c, 0x63, 0x5f, 0x0c, 0x1d, 0x36, 0x6e, 0x7a,
0xc0, 0x5b, 0xdb, 0xa1, 0xf8, 0x16, 0x29, 0x04,
0x2f, 0x2b, 0xb8, 0x11, 0xf9, 0xef, 0x1a, 0x50,
0x0c, 0x97, 0x19, 0x20, 0xbc, 0xe9, 0x40, 0xd1,
0x0b, 0x74, 0xec, 0xa0, 0xd5, 0x18, 0x6b, 0xc8,
0x6e, 0xb1, 0x65, 0xd7, 0x5f, 0xf3, 0x7c, 0x33,
0x89, 0xca, 0x15, 0xd1, 0xa8, 0x7f, 0x73, 0xe0,
0xa2, 0x72, 0x27, 0x6d, 0x79, 0xa5, 0xec, 0x36,
0x4e, 0x47, 0xd1, 0x52, 0xe4, 0x0f, 0x3b, 0x9a,
0xb5, 0xef, 0x97, 0x0f, 0xc5, 0x9c, 0x7a, 0x51,
0xbe, 0x23, 0x0f, 0x15, 0x87, 0xd0, 0xa5, 0xf6,
0x12, 0x81, 0xdd, 0x44, 0xd9, 0xf4, 0xcc, 0xda,
0x61, 0x5e, 0x66, 0xa4, 0xf1, 0x7c, 0xd7, 0xd3,
0xac, 0xf0, 0x57, 0xd0, 0x53, 0xeb, 0x19, 0xbd,
0x9d, 0xb4, 0xcb, 0x9e, 0x61, 0x1e, 0xe2, 0x0e,
0xdb, 0x6d, 0x40, 0xaa, 0xe8, 0xc8, 0x91, 0xec,
0xca, 0xb0, 0x0f, 0xf1, 0x41, 0x71, 0x43, 0x25,
0x71, 0xf5, 0xab, 0x93, 0x03, 0xa7, 0x64, 0xdb,
0xb4, 0xde, 0x11, 0x4f, 0x08, 0xe9, 0xb2, 0x6d
}};
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/

273
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c
View File

@@ -1,273 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 Microcode patch.
*
* Fam14 Microcode Patch rev 0500001A for 5001 or equivalent.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x14
* @e \$Revision: 37850 $ @e \$Date: 2010-09-13 18:09:57 -0400 (Mon, 13 Sep 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuEarlyInit.h"
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
// Patch code 0500001A for 5001 and equivalent
CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500001A =
{{
0x10, 0x20, 0x08, 0x09, 0x1a, 0x00, 0x00, 0x05,
0x01, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x01, 0x50, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa,
0x66, 0xb4, 0x7f, 0x31, 0x85, 0x36, 0x47, 0xfa,
0xa2, 0x3e, 0x1c, 0xb4, 0x9d, 0xaa, 0x69, 0x39,
0xc4, 0xc0, 0xc6, 0xa7, 0xaf, 0x4a, 0x48, 0xe1,
0xe4, 0xbe, 0x8a, 0x91, 0x15, 0xfd, 0x1f, 0x89,
0xd9, 0x17, 0x1e, 0xe0, 0xe5, 0x8d, 0xd1, 0x77,
0xe1, 0xd6, 0xbc, 0x7b, 0x85, 0x18, 0x61, 0xc0,
0x94, 0xb7, 0x36, 0x07, 0x19, 0x64, 0x8f, 0x10,
0xda, 0x1e, 0xf1, 0xf3, 0xe4, 0xe9, 0xc6, 0xbd,
0x05, 0xe5, 0xb2, 0x5c, 0x8a, 0xdb, 0x35, 0x84,
0x68, 0x07, 0x15, 0xa1, 0xca, 0xcc, 0x41, 0x3a,
0xef, 0x18, 0x02, 0x72, 0x71, 0xff, 0x65, 0x6e,
0x3c, 0x2d, 0x2a, 0xe8, 0x26, 0x00, 0xe1, 0xf8,
0x8b, 0x4c, 0xe2, 0xbd, 0x1b, 0xc0, 0x83, 0x11,
0xc5, 0x38, 0x65, 0x4d, 0x65, 0xb7, 0x9d, 0x1f,
0x5b, 0x46, 0x96, 0x6c, 0x7b, 0xc1, 0x03, 0x59,
0x1d, 0x0f, 0x6b, 0x0b, 0x2c, 0xfc, 0x96, 0x3f,
0xf8, 0xc5, 0x76, 0xaf, 0x08, 0xb0, 0x60, 0xc8,
0xaa, 0x66, 0x99, 0x1f, 0xb1, 0x67, 0x85, 0x2b,
0x03, 0x06, 0x50, 0x7c, 0x22, 0x7c, 0xa7, 0xb4,
0x04, 0x58, 0xcc, 0xdf, 0xf1, 0xdc, 0x94, 0x84,
0x84, 0x06, 0xf7, 0x17, 0xc9, 0x02, 0x75, 0xd6,
0x03, 0xd3, 0x20, 0x8c, 0x23, 0x5e, 0xfb, 0x76,
0xf3, 0x74, 0x6b, 0x4d, 0x16, 0x1a, 0x66, 0xb6,
0xfa, 0x30, 0x5f, 0xea, 0x82, 0xf1, 0x5b, 0x9d,
0xb0, 0xd2, 0xd6, 0x2c, 0xa7, 0x5f, 0xb0, 0x4b,
0xfa, 0x27, 0xff, 0xd5, 0x7b, 0xfa, 0x8d, 0x18,
0xab, 0x96, 0xfc, 0x42, 0xc4, 0x5b, 0x85, 0xbc,
0x9b, 0xf5, 0x4b, 0x59, 0x0d, 0xc7, 0x88, 0xfc,
0xc0, 0x6e, 0xac, 0xe5, 0xe2, 0xa3, 0x14, 0x44,
0xf8, 0xb2, 0x8a, 0xe9, 0x9d, 0x75, 0xe2, 0xdc,
0xf1, 0x3b, 0x18, 0xe9, 0x17, 0x9a, 0x59, 0x55,
0x28, 0xf3, 0x84, 0xcc, 0xf2, 0x08, 0x6e, 0xe0,
0x94, 0xd9, 0x88, 0x3d, 0x3a, 0xf0, 0xa2, 0xdb,
0xa2, 0x58, 0xbe, 0x7c, 0x6e, 0x26, 0xd6, 0x2d,
0xba, 0x09, 0xba, 0xf8, 0xba, 0x28, 0xf9, 0xff,
0x71, 0xd3, 0xb4, 0xd7, 0x31, 0x31, 0xd4, 0x8d,
0xcc, 0x44, 0xcc, 0xb8, 0xed, 0xc7, 0x83, 0x97,
0x04, 0x88, 0x05, 0xb8, 0x5b, 0x27, 0x6b, 0xef,
0xe4, 0x5d, 0x03, 0xac, 0x95, 0x05, 0x17, 0x79,
0x0b, 0xe9, 0xbe, 0xaf, 0x25, 0x4a, 0x3b, 0xf2,
0x09, 0xd9, 0x83, 0x17, 0x4f, 0x95, 0x11, 0x17,
0xf5, 0xa4, 0xa6, 0x3e, 0xb8, 0x71, 0x9e, 0x38,
0x86, 0xc8, 0x97, 0x7b, 0x19, 0xab, 0xd5, 0xec,
0xc3, 0x99, 0xe2, 0x95, 0x97, 0xbd, 0x93, 0xd0,
0x1b, 0x76, 0xc4, 0x86, 0x14, 0x58, 0xbf, 0x0b,
0x14, 0x9d, 0x04, 0x64, 0xa8, 0xa6, 0xaf, 0x69,
0x3b, 0xe7, 0x37, 0xed, 0x19, 0xaf, 0x28, 0x2b,
0xff, 0x36, 0xbd, 0x72, 0xf1, 0x2b, 0x06, 0x7f,
0xe9, 0xae, 0x5e, 0xa0, 0xe3, 0x0d, 0x1e, 0x64,
0x06, 0xa8, 0x24, 0x99, 0x2e, 0x7a, 0x41, 0x94,
0x77, 0x4a, 0x17, 0x93, 0x04, 0xd6, 0x2e, 0x86,
0x7a, 0x24, 0x05, 0x87, 0x18, 0x17, 0xb6, 0xe8,
0x41, 0xc2, 0x33, 0xec, 0xb6, 0x42, 0xb2, 0x08,
0xe5, 0xf2, 0x12, 0x15, 0x6b, 0xc9, 0x55, 0xd4,
0xce, 0xa4, 0x4e, 0xa5, 0x2f, 0xd2, 0x3b, 0xd1,
0x08, 0x61, 0x9f, 0xe4, 0x92, 0x1a, 0x84, 0x62,
0x73, 0x7d, 0x87, 0xb2, 0x4b, 0x3d, 0x07, 0x1c,
0xad, 0x13, 0x9f, 0xd6, 0xa5, 0x80, 0x90, 0x95,
0x09, 0xf0, 0x45, 0x04, 0x13, 0xd0, 0x06, 0xc2,
0x24, 0xd4, 0x0b, 0x39, 0xe7, 0x7b, 0xd7, 0xda,
0x7b, 0x88, 0xe7, 0xcf, 0x53, 0xac, 0x38, 0x11,
0x2e, 0x01, 0x94, 0x69, 0x5a, 0x04, 0xb4, 0xf5,
0x1f, 0x7c, 0x44, 0x7a, 0x3e, 0x73, 0x8c, 0x38,
0xcf, 0xf2, 0xd3, 0xf6, 0x3f, 0x5a, 0x76, 0xd3,
0x5b, 0x2e, 0x9f, 0xb3, 0xe7, 0x93, 0x11, 0x05,
0x55, 0x14, 0x8d, 0xc1, 0x6e, 0x36, 0x6e, 0xa3,
0xa0, 0x0b, 0xe1, 0x48, 0x7f, 0x48, 0x80, 0x21,
0x59, 0x00, 0x86, 0xd9, 0x1a, 0x99, 0x9e, 0xf6,
0x4d, 0xa0, 0xd7, 0xbe, 0xb0, 0x2b, 0x13, 0x5d,
0x5b, 0xf3, 0x01, 0x7d, 0xbc, 0x46, 0x99, 0xd9,
0xb4, 0xdb, 0xc8, 0xd1, 0x21, 0x94, 0x91, 0xdc,
0x7a, 0x85, 0xaf, 0x74, 0x9e, 0x0b, 0x18, 0x05,
0xfd, 0xba, 0xac, 0x7a, 0xea, 0xa9, 0x6e, 0x07,
0x32, 0xf8, 0x1d, 0x0d, 0x7b, 0x18, 0x6f, 0x13,
0x89, 0x4c, 0xb3, 0x50, 0x5d, 0x8c, 0x81, 0xd5,
0x2a, 0x6f, 0xf3, 0xa4, 0x93, 0x7c, 0x16, 0xfd,
0x25, 0xf8, 0x83, 0xc7, 0xd0, 0x21, 0xf9, 0x51,
0xc5, 0xbb, 0x6a, 0x42, 0xe6, 0xfd, 0x05, 0x7e,
0xa0, 0x37, 0x93, 0x55, 0x98, 0x8b, 0x30, 0xbd,
0x62, 0x33, 0x91, 0xe3, 0x44, 0xd6, 0xc5, 0xa4,
0x17, 0x2d, 0x70, 0x97, 0xaa, 0x02, 0xc3, 0xa4,
0x09, 0x6f, 0x7f, 0x00, 0xcf, 0xae, 0x5f, 0x25,
0xf5, 0x5e, 0xca, 0x7b, 0x7c, 0x61, 0x07, 0x1c,
0xd9, 0x49, 0xa5, 0x9d, 0x42, 0xe4, 0x74, 0x93,
0xe1, 0x3f, 0x8f, 0xc0, 0xa1, 0x32, 0x1a, 0x83,
0x06, 0x3a, 0x1b, 0xb2, 0x25, 0x69, 0xec, 0x20,
0xd5, 0x9b, 0x7a, 0x9f, 0x34, 0xb0, 0x27, 0x23,
0x20, 0xa0, 0x31, 0xc1, 0x24, 0xd2, 0x8e, 0x34,
0x1f, 0x7c, 0xd8, 0xc7, 0x75, 0xb1, 0x4c, 0xe8,
0x87, 0x98, 0xe1, 0xbb, 0x94, 0x55, 0xc3, 0x63,
0x25, 0x1a, 0xc8, 0xae, 0x0b, 0xf4, 0xd9, 0xb9,
0xe3, 0xdc, 0x5e, 0x9a, 0xb1, 0x98, 0x89, 0x4c,
0x2a, 0x09, 0x0e, 0xfa, 0x98, 0x21, 0x87, 0xf3,
0x58, 0xe0, 0xa9, 0x8a, 0xda, 0xf5, 0xc7, 0x0b,
0x70, 0xa5, 0x69, 0x0c, 0xe5, 0x38, 0x98, 0x22,
0xac, 0x05, 0xe4, 0x45, 0x56, 0x77, 0xa5, 0xfe,
0x34, 0x5b, 0xb9, 0x45, 0x58, 0x1d, 0x95, 0xd2,
0x62, 0x60, 0x86, 0x88, 0x19, 0x03, 0x2c, 0xee,
0xd6, 0xc4, 0x32, 0x41, 0x5d, 0xa5, 0x0b, 0x71,
0xfb, 0x8c, 0x6c, 0xb0, 0xdc, 0x61, 0x67, 0x3d,
0xfb, 0xb1, 0xec, 0xf1, 0x95, 0xfc, 0x5d, 0x18,
0x93, 0x76, 0xca, 0x55, 0x2c, 0xdc, 0x8c, 0x87,
0xf1, 0x00, 0x84, 0xa6, 0x55, 0x91, 0xab, 0xf9,
0x24, 0xa5, 0x27, 0x55, 0xfb, 0xd4, 0xb4, 0xfd,
0xac, 0xc9, 0xfe, 0xdb, 0xeb, 0xcc, 0x6f, 0xd4,
0x92, 0x8a, 0xa9, 0x26, 0x07, 0xfb, 0x4f, 0x53,
0x3d, 0x89, 0xa8, 0x4c, 0x94, 0x7a, 0xce, 0xec,
0xd5, 0x4b, 0xef, 0x65, 0xab, 0x65, 0xc0, 0x3b,
0x28, 0xfe, 0xfb, 0xc9, 0x83, 0x6b, 0xbc, 0x72,
0x42, 0xf7, 0x78, 0x92, 0x87, 0x76, 0xbe, 0x0c,
0x42, 0x42, 0x96, 0x18, 0x03, 0x69, 0x16, 0x67,
0xc6, 0xe7, 0x75, 0xee, 0xb6, 0x1b, 0x85, 0x46,
0xb4, 0x65, 0x0a, 0x61, 0xbb, 0xb9, 0xb3, 0x37,
0xf8, 0x35, 0x98, 0x38, 0x5d, 0x93, 0x3d, 0x99,
0x84, 0x40, 0x9d, 0x66, 0x3e, 0x3b, 0xd0, 0x01,
0x8a, 0x67, 0x83, 0xce, 0x26, 0x48, 0x76, 0x93,
0x70, 0xa7, 0xfe, 0x13, 0xee, 0x5a, 0x30, 0x2c,
0xcc, 0xba, 0xa9, 0xe8, 0x76, 0x88, 0xa7, 0x8e,
0x78, 0x22, 0xdf, 0xec, 0xc2, 0x68, 0xcf, 0xf4,
0x29, 0x6d, 0x19, 0x6e, 0x4d, 0xad, 0x35, 0xee,
0x07, 0xb5, 0xcf, 0x20, 0x80, 0x77, 0xf9, 0xb7,
0x45, 0x78, 0x63, 0x3a, 0x39, 0x7b, 0x44, 0xec,
0x82, 0x0e, 0x8f, 0xf2, 0x03, 0xa8, 0xaf, 0x83,
0x3d, 0x3a, 0xc5, 0x54, 0xfe, 0xc0, 0xf5, 0xf4,
0x98, 0xf4, 0x8d, 0x96, 0x2a, 0x62, 0xd2, 0xbc,
0x56, 0x3c, 0xfe, 0x7d, 0x46, 0x7f, 0x21, 0x92,
0x8d, 0x57, 0x15, 0x3f, 0xff, 0xc7, 0xe4, 0x24,
0x71, 0x36, 0xe3, 0x25, 0x7d, 0xb3, 0xf7, 0xd1,
0x18, 0xf5, 0x3e, 0x0e, 0xb3, 0xa3, 0xd8, 0x60,
0xda, 0xa6, 0x72, 0xc6, 0x84, 0x09, 0x2b, 0xfe,
0x74, 0x0d, 0x7b, 0x71, 0x40, 0x74, 0x99, 0x2a,
0xe9, 0xc4, 0x3e, 0x1f, 0xab, 0x22, 0x21, 0x97,
0xab, 0x93, 0x4a, 0x72, 0x3b, 0x15, 0xd8, 0xc3,
0x68, 0x3f, 0xd0, 0x7f, 0x21, 0x48, 0x6e, 0xf2,
0x68, 0x41, 0x16, 0x49, 0x6a, 0x4c, 0xdd, 0xe0,
0x44, 0xd6, 0x04, 0xc1, 0xc5, 0x4a, 0x3e, 0x06,
0x2c, 0x6d, 0x30, 0x76, 0x71, 0x33, 0xde, 0x73,
0x44, 0x96, 0x05, 0xaa, 0x3d, 0x31, 0x55, 0xf7,
0xdb, 0x17, 0x5f, 0xa1, 0xd0, 0x36, 0x9f, 0xaa,
0x95, 0x82, 0x46, 0x79, 0x78, 0x77, 0xaf, 0x04,
0x78, 0x7d, 0xe8, 0x8a, 0x5c, 0x69, 0xe2, 0x88,
0xce, 0xca, 0x21, 0x18, 0x0d, 0x1b, 0xe7, 0x3c,
0x14, 0xec, 0x8b, 0xc6, 0x55, 0x30, 0xf1, 0x40,
0x7f, 0x4e, 0x1d, 0xda, 0x86, 0x81, 0x05, 0x72,
0x3a, 0x99, 0xad, 0x78, 0xfc, 0x96, 0xcc, 0x0e,
0x81, 0x0c, 0xed, 0xce, 0x69, 0x14, 0x15, 0xc9,
0xdd, 0xb5, 0xf7, 0xde, 0xf5, 0x9c, 0xc7, 0xc1,
0xb9, 0x09, 0x8e, 0xf7, 0xd9, 0xf2, 0x05, 0x02,
0x36, 0xe9, 0x8d, 0xb4, 0x51, 0x23, 0x78, 0xc2,
0x2a, 0x2f, 0x27, 0x2e, 0x2e, 0xa1, 0x9f, 0xda,
0xb1, 0x0d, 0xc0, 0x97, 0x18, 0x65, 0x4e, 0x87,
0xa6, 0x95, 0xa7, 0xdc, 0x91, 0xfd, 0x10, 0xee,
0x32, 0x36, 0x23, 0xad, 0x79, 0x66, 0x68, 0x16,
0x6a, 0x7a, 0x91, 0xe9, 0xb6, 0xd0, 0xf7, 0x38,
0xc0, 0xa2, 0xca, 0xd4, 0xc0, 0xcd, 0x4a, 0x68,
0x01, 0x07, 0x8e, 0x8d, 0x82, 0x85, 0xd1, 0x88,
0x8c, 0x7b, 0xdf, 0x90, 0x9b, 0x28, 0x00, 0xaa,
0x4d, 0x14, 0x2f, 0x65, 0xd6, 0x90, 0x7a, 0xe0,
0x10, 0xed, 0xf0, 0x04, 0x80, 0xff, 0x52, 0xb5,
0xb3, 0x66, 0xae, 0xb2, 0x4c, 0xe0, 0x4f, 0x69,
0x18, 0xa6, 0x4e, 0x1a, 0x95, 0xd2, 0xf4, 0x26,
0xba, 0x16, 0xea, 0xb6, 0x51, 0xdc, 0x3f, 0xf2,
0x29, 0xf8, 0x5b, 0x1a, 0x6e, 0x0a, 0x21, 0xa2,
0x34, 0x40, 0x8a, 0x58, 0x10, 0xb7, 0xaa, 0xe5,
0x4b, 0xa9, 0x7a, 0x7c, 0x32, 0x10, 0xdd, 0x74,
0x32, 0xca, 0x21, 0xfb, 0x92, 0x88, 0x22, 0x29,
0xdd, 0x51, 0xe9, 0xcc, 0xcb, 0x66, 0x5f, 0xca,
0x4a, 0x9d, 0xd6, 0x55, 0x0a, 0x5d, 0xe9, 0x6c,
0x37, 0xba, 0x75, 0x18, 0x7c, 0x00, 0x4a, 0x78,
0x58, 0x1f, 0xec, 0x47, 0x75, 0x74, 0x21, 0x13,
0x69, 0x66, 0x44, 0xe8, 0x00, 0x6f, 0x7d, 0xb9,
0x31, 0xc8, 0xb1, 0xdc, 0xc2, 0x62, 0x52, 0xf1,
0x20, 0x1d, 0xeb, 0x88, 0x18, 0x65, 0x13, 0x8f,
0x78, 0xba, 0x5a, 0xb9, 0x2b, 0x6c, 0x80, 0xe0,
0xa7, 0x5f, 0xb9, 0xec, 0x1b, 0x86, 0x06, 0x8a,
0xbf, 0x71, 0x44, 0x4f, 0x41, 0x73, 0x32, 0x59,
0x01, 0x33, 0x54, 0xac, 0x5e, 0xac, 0xc2, 0x0a,
0xa4, 0xd5, 0xc3, 0x54, 0x05, 0xbf, 0x44, 0xdc,
0x72, 0x3d, 0xc8, 0x44, 0x6c, 0x80, 0x1f, 0x69,
0x16, 0x85, 0x65, 0xbc, 0xa1, 0x99, 0x50, 0xd9,
0x39, 0xa7, 0x7c, 0xac, 0xf1, 0x0c, 0xd7, 0xdc,
0xe7, 0x2a, 0xe4, 0xf2, 0xa4, 0x6f, 0xf4, 0xe2,
0xd5, 0x12, 0x36, 0x93, 0xa6, 0xfd, 0xdd, 0xde,
0x4c, 0x07, 0x11, 0x43, 0x25, 0x31, 0xa7, 0x54,
0x81, 0x28, 0x27, 0x41, 0x70, 0xd9, 0xb9, 0x4e,
0xce, 0x45, 0x40, 0xe2, 0xb8, 0xa5, 0x79, 0xf6,
0x39, 0x8e, 0xf8, 0xae, 0xfe, 0x25, 0x47, 0x8c,
0xc2, 0x1a, 0xc0, 0x58, 0x45, 0x38, 0x13, 0x3b,
0xbb, 0x1e, 0x2c, 0xdf, 0xf6, 0x62, 0xb0, 0xe0,
0x88, 0x26, 0xf1, 0xab, 0xd9, 0xa0, 0x5d, 0x69,
0x93, 0x72, 0x6c, 0x4a, 0xe0, 0xef, 0x9f, 0x21,
0xaf, 0x2b, 0x35, 0x2a, 0x27, 0x73, 0x52, 0x3b
}};
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/

260
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000029.c
View File

@@ -1,260 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 Microcode patch.
*
* Fam14 Microcode Patch rev 05000029 for 5010 or equivalent.
*
*
*/
/*
******************************************************************************
*
* Copyright (c) 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuEarlyInit.h"
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
// Encrypt Patch code 05000029 for 5010 and equivalent
CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000029 =
{{
0x13, 0x20, 0x21, 0x01, 0x29, 0x00, 0x00, 0x05,
0x01, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x10, 0x50, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA,
0x0E, 0xAB, 0x99, 0xFE, 0xC0, 0x7C, 0x83, 0x1F,
0xBB, 0x18, 0x59, 0x9E, 0xF8, 0xC1, 0xA6, 0x9E,
0x64, 0xEC, 0x53, 0x29, 0x98, 0xD7, 0x25, 0x18,
0xF1, 0x8D, 0x2D, 0xCB, 0x74, 0xED, 0x63, 0xD2,
0xEF, 0xB0, 0xD5, 0x21, 0x31, 0x4D, 0x45, 0x1B,
0xB5, 0x33, 0x72, 0xE6, 0x04, 0x32, 0x02, 0xBD,
0x98, 0xD1, 0x99, 0x03, 0xFA, 0xE3, 0xE6, 0xBC,
0xDF, 0x91, 0x65, 0x4D, 0xE0, 0xA0, 0x4E, 0x57,
0x05, 0xA7, 0x91, 0x54, 0xD8, 0x96, 0x4C, 0x01,
0x64, 0x49, 0x8A, 0x3C, 0x8A, 0xD8, 0x48, 0x04,
0x9C, 0x9E, 0x33, 0xBE, 0xE4, 0xD8, 0x23, 0x05,
0xDB, 0x42, 0x2B, 0xA8, 0x5A, 0x7B, 0x52, 0xF3,
0xF4, 0x6A, 0xD4, 0x15, 0x5D, 0x03, 0x58, 0x98,
0x10, 0x72, 0x73, 0x5B, 0x90, 0xBF, 0x40, 0x7B,
0xB9, 0x80, 0xDC, 0xC8, 0x0C, 0xFB, 0xAE, 0xE3,
0x52, 0xFA, 0x26, 0x08, 0x04, 0x13, 0x35, 0xC8,
0x9D, 0x8B, 0x10, 0xBF, 0x60, 0x6B, 0x9B, 0xC0,
0x97, 0xAF, 0x6F, 0x61, 0x1F, 0xB2, 0x62, 0xAF,
0xC0, 0x06, 0x9A, 0xC5, 0x7E, 0xC1, 0xFF, 0xE9,
0x16, 0x8D, 0xF2, 0x81, 0xA0, 0x6D, 0x39, 0x7E,
0x74, 0x86, 0x4B, 0x5B, 0xA5, 0x48, 0xE7, 0x71,
0x9F, 0x04, 0x84, 0xA1, 0xF2, 0x1E, 0x08, 0x5B,
0x15, 0xAC, 0x1E, 0x32, 0xF8, 0xDC, 0xCD, 0x15,
0x68, 0x3B, 0x06, 0xFA, 0x0A, 0x84, 0x99, 0xB1,
0x8E, 0x49, 0x69, 0x83, 0xB0, 0x93, 0xC2, 0xA9,
0x35, 0x4F, 0x80, 0x7F, 0x46, 0xC0, 0x6C, 0xA2,
0xA2, 0xBB, 0xD4, 0x6F, 0x2C, 0x32, 0x54, 0xD2,
0x91, 0xC7, 0x1E, 0x6D, 0xDF, 0xE2, 0xA2, 0xE1,
0x69, 0x17, 0xC7, 0x8D, 0x85, 0xFB, 0x72, 0x3F,
0xA8, 0x00, 0x08, 0x6A, 0xC2, 0xAC, 0x38, 0x9D,
0x0B, 0xD1, 0xAE, 0x59, 0xFB, 0xE3, 0x00, 0xC1,
0x39, 0x47, 0x73, 0x08, 0xB9, 0xA7, 0xD7, 0x1A,
0x6C, 0x37, 0x07, 0x5F, 0xE8, 0x3F, 0x72, 0xAE,
0x6D, 0x44, 0x2B, 0xE9, 0x10, 0x07, 0x97, 0x5D,
0x2C, 0xFF, 0x16, 0x60, 0xF4, 0xE8, 0x80, 0x60,
0x9F, 0x14, 0xF2, 0xED, 0x39, 0xE8, 0x60, 0xEC,
0x24, 0xEE, 0xCE, 0xC0, 0xE5, 0x5A, 0x62, 0xCF,
0x73, 0x1E, 0xDC, 0x20, 0x80, 0x7E, 0xAE, 0x3F,
0xCF, 0x7C, 0x24, 0x7F, 0xCF, 0x45, 0x4F, 0x7F,
0xFB, 0xB8, 0x1D, 0x37, 0x99, 0xCB, 0x5F, 0x79,
0xC6, 0x1E, 0xF6, 0xB2, 0x83, 0x69, 0x57, 0x1D,
0x81, 0xC7, 0xEA, 0x50, 0x58, 0x69, 0x26, 0xEC,
0xE7, 0x31, 0x3F, 0x93, 0x90, 0x71, 0xB5, 0xB4,
0x11, 0xC0, 0x19, 0x6E, 0x09, 0xA4, 0x01, 0x32,
0x8D, 0xFE, 0x4A, 0x8C, 0x6C, 0xFB, 0xDD, 0xC2,
0x06, 0x96, 0xD9, 0x5E, 0x0F, 0xD9, 0xB1, 0x6F,
0x02, 0x0D, 0x8B, 0xEB, 0xCF, 0x94, 0x0B, 0xCA,
0xEC, 0x21, 0x80, 0xFC, 0x83, 0x39, 0xA5, 0x18,
0x27, 0xF3, 0x0D, 0x93, 0x58, 0xBD, 0x57, 0xE8,
0x5D, 0xC7, 0x02, 0x4C, 0xAB, 0x79, 0x07, 0xDF,
0x94, 0x8F, 0x1C, 0x99, 0x0F, 0x29, 0x96, 0x7F,
0xDE, 0xFF, 0xC9, 0xC7, 0x15, 0xEC, 0x0E, 0x94,
0x41, 0xF2, 0xA7, 0x2A, 0xB5, 0xE2, 0x1E, 0x41,
0x05, 0x81, 0xDA, 0xFF, 0x0F, 0x1B, 0xCF, 0x61,
0x75, 0xA8, 0x54, 0x62, 0xE4, 0xE9, 0x23, 0x9B,
0x1A, 0xAE, 0x96, 0x37, 0x7C, 0x60, 0x18, 0xDE,
0x76, 0x9A, 0x13, 0x8F, 0x0D, 0x67, 0xE7, 0x1B,
0x5C, 0x14, 0xB8, 0x93, 0x64, 0x58, 0xE0, 0xCA,
0xA8, 0x1D, 0x23, 0x67, 0x3A, 0x10, 0x1D, 0xA9,
0xA2, 0x25, 0xA7, 0xFF, 0x5C, 0x91, 0x2D, 0xA4,
0xD5, 0xE2, 0x65, 0x14, 0x58, 0xA8, 0x73, 0x76,
0x26, 0xF0, 0xE5, 0xF8, 0xDB, 0xC6, 0xDA, 0x39,
0xEE, 0xCC, 0x91, 0x57, 0x30, 0xC7, 0xE0, 0x9B,
0xBA, 0x66, 0x53, 0x78, 0x07, 0xD2, 0xC1, 0x86,
0x5B, 0xFD, 0xDA, 0x5F, 0xCF, 0x68, 0x62, 0x5D,
0x18, 0x8B, 0xD2, 0x8A, 0x8D, 0x2A, 0x39, 0xA6,
0x3D, 0x89, 0x8F, 0x65, 0x64, 0xE6, 0xD4, 0x5B,
0x4D, 0x82, 0xDD, 0x80, 0xAA, 0x10, 0x5C, 0x0B,
0x55, 0x68, 0x3D, 0x35, 0xDC, 0x0B, 0xF4, 0x18,
0xBC, 0xC8, 0x48, 0x29, 0x08, 0x7A, 0x03, 0x14,
0x32, 0xCB, 0x42, 0xCA, 0x6F, 0x1D, 0x3D, 0x53,
0x3D, 0x7F, 0xC3, 0x96, 0x16, 0x3B, 0xB7, 0x40,
0x98, 0xEE, 0xC6, 0x55, 0xC0, 0x02, 0x3E, 0xAE,
0x0D, 0x99, 0x60, 0xC6, 0xF7, 0x0A, 0x43, 0xB4,
0xF9, 0x1B, 0x5F, 0xEF, 0x6B, 0x5D, 0xED, 0x29,
0xE1, 0x70, 0xF7, 0x92, 0x11, 0x01, 0xB6, 0x56,
0xEF, 0xBD, 0x31, 0x55, 0xC1, 0xFC, 0xF8, 0xE4,
0xFC, 0x37, 0x6E, 0xE6, 0x29, 0x25, 0xB3, 0x8D,
0x50, 0x9B, 0x17, 0xE3, 0x24, 0x46, 0x2B, 0x70,
0xF0, 0xD9, 0x2C, 0x70, 0x0C, 0xA0, 0x48, 0x4A,
0x55, 0x3D, 0xB1, 0x2F, 0xEC, 0xC2, 0x0C, 0x36,
0x3B, 0x36, 0x7F, 0x1D, 0xC3, 0x4C, 0xF5, 0xB7,
0x88, 0x33, 0x40, 0x84, 0x99, 0x07, 0x84, 0x1E,
0x20, 0x09, 0x98, 0x9F, 0x4A, 0x99, 0xFE, 0x88,
0xB1, 0xE1, 0x7F, 0xED, 0xCF, 0x54, 0x4B, 0x3C,
0xBF, 0x97, 0x46, 0x39, 0x0B, 0x8C, 0xCA, 0xA7,
0xB5, 0x93, 0x5D, 0x65, 0xFF, 0x30, 0xFB, 0xDB,
0x98, 0x94, 0x99, 0xE0, 0xE0, 0xD5, 0xFA, 0xF6,
0xB3, 0xEC, 0x94, 0x5F, 0x78, 0x13, 0x5A, 0x3E,
0x21, 0x2D, 0x76, 0xBC, 0xEF, 0xED, 0x94, 0x01,
0xC5, 0x22, 0x6E, 0xD3, 0x77, 0x67, 0x81, 0xAD,
0x63, 0xB4, 0x32, 0x8D, 0x50, 0x84, 0xCE, 0xF2,
0xDD, 0xE4, 0xCF, 0xF7, 0xDF, 0x18, 0x9A, 0x03,
0x24, 0x01, 0xA6, 0x9B, 0xF6, 0x5A, 0xD0, 0x15,
0x9B, 0x80, 0x5A, 0x6E, 0x46, 0x1F, 0x60, 0x9F,
0xE6, 0x71, 0xE3, 0x58, 0xFF, 0x8D, 0x6D, 0xC6,
0x9D, 0x5E, 0x3A, 0x20, 0x08, 0x0C, 0x26, 0x18,
0x51, 0xE2, 0xF8, 0x76, 0xC8, 0xD3, 0xDC, 0x41,
0x82, 0x52, 0x7B, 0x69, 0x2A, 0x95, 0xCA, 0xD4,
0x0A, 0x99, 0x2A, 0x73, 0xDD, 0xCB, 0xAC, 0x68,
0xCF, 0xD6, 0x1B, 0x53, 0x0E, 0xA9, 0x08, 0x58,
0x95, 0x7C, 0xF7, 0xEF, 0x45, 0x1F, 0x1B, 0x61,
0x5D, 0x3D, 0xB7, 0xEB, 0x45, 0x74, 0x01, 0x0A,
0xF2, 0x1D, 0x2C, 0xBF, 0x99, 0xF5, 0x9A, 0x5D,
0x5E, 0xED, 0x4F, 0xC7, 0x79, 0x8B, 0x49, 0xEC,
0x8D, 0x8B, 0xD3, 0xF0, 0x3C, 0xF5, 0xDA, 0x8C,
0xAF, 0xAD, 0x72, 0xB7, 0x8D, 0x30, 0xDC, 0x9C,
0x3C, 0x76, 0x17, 0x8A, 0xA7, 0x02, 0xF5, 0x01,
0xBA, 0xBA, 0xF0, 0x71, 0x03, 0x6D, 0xEA, 0x13,
0x8D, 0xF1, 0x6C, 0x3E, 0xE3, 0xB3, 0x0E, 0x1B,
0x98, 0x60, 0x8A, 0xAD, 0xD8, 0x55, 0x25, 0x7F,
0xE0, 0x00, 0x58, 0x21, 0x20, 0xA4, 0x2D, 0x83,
0xAA, 0x39, 0x9A, 0x70, 0xBD, 0x9D, 0x4F, 0x6C,
0xB2, 0x21, 0x2C, 0xB7, 0x75, 0xA5, 0xA5, 0xEC,
0xB1, 0x5A, 0xFE, 0x91, 0x49, 0xD0, 0x90, 0x02,
0xBB, 0x2E, 0xC4, 0xB4, 0x73, 0x58, 0x49, 0x53,
0x31, 0xEB, 0x58, 0x66, 0xE2, 0xD2, 0x0D, 0xD2,
0x9F, 0x7D, 0x9B, 0x4D, 0xA6, 0x72, 0x2A, 0xE4,
0x04, 0xF0, 0x53, 0xF5, 0xDD, 0x8F, 0x8D, 0x0A,
0xD0, 0xD3, 0xBA, 0xAA, 0x2F, 0x2E, 0xD1, 0x7A,
0xED, 0xAD, 0x48, 0x21, 0xA7, 0x1E, 0xC9, 0x4F,
0xF2, 0xE4, 0xAF, 0x62, 0x1D, 0x91, 0xB9, 0x9D,
0xEA, 0x0F, 0x69, 0x23, 0x55, 0x99, 0xF0, 0xD2,
0x92, 0xD8, 0x20, 0xC0, 0xBC, 0x75, 0xA7, 0x83,
0x5B, 0x6F, 0x4A, 0x2F, 0xA8, 0x35, 0x2B, 0xC3,
0xBA, 0xFB, 0x9B, 0xB9, 0x11, 0xF7, 0x8E, 0xF5,
0x0E, 0x9B, 0x51, 0xB7, 0xFB, 0x59, 0x63, 0x17,
0x37, 0x5A, 0x7E, 0x20, 0xAF, 0x97, 0xAD, 0x61,
0xA0, 0xFA, 0xFC, 0x95, 0x56, 0xD9, 0x08, 0x34,
0x76, 0xEF, 0xE9, 0xA1, 0x06, 0xB5, 0xEA, 0xC5,
0xDE, 0x7F, 0xE6, 0xBC, 0x9E, 0x2A, 0x51, 0x4D,
0x9C, 0x42, 0x96, 0x3F, 0xAF, 0xA5, 0x49, 0x78,
0x9E, 0xF1, 0xFD, 0x2A, 0xD4, 0x3D, 0xA7, 0x6B,
0x9F, 0xDF, 0x37, 0x7A, 0xAB, 0x99, 0x00, 0xE2,
0xA1, 0x9C, 0xDB, 0x54, 0x8F, 0xF2, 0xBB, 0x1B,
0x7F, 0x28, 0x84, 0x20, 0x65, 0xD5, 0x2A, 0xA6,
0x0D, 0x62, 0x4F, 0x2D, 0xF0, 0xAF, 0x40, 0xFD,
0x2E, 0xB1, 0x72, 0xCD, 0x1D, 0x9A, 0xC4, 0x71,
0xFD, 0x4B, 0xB6, 0x5B, 0x13, 0xDB, 0x78, 0xDD,
0x79, 0xC6, 0x05, 0x22, 0x14, 0x98, 0xD5, 0x10,
0xC5, 0x5A, 0xBE, 0x11, 0xD6, 0xC1, 0x4B, 0x39,
0xD1, 0x88, 0x80, 0x79, 0x86, 0xDD, 0x1F, 0x54,
0x87, 0x96, 0x3E, 0xDE, 0x43, 0x25, 0xB2, 0xA6,
0x6E, 0xD0, 0xA4, 0x69, 0x67, 0x33, 0xE1, 0xD9,
0x24, 0xFB, 0x67, 0xD0, 0xC9, 0x4F, 0xB4, 0x3E,
0x48, 0x66, 0x42, 0x64, 0x42, 0xB6, 0x49, 0x99,
0x0F, 0x4D, 0xCD, 0xC8, 0x1B, 0x0E, 0x1B, 0x47,
0x8C, 0x57, 0x2A, 0x02, 0xBA, 0x43, 0x53, 0x74,
0xD8, 0x74, 0x28, 0x05, 0x03, 0x16, 0x1D, 0x73,
0x2F, 0x22, 0x0B, 0xA4, 0xFB, 0xBC, 0xE3, 0x11,
0xCA, 0xAF, 0x90, 0x1F, 0xA8, 0x67, 0xE1, 0xA1,
0x28, 0x68, 0xA5, 0x9D, 0x32, 0x85, 0xB3, 0x53,
0x5E, 0x7A, 0xF4, 0xE8, 0xB1, 0x96, 0xCF, 0xB8,
0xAA, 0x18, 0x7C, 0xEB, 0xF9, 0x33, 0x3E, 0x95,
0xF6, 0xFC, 0x9A, 0x5A, 0xAC, 0x60, 0x9F, 0xC9,
0xB8, 0x6D, 0xA2, 0x77, 0xFA, 0x64, 0xBA, 0x7B,
0xB5, 0x4D, 0x60, 0x49, 0xE3, 0x28, 0x04, 0x7C,
0xAD, 0xA1, 0xA3, 0xB6, 0x54, 0xB4, 0xAE, 0xAE,
0x0E, 0xA7, 0x83, 0x48, 0x64, 0xB0, 0x52, 0x5B,
0x12, 0xBE, 0x36, 0x72, 0x8C, 0xAC, 0x5D, 0x30,
0x5C, 0xC2, 0x0F, 0x5A, 0x92, 0x95, 0x34, 0xC4,
0x66, 0xFF, 0x5B, 0x32, 0x97, 0x07, 0xE7, 0x06,
0x5B, 0x10, 0x1D, 0xF9, 0xA7, 0xDA, 0x87, 0xFD,
0x76, 0x79, 0xF5, 0xD1, 0xE7, 0xE8, 0xA0, 0x03,
0x59, 0x70, 0xE4, 0x1A, 0x34, 0x73, 0xAA, 0xB0,
0x6A, 0x81, 0xC8, 0x24, 0x32, 0x48, 0x9E, 0x13,
0x3A, 0xFB, 0x03, 0xF3, 0xFF, 0x72, 0x4F, 0xD5,
0xC6, 0xE5, 0xDD, 0xCA, 0x6F, 0x37, 0xB4, 0x67,
0x77, 0x40, 0x8F, 0x2F, 0xFE, 0xF0, 0x61, 0xE0,
0x94, 0x45, 0x0E, 0x53, 0x9A, 0xC5, 0xC1, 0x8E,
0xA1, 0xA6, 0x73, 0xD3, 0xF4, 0x73, 0x18, 0xDC,
0xB1, 0xF3, 0xB7, 0x9B, 0xF5, 0xFF, 0x50, 0x61,
0x27, 0xD5, 0x72, 0xED, 0x64, 0x9D, 0x08, 0x84,
0x5F, 0x6E, 0x7F, 0x6E, 0xDF, 0x77, 0x0C, 0xC0,
0x19, 0xDB, 0x77, 0x54, 0x00, 0x68, 0xF8, 0xA8,
0x66, 0xF8, 0x3E, 0xE6, 0x26, 0x32, 0x32, 0xE9,
0xB0, 0xB7, 0x74, 0xFD, 0xD8, 0x58, 0x58, 0x69,
0xB0, 0x1E, 0xD3, 0x65, 0x70, 0x23, 0x79, 0x9E,
0xD9, 0x34, 0x84, 0xEB, 0xB9, 0xE4, 0x49, 0xB9,
0xF4, 0x31, 0x05, 0x31, 0x27, 0xF0, 0x80, 0x1F,
0xBE, 0xD5, 0x5F, 0x1F, 0x17, 0x9D, 0x0C, 0x7B,
0x94, 0x3E, 0x63, 0x4C, 0xF9, 0x2F, 0x76, 0xB3,
0xC1, 0xEF, 0x34, 0x20, 0xA4, 0x4B, 0x5A, 0x29,
0xAA, 0x40, 0xA9, 0x0C, 0xF2, 0x24, 0x27, 0xE8,
0xF1, 0xBF, 0xDA, 0x79, 0x75, 0x75, 0xE6, 0xA1,
0xAB, 0xD3, 0xB5, 0xCD, 0xEA, 0x1E, 0x6A, 0x9D,
0x74, 0x15, 0x77, 0x8D, 0x7A, 0x5B, 0xDA, 0x2F,
0x76, 0x7E, 0xE9, 0xFE, 0xEA, 0x88, 0x22, 0x35,
0x94, 0x60, 0x31, 0x3D, 0xA9, 0x83, 0x31, 0xBB,
0x3E, 0xEE, 0x97, 0x21, 0x0B, 0x1D, 0x76, 0x6D,
0x00, 0x9A, 0x45, 0x60, 0x7E, 0x79, 0xED, 0x70,
0x8C, 0xB1, 0xA2, 0xA1, 0xC0, 0x63, 0x37, 0x5D
}};

260
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000119.c
View File

@@ -1,260 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 Microcode patch.
*
* Fam14 Microcode Patch rev 05000119 for 5020 or equivalent.
*
*
*/
/*
******************************************************************************
*
* Copyright (c) 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuEarlyInit.h"
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
// Encrypt Patch code 05000119 for 5020 and equivalent
CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000119 =
{{
0x13, 0x20, 0x18, 0x01, 0x19, 0x01, 0x00, 0x05,
0x01, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x20, 0x50, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA,
0x55, 0xCB, 0x7C, 0x80, 0xF6, 0x0B, 0xB5, 0xB9,
0xDB, 0x48, 0xC0, 0xC7, 0xC3, 0x4B, 0x3F, 0x8E,
0x0C, 0xFE, 0xBB, 0x19, 0x27, 0xB0, 0x67, 0xE7,
0x4D, 0xB6, 0xDF, 0x55, 0x39, 0x92, 0x14, 0x55,
0x94, 0x94, 0x8F, 0xE1, 0x58, 0xE6, 0xE3, 0x99,
0x34, 0x2B, 0x74, 0x74, 0xFF, 0x5E, 0x0E, 0xBF,
0x20, 0xE5, 0xA5, 0x5E, 0xB2, 0xE7, 0xD0, 0xC9,
0x78, 0x85, 0xB2, 0xE4, 0xFB, 0x48, 0x4A, 0xD9,
0xE2, 0x9B, 0x58, 0x9B, 0x98, 0x5D, 0x2B, 0xC2,
0xF1, 0xFC, 0x43, 0x76, 0x49, 0xCB, 0x9E, 0x1E,
0x48, 0x0B, 0xF8, 0xE6, 0x51, 0xC6, 0x25, 0xBF,
0x4F, 0x2D, 0x50, 0xDF, 0xC4, 0x29, 0x80, 0x44,
0xAA, 0x2C, 0xF1, 0x4E, 0xE0, 0x0A, 0x25, 0xF0,
0x43, 0x0A, 0x22, 0xD9, 0x89, 0xA2, 0x4B, 0x0A,
0x12, 0x4C, 0x4A, 0x27, 0xCE, 0x98, 0x60, 0xF9,
0x9D, 0x76, 0x95, 0x71, 0x8C, 0xFD, 0xA1, 0x86,
0xD6, 0x42, 0x5E, 0x9F, 0x2C, 0xE2, 0x8C, 0x69,
0x20, 0x14, 0xF5, 0xF5, 0x0F, 0x65, 0xDC, 0x08,
0xFE, 0x26, 0x9E, 0xCD, 0x07, 0x45, 0xE9, 0x4D,
0xA1, 0x78, 0x1C, 0x90, 0xF5, 0x9E, 0xE5, 0x78,
0x4F, 0x7B, 0xA7, 0x8E, 0xB6, 0x24, 0x86, 0x7E,
0xBC, 0x4B, 0x6C, 0x2E, 0x3B, 0xD1, 0xA4, 0x00,
0xCA, 0x20, 0x9E, 0x1D, 0x45, 0x41, 0x62, 0xD2,
0x27, 0x50, 0x9D, 0x99, 0x2B, 0xAC, 0x1D, 0x12,
0xC0, 0x25, 0xF3, 0x95, 0xB1, 0x0F, 0x28, 0x91,
0x43, 0xC6, 0x78, 0xD6, 0xBC, 0xB0, 0x06, 0x48,
0xAB, 0x83, 0xF9, 0x14, 0xF4, 0xF4, 0x2E, 0x7A,
0x7C, 0x34, 0x8B, 0x24, 0xBB, 0x20, 0xEC, 0x87,
0xC6, 0x6A, 0x99, 0x45, 0x94, 0xDC, 0x41, 0xB6,
0x7E, 0xAE, 0x63, 0x6A, 0x46, 0x9D, 0x4C, 0xC1,
0xA5, 0xFB, 0xC3, 0x00, 0x26, 0xE0, 0x8A, 0x79,
0x5B, 0x9C, 0x05, 0xD2, 0x3C, 0x05, 0x18, 0x7C,
0x49, 0x5A, 0xDC, 0xDD, 0xDF, 0x48, 0xD0, 0x91,
0x39, 0xB6, 0xD5, 0xD8, 0x91, 0x85, 0xE9, 0xFF,
0x25, 0x5E, 0xEF, 0x02, 0xF4, 0x7A, 0x8D, 0x58,
0xA3, 0x6F, 0x66, 0xCE, 0x94, 0xF9, 0xFF, 0x42,
0x65, 0x31, 0xA9, 0x3E, 0x04, 0x4C, 0x55, 0xF4,
0x57, 0xF0, 0xD6, 0x67, 0x9F, 0x5B, 0x4B, 0x18,
0x54, 0x5A, 0xC8, 0xC0, 0x60, 0xC1, 0xED, 0x97,
0x4A, 0xDC, 0x30, 0x32, 0xF3, 0x1F, 0xA4, 0x38,
0x8D, 0x53, 0x00, 0x91, 0xAC, 0x11, 0x72, 0x5E,
0xEE, 0xEB, 0x49, 0x20, 0x59, 0xB5, 0x7F, 0x5B,
0x91, 0xF5, 0x9C, 0x3D, 0x70, 0x6B, 0xCF, 0x19,
0x9F, 0xFA, 0x40, 0x50, 0x59, 0x12, 0x85, 0xFA,
0xB9, 0x96, 0xFB, 0x4E, 0x22, 0xDA, 0xE5, 0xFD,
0xDF, 0xE7, 0x58, 0x16, 0xD0, 0xD1, 0x46, 0xF6,
0x12, 0x27, 0x34, 0x22, 0xA3, 0x71, 0x44, 0xA0,
0x6E, 0x0E, 0x56, 0x81, 0xA9, 0xB4, 0x6D, 0x37,
0xFC, 0x67, 0x69, 0xD5, 0xC4, 0x3E, 0x70, 0x0D,
0x56, 0x13, 0xB2, 0xFD, 0x7D, 0x5E, 0x2E, 0x5A,
0xC8, 0x21, 0x6A, 0xB5, 0x61, 0x33, 0xE1, 0x2C,
0x23, 0xC7, 0x2B, 0x66, 0x51, 0xA4, 0x8C, 0xFA,
0xC9, 0xEF, 0x4D, 0x10, 0xB7, 0x86, 0xA5, 0x96,
0x3D, 0x58, 0x6E, 0x7E, 0x88, 0xDF, 0x3F, 0xAC,
0xD2, 0x15, 0x0F, 0x21, 0x89, 0x50, 0x8E, 0xA9,
0x99, 0xAC, 0x5B, 0xA3, 0xD8, 0xB2, 0xFC, 0x37,
0x6C, 0x9A, 0x1C, 0x93, 0xB0, 0x87, 0x1E, 0xA2,
0x3B, 0x0F, 0x2F, 0xC9, 0x72, 0xB9, 0x39, 0x3D,
0xB9, 0x7F, 0xCF, 0x2F, 0x79, 0xA3, 0xD9, 0x5F,
0xF5, 0x53, 0x70, 0x8A, 0x88, 0x67, 0xDA, 0xDC,
0xD4, 0xB8, 0x60, 0xFC, 0x11, 0x87, 0x5A, 0xCC,
0x9A, 0xB3, 0x80, 0xC8, 0x1A, 0xC8, 0xBE, 0x10,
0xE7, 0x3D, 0x03, 0x98, 0x1A, 0x84, 0xA9, 0x6F,
0x13, 0x25, 0x69, 0x0D, 0x1B, 0x58, 0x4F, 0x7D,
0x1C, 0xD6, 0x91, 0x96, 0xD0, 0x60, 0x03, 0xA2,
0xAB, 0x62, 0x3C, 0xBB, 0xB4, 0x20, 0x79, 0x54,
0x6D, 0x12, 0x74, 0xBA, 0x40, 0x51, 0xAC, 0x22,
0xE3, 0x41, 0xC5, 0xEE, 0xCE, 0x73, 0x78, 0xAC,
0xEB, 0x12, 0x22, 0xC6, 0x20, 0x3D, 0x7F, 0x2E,
0x53, 0x37, 0x62, 0x39, 0x94, 0x8A, 0xF3, 0xAD,
0x3A, 0xD7, 0xA6, 0x27, 0x58, 0xDC, 0x6C, 0x60,
0x9E, 0x9A, 0x07, 0x72, 0x38, 0xB2, 0xC2, 0xEF,
0xE4, 0x82, 0xC5, 0xED, 0xB0, 0xC3, 0x55, 0x0A,
0x30, 0xA7, 0xAB, 0x1B, 0xB4, 0xC7, 0x98, 0x25,
0x4B, 0xB9, 0x80, 0x3F, 0x74, 0x79, 0xD1, 0x66,
0x34, 0xEC, 0x4C, 0x36, 0x44, 0x57, 0x32, 0x77,
0x59, 0xA2, 0x8A, 0xAF, 0xE9, 0x26, 0x19, 0xAA,
0x5F, 0x41, 0x25, 0x58, 0x03, 0x94, 0xBA, 0xB8,
0x12, 0xE8, 0x0F, 0x4C, 0xF8, 0x5F, 0x10, 0xD0,
0xC7, 0xC1, 0x8E, 0xEE, 0x89, 0xF0, 0x2D, 0xBB,
0x92, 0xB6, 0xBE, 0x4E, 0xA5, 0xA7, 0x40, 0xE5,
0xDD, 0xDB, 0x07, 0x8B, 0x4A, 0x10, 0x38, 0x66,
0x35, 0xAF, 0x07, 0x7A, 0x89, 0x71, 0xAE, 0x51,
0x98, 0xFC, 0xC3, 0xB7, 0x32, 0x72, 0xFE, 0x47,
0x08, 0xA5, 0x83, 0xFB, 0x93, 0x94, 0x3E, 0x2A,
0x4F, 0x32, 0x00, 0xBD, 0xFE, 0x40, 0x55, 0xB0,
0x97, 0x1B, 0x91, 0x8D, 0x21, 0x05, 0x1B, 0xBC,
0x5A, 0x37, 0x17, 0x01, 0xFC, 0xB7, 0x26, 0x09,
0x11, 0xD5, 0x0A, 0x97, 0x20, 0xF4, 0xDC, 0x12,
0x5C, 0x99, 0x18, 0xAB, 0xC7, 0xC2, 0xF4, 0xD7,
0x10, 0x4C, 0x6B, 0x52, 0x83, 0x81, 0xBD, 0x0D,
0xA6, 0xA2, 0x7C, 0x0E, 0x3B, 0x4C, 0xDC, 0x62,
0xD9, 0xFC, 0xD6, 0xD3, 0x47, 0xD2, 0xDB, 0xFD,
0xE5, 0x49, 0x6C, 0x18, 0xB6, 0xA1, 0xFD, 0x74,
0xE3, 0xAD, 0x4D, 0x01, 0xF6, 0x7D, 0x67, 0x4E,
0x93, 0x24, 0x42, 0x5F, 0xB0, 0x8F, 0xF7, 0x38,
0xA3, 0x80, 0x8C, 0x65, 0x96, 0xB0, 0x59, 0xE8,
0x2F, 0x69, 0xDA, 0xA8, 0xBA, 0x34, 0xF4, 0x76,
0x78, 0x9C, 0x24, 0x17, 0xA8, 0xE0, 0xB2, 0x6E,
0xC4, 0x23, 0x3C, 0xE1, 0xC1, 0x7C, 0x5D, 0xC9,
0x35, 0x4B, 0xDD, 0x2C, 0x1C, 0xB2, 0xD1, 0xBE,
0x38, 0x87, 0xB8, 0x19, 0x6F, 0x6D, 0xE8, 0x0B,
0xE9, 0x14, 0x13, 0x32, 0xCD, 0x6B, 0x34, 0xE9,
0x7C, 0x7A, 0x03, 0xC6, 0x67, 0x84, 0x56, 0xA6,
0x32, 0x34, 0xED, 0x9F, 0x4B, 0x34, 0x42, 0x1D,
0xDF, 0x67, 0x9F, 0xBF, 0xE3, 0x98, 0xB5, 0x36,
0x39, 0x6D, 0x43, 0xBC, 0xA6, 0x15, 0x77, 0xB0,
0x72, 0x02, 0xD9, 0x70, 0xFD, 0x8F, 0xFA, 0xD5,
0xD1, 0x02, 0xC4, 0x2B, 0x1E, 0x76, 0x48, 0xDD,
0xD4, 0x88, 0x34, 0x5D, 0xCB, 0xB3, 0x32, 0x4F,
0x13, 0x1A, 0xEC, 0x68, 0xBC, 0xB5, 0x10, 0x26,
0xB0, 0x73, 0x35, 0xCB, 0x68, 0xFF, 0xEA, 0xE1,
0x61, 0x9B, 0x14, 0x0E, 0x2F, 0xDE, 0x16, 0x21,
0xDB, 0xB2, 0x95, 0xA2, 0x8A, 0x79, 0x93, 0xC5,
0xCB, 0xCE, 0xB5, 0x6A, 0xD4, 0x0F, 0x58, 0x33,
0x12, 0x2E, 0x96, 0x14, 0xEA, 0x98, 0x9D, 0x05,
0xCD, 0x2E, 0x5B, 0x07, 0xEB, 0xA2, 0x3C, 0x8A,
0x13, 0x73, 0xAC, 0x19, 0x6B, 0xCD, 0x88, 0xBA,
0x9E, 0x39, 0x76, 0x84, 0xE4, 0xAF, 0x6B, 0x88,
0x2B, 0x70, 0xE0, 0xF6, 0x83, 0x58, 0xD5, 0x14,
0x49, 0x8E, 0x7A, 0xF1, 0xC5, 0x68, 0x77, 0xF8,
0x3C, 0x8E, 0x56, 0xB6, 0xA2, 0x66, 0x7F, 0xCB,
0x60, 0x23, 0x75, 0xB8, 0x94, 0x5C, 0x16, 0xF5,
0xA6, 0x77, 0x99, 0x3D, 0x2C, 0x0D, 0x6E, 0x64,
0x6A, 0x03, 0xBF, 0xDE, 0xEE, 0x74, 0xF1, 0x37,
0x67, 0x32, 0x73, 0xBD, 0x6F, 0x7B, 0x42, 0x4A,
0xC0, 0x8E, 0x04, 0x69, 0xFC, 0x83, 0x91, 0x7A,
0xB0, 0x3B, 0x0F, 0xAB, 0xF2, 0x9F, 0xD8, 0x70,
0x9A, 0x23, 0xB4, 0x93, 0x55, 0x6D, 0xED, 0x76,
0xCB, 0xAC, 0x3B, 0xC8, 0x69, 0x37, 0x5A, 0x98,
0xA3, 0x54, 0x78, 0x20, 0xC2, 0xEF, 0x39, 0x27,
0xB1, 0x58, 0x30, 0x46, 0x95, 0x45, 0x0E, 0x7C,
0x28, 0xBF, 0xF7, 0xA6, 0x64, 0x8E, 0xD2, 0xA2,
0xA1, 0x6D, 0x1C, 0xC3, 0xA6, 0x7A, 0xCD, 0x13,
0x85, 0x93, 0xEB, 0xA0, 0x94, 0x19, 0x02, 0xC0,
0x9A, 0xFA, 0x7A, 0x2F, 0x14, 0xB9, 0xE7, 0x57,
0x6D, 0xFD, 0x93, 0x85, 0xBD, 0x9B, 0xEE, 0x99,
0x72, 0xD5, 0x08, 0x6E, 0xCE, 0xC2, 0x40, 0x5F,
0x4B, 0xF9, 0x9E, 0xDF, 0x92, 0xF0, 0x55, 0x2C,
0x4C, 0xE5, 0x43, 0x8E, 0x2C, 0x2D, 0x23, 0x23,
0x59, 0xAE, 0x52, 0x8D, 0x27, 0x64, 0x15, 0xF9,
0xFA, 0x78, 0xA6, 0x2B, 0x48, 0xE4, 0x70, 0x05,
0x8E, 0x44, 0x4B, 0x12, 0xC6, 0x33, 0x26, 0x2D,
0x5A, 0x8D, 0x1D, 0x5C, 0xE4, 0x66, 0x40, 0x92,
0x6B, 0xB4, 0x52, 0x49, 0x82, 0x82, 0x82, 0x8B,
0x71, 0x65, 0x28, 0x5C, 0x1D, 0x4A, 0x1C, 0x4A,
0xFA, 0xB0, 0x07, 0x2A, 0x95, 0x35, 0xBC, 0xD2,
0x6A, 0x69, 0x49, 0x83, 0x67, 0xB0, 0x3C, 0x7F,
0xB7, 0xE8, 0xA4, 0xBD, 0x2B, 0xBB, 0xB2, 0x4E,
0x94, 0xCB, 0xE1, 0xAC, 0x37, 0x10, 0x61, 0xC3,
0x37, 0x95, 0x47, 0xF5, 0x54, 0x2F, 0x90, 0x7B,
0xD8, 0x07, 0xF1, 0xEB, 0x60, 0x01, 0x1B, 0xF3,
0x81, 0x26, 0x30, 0xCA, 0x26, 0x97, 0x5B, 0x17,
0x82, 0xF6, 0x0C, 0x4E, 0xE9, 0xB5, 0x47, 0xD1,
0xC1, 0x7D, 0x37, 0x36, 0xC7, 0xAC, 0xC5, 0xC4,
0xE4, 0x68, 0xD6, 0x19, 0x76, 0xFD, 0xAF, 0xF6,
0x14, 0x68, 0x9E, 0x18, 0x06, 0xD9, 0xB1, 0x57,
0xCA, 0xB0, 0x77, 0x07, 0x01, 0x8E, 0x10, 0xE4,
0x8B, 0x69, 0xD9, 0xFC, 0xEA, 0x73, 0xC7, 0xAF,
0xD8, 0xB6, 0x03, 0x79, 0x64, 0x29, 0x1B, 0xEB,
0x7D, 0x7F, 0xA0, 0x0F, 0x81, 0x44, 0x4D, 0x40,
0xB8, 0x4C, 0x66, 0x70, 0x66, 0xF5, 0xB8, 0x79,
0xE2, 0x4E, 0xF5, 0xFD, 0x27, 0xCE, 0x73, 0x8D,
0x50, 0xD8, 0xC9, 0x5B, 0x11, 0xB8, 0xB4, 0xE4,
0x83, 0x3C, 0x83, 0x0F, 0x88, 0xBB, 0x1E, 0xFC,
0xF5, 0x5A, 0x92, 0x0D, 0x82, 0x96, 0x69, 0xA4,
0xE1, 0xF1, 0x3A, 0xBD, 0xEF, 0x23, 0x63, 0xB9,
0xAA, 0x83, 0x2D, 0x98, 0x73, 0xF8, 0xB6, 0x3B,
0xE8, 0x3A, 0x73, 0x66, 0x25, 0x8F, 0x0F, 0xAB,
0x96, 0x89, 0xEE, 0x49, 0xCD, 0x8B, 0x98, 0xA1,
0x3F, 0x04, 0x7A, 0x31, 0x53, 0x68, 0x11, 0xAD,
0xB6, 0x0D, 0xD2, 0x72, 0x25, 0xCC, 0x7B, 0x5F,
0x34, 0x3F, 0x10, 0x1E, 0x6E, 0xEE, 0x6B, 0x8B,
0x35, 0x0E, 0x55, 0x30, 0x0D, 0xAF, 0x8F, 0x94,
0x3E, 0x07, 0x2A, 0x82, 0x52, 0x08, 0xEC, 0xC9,
0xEB, 0x0E, 0xD8, 0x6B, 0xB0, 0xA5, 0xBE, 0x14,
0x1D, 0xBB, 0x8A, 0x0D, 0xF9, 0x8C, 0x25, 0x69,
0xDB, 0xB1, 0xC3, 0x40, 0x99, 0x9D, 0x51, 0x13,
0x63, 0x1C, 0x10, 0xB3, 0x92, 0x4E, 0xDF, 0x1D,
0xDD, 0x5B, 0x36, 0x4D, 0x1D, 0x94, 0xD4, 0xAC,
0x90, 0xCE, 0x3D, 0xC4, 0x12, 0x92, 0x10, 0xA7,
0x54, 0xEC, 0x25, 0xE6, 0x18, 0xCD, 0xF1, 0x70,
0x1E, 0x51, 0x7A, 0xF7, 0x1B, 0xBF, 0xDC, 0x94,
0x5F, 0xA3, 0x54, 0xEF, 0xFD, 0xA7, 0x8A, 0x3E,
0xEB, 0xE6, 0x5D, 0xFD, 0xB5, 0x3F, 0xE9, 0xDA,
0xEF, 0xDC, 0x1F, 0x11, 0x78, 0x66, 0xED, 0x46,
0xAF, 0xBD, 0xDB, 0x10, 0x16, 0x32, 0x43, 0xB9,
0x14, 0xDA, 0x6F, 0x77, 0x6D, 0x92, 0x4B, 0x1D,
0xA7, 0xC5, 0x61, 0xA7, 0xE4, 0xCC, 0x3C, 0x5F,
0xF7, 0x3F, 0x6D, 0x49, 0xE1, 0x18, 0x14, 0x5F,
0x7D, 0x92, 0xFB, 0xB9, 0x8F, 0x78, 0x11, 0x18,
0xB3, 0x34, 0x3E, 0x78, 0xF2, 0xFC, 0x49, 0x24
}};

77
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14PackageType.h
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@@ -1,77 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 Package Type Definitions
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F14
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _F14_PACKAGE_TYPE_H_
#define _F14_PACKAGE_TYPE_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
// Below equates are defined to cooperate with LibAmdGetPackageType.
#define PACKAGE_TYPE_FT1_BIT (1 << 0)
// Raw data definitions
#define PACKAGE_TYPE_FT1 0
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
#endif // _F14_PACKAGE_TYPE_H_

22
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/Makefile.inc
View File

@@ -1,22 +0,0 @@
libagesa-y += F14C6State.c
libagesa-y += F14IoCstate.c
libagesa-y += F14MicrocodePatch0500000B.c
libagesa-y += F14MicrocodePatch0500001A.c
libagesa-y += F14MicrocodePatch05000029.c
libagesa-y += F14MicrocodePatch05000119.c
libagesa-y += cpuCommonF14Utilities.c
libagesa-y += cpuF14BrandId.c
libagesa-y += cpuF14BrandIdFt1.c
libagesa-y += cpuF14CacheDefaults.c
libagesa-y += cpuF14Dmi.c
libagesa-y += cpuF14LowPowerInit.c
libagesa-y += cpuF14MsrTables.c
libagesa-y += cpuF14PciTables.c
libagesa-y += cpuF14PerCorePciTables.c
libagesa-y += cpuF14PowerCheck.c
libagesa-y += cpuF14PowerMgmtSystemTables.c
libagesa-y += cpuF14PowerPlane.c
libagesa-y += cpuF14Pstate.c
libagesa-y += cpuF14SoftwareThermal.c
libagesa-y += cpuF14Utilities.c
libagesa-y += cpuF14WheaInitDataTables.c

187
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnCpb.c
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@@ -1,187 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family 14 Ontario CPB Initialization
*
* Enables core performance boost.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x14/ON
* @e \$Revision: 46389 $ @e \$Date: 2011-01-31 22:22:49 -0500 (Mon, 31 Jan 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuFamilyTranslation.h"
#include "cpuF14PowerMgmt.h"
#include "GnbRegistersON.h"
#include "NbSmuLib.h"
#include "NbSmuLib.h"
#include "cpuFeatures.h"
#include "cpuCpb.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X14_ON_F14ONCPB_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* BSC entry point for checking whether or not CPB is supported.
*
* @param[in] CpbServices The current CPU's family services.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] Socket Zero based socket number to check.
* @param[in] StdHeader Config handle for library and services.
*
* @retval TRUE CPB is supported.
* @retval FALSE CPB is not supported.
*
*/
BOOLEAN
STATIC
F14OnIsCpbSupported (
IN CPB_FAMILY_SERVICES *CpbServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
CPB_CTRL_REGISTER CpbControl;
CPU_LOGICAL_ID CpuFamilyRevision;
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) != 0) {
return FALSE;
} else {
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
return (BOOLEAN) (CpbControl.NumBoostStates != 0);
}
}
/*---------------------------------------------------------------------------------------*/
/**
* BSC entry point for enabling Core Performance Boost.
*
* Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
*
* @param[in] CpbServices The current CPU's family services.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] EntryPoint Current CPU feature dispatch point.
* @param[in] Socket Zero based socket number to check.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F14OnInitializeCpb (
IN CPB_FAMILY_SERVICES *CpbServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN UINT64 EntryPoint,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
CPB_CTRL_REGISTER CpbControl;
LPMV_SCALAR2_REGISTER LpmvScalar2;
SMUx0B_x8580_STRUCT SMUx0Bx8580;
if ((EntryPoint & CPU_FEAT_BEFORE_PM_INIT) != 0) {
// F4x14C [25:24] ApmCstExtPol = 1
PciAddress.AddressValue = LPMV_SCALAR2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LpmvScalar2, StdHeader);
LpmvScalar2.ApmCstExtPol = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &LpmvScalar2, StdHeader);
// F4x15C [1:0] BoostSrc = 1
// F4x15C [29] BoostEnAllCores = 1
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
CpbControl.BoostSrc = 1;
CpbControl.BoostEnAllCores = 1;
IDS_OPTION_HOOK (IDS_CPB_CTRL, &CpbControl, StdHeader);
LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader);
} else if ((EntryPoint & CPU_FEAT_INIT_LATE_END) != 0) {
// Ensure that the recommended settings have been programmed into SMUx0B_x8580, then
// interrupt the SMU with service index 12h.
NbSmuRcuRegisterRead (SMUx0B_x8580_ADDRESS, &SMUx0Bx8580.Value, 1, StdHeader);
SMUx0Bx8580.Field.PdmPeriod = 0x1388;
SMUx0Bx8580.Field.PdmParamLoc = 0;
SMUx0Bx8580.Field.PdmCacEn = 1;
SMUx0Bx8580.Field.PdmUnit = 1;
SMUx0Bx8580.Field.PdmEn = 1;
NbSmuRcuRegisterWrite (SMUx0B_x8580_ADDRESS, &SMUx0Bx8580.Value, 1, TRUE, StdHeader);
NbSmuServiceRequest (0x12, TRUE, StdHeader);
}
return AGESA_SUCCESS;
}
CONST CPB_FAMILY_SERVICES ROMDATA F14OnCpbSupport =
{
0,
F14OnIsCpbSupported,
F14OnInitializeCpb
};

135
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c
View File

@@ -1,135 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 Ontario Equivalence Table related data
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x14
* @e \$Revision: 48589 $ @e \$Date: 2011-03-10 09:27:00 -0700 (Thu, 10 Mar 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
#include "amdlib.h"
#include "cpuRegisters.h"
#define FILECODE PROC_CPU_FAMILY_0X14_ON_F14ONEQUIVALENCETABLE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
GetF14OnMicrocodeEquivalenceTable (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **OnEquivalenceTablePtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
STATIC CONST UINT16 ROMDATA CpuF14MicrocodeEquivalenceTable[] =
{
0x5000, 0x5000,
0x5001, 0x5001,
0x5010, 0x5010,
0x5020, 0x5020
};
// Unencrypted equivalent
STATIC CONST UINT16 ROMDATA CpuF14UnEncryptedMicrocodeEquivalenceTable[] =
{
0x5000, 0x5800,
0x5001, 0x5801,
0x5010, 0x5810,
0x5020, 0x5820
};
/*---------------------------------------------------------------------------------------*/
/**
* Returns the appropriate microcode patch equivalent ID table.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] OnEquivalenceTablePtr Points to the first entry in the table.
* @param[out] NumberOfElements Number of valid entries in the table.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF14OnMicrocodeEquivalenceTable (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **OnEquivalenceTablePtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrMeCfg;
LibAmdMsrRead (MSR_ME_CFG, &MsrMeCfg, StdHeader);
if ((MsrMeCfg & 0x1000) == 0) {
*NumberOfElements = ((sizeof (CpuF14UnEncryptedMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
*OnEquivalenceTablePtr = CpuF14UnEncryptedMicrocodeEquivalenceTable;
} else {
*NumberOfElements = ((sizeof (CpuF14MicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
*OnEquivalenceTablePtr = CpuF14MicrocodeEquivalenceTable;
}
}

317
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c
View File

@@ -1,317 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Implements the workaround for encrypted microcode patch loading.
*
* Returns the table of initialization steps to perform at
* AmdInitEarly.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x14/ON
* @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuRegisters.h"
#include "cpuFamilyTranslation.h"
#include "cpuEarlyInit.h"
#include "GnbRegistersON.h"
#include "F14OnInitEarlyTable.h"
#include "OptionFamily14hEarlySample.h"
#include "GeneralServices.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_ON_F14ONINITEARLYTABLE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
// Field Data
#define D18F4x164_FixedErrata_0_OFFSET 0
#define D18F4x164_FixedErrata_0_WIDTH 1
#define D18F4x164_FixedErrata_0_MASK 0x00000001
#define D18F4x164_Reserved_31_1_OFFSET 1
#define D18F4x164_Reserved_31_1_WIDTH 31
#define D18F4x164_Reserved_31_1_MASK 0xFFFFFFFE
extern F14_ES_CORE_SUPPORT F14EarlySampleCoreSupport;
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
GetF14OnEarlyInitOnCoreTable (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
F14OnLoadMicrocodePatchAtEarly (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
F14OnProductionErrataAtEarly (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
extern F_PERFORM_EARLY_INIT_ON_CORE McaInitializationAtEarly;
extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAtEarly;
extern F_PERFORM_EARLY_INIT_ON_CORE SetBrandIdRegistersAtEarly;
extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly;
CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F14OnEarlyInitOnCoreTable[] =
{
{McaInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
{SetRegistersFromTablesAtEarly, PERFORM_EARLY_ANY_CONDITION},
{SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION},
{LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
{F14OnLoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION},
{F14NbBufferAllocationAtEarly, PERFORM_EARLY_ANY_CONDITION},
{F14OnProductionErrataAtEarly, PERFORM_EARLY_ANY_CONDITION},
{NULL, 0}
};
/*------------------------------------------------------------------------------------*/
/**
* Initializer routine that may be invoked at AmdCpuEarly to return the steps that a
* processor that uses the standard initialization steps should take.
*
* @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}.
*
* @param[in] FamilyServices The current Family Specific Services.
* @param[out] Table Table of appropriate init steps for the executing core.
* @param[in] EarlyParams Service Interface structure to initialize.
* @param[in] StdHeader Opaque handle to standard config header.
*
*/
VOID
GetF14OnEarlyInitOnCoreTable (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
*Table = F14OnEarlyInitOnCoreTable;
F14EarlySampleCoreSupport.F14GetEarlyInitTableHook ((const VOID **)Table, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
* Update microcode patch in current processor for Family14h ON.
*
* This function acts as a wrapper for calling the LoadMicrocodePatch
* routine at AmdInitEarly.
*
* @param[in] FamilyServices The current Family Specific Services.
* @param[in] EarlyParams Service parameters.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F14OnLoadMicrocodePatchAtEarly (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrValue;
AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader);
// To load a microcode patch while using the cache as general storage,
// the following steps are followed:
// 1. Program MSRC001_102B[L2AllocDcFlushVictim]=1.
// 2. Load the microcode patch.
// 3. Program MSRC001_102B[L2AllocDcFlushVictim]=0.
LibAmdMsrRead (MSR_BU_CFG3, &MsrValue, StdHeader);
MsrValue = MsrValue | BIT7;
LibAmdMsrWrite (MSR_BU_CFG3, &MsrValue, StdHeader);
LoadMicrocodePatch (StdHeader);
LibAmdMsrRead (MSR_BU_CFG3, &MsrValue, StdHeader);
MsrValue = MsrValue & ~((UINT64)BIT7);
LibAmdMsrWrite (MSR_BU_CFG3, &MsrValue, StdHeader);
}
/**
* North bridge bufer allocation for Family14h ON.
*
* This function programs North bridge buffer allocation registers and provides
* hook routine for override at AmdInitEarly.
*
* @param[in] FamilyServices The current Family Specific Services.
* @param[in] EarlyParams Service parameters.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F14NbBufferAllocationAtEarly (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
//Buffer allocations cannot be decreased through software, so move these register setting from register table
//to here to make IDS easy override
NB_BUFFER_ALLOCATION NbBufAllocation;
PCI_ADDR PciAddr;
AGESA_STATUS Ignored;
if (IsBsp (StdHeader, &Ignored)) {
PciAddr.AddressValue = MAKE_SBDFO (0, 0, 24, FUNC_3, D18F3x6C_ADDRESS);
LibAmdPciRead (AccessWidth32, PciAddr, &NbBufAllocation.D18F3x6C.Value, StdHeader);
PciAddr.Address.Register = D18F3x74_ADDRESS;
LibAmdPciRead (AccessWidth32, PciAddr, &NbBufAllocation.D18F3x74.Value, StdHeader);
PciAddr.Address.Register = D18F3x7C_ADDRESS;
LibAmdPciRead (AccessWidth32, PciAddr, &NbBufAllocation.D18F3x7C.Value, StdHeader);
PciAddr.Address.Register = D18F3x17C_ADDRESS;
LibAmdPciRead (AccessWidth32, PciAddr, &NbBufAllocation.D18F3x17C.Value, StdHeader);
//Recommend value for NB buffer allocation
// D18F3x6C - Upstream Data Buffer Count
// bits[3:0] UpLoPreqDBC = 0x0E
// bits[7:4] UpLoNpReqDBC = 1
// bits[11:8] UpLoRespDBC = 1
// bits[19:16] UpHiPreqDBC = 0
// bits[23:20] UpHiNpReqDBC = 0
NbBufAllocation.D18F3x6C.Field.UpLoPreqDBC = 0x0E;
NbBufAllocation.D18F3x6C.Field.UpLoNpreqDBC = 1;
NbBufAllocation.D18F3x6C.Field.UpLoRespDBC = 1;
NbBufAllocation.D18F3x6C.Field.UpHiPreqDBC = 0;
NbBufAllocation.D18F3x6C.Field.UpHiNpreqDBC = 0;
// D18F3x74 - Upstream Command Buffer Count
// bits[3:0] UpLoPreqCBC = 7
// bits[7:4] UpLoNpreqCBC = 9
// bits[11:8] UpLoRespCBC = 8
// bits[19:16] UpHiPreqCBC = 0
// bits[23:20] UpHiNpreqCBC = 0
NbBufAllocation.D18F3x74.Field.UpLoPreqCBC = 7;
NbBufAllocation.D18F3x74.Field.UpLoNpreqCBC = 9;
NbBufAllocation.D18F3x74.Field.UpLoRespCBC = 8;
NbBufAllocation.D18F3x74.Field.UpHiPreqCBC = 0;
NbBufAllocation.D18F3x74.Field.UpHiNpreqCBC = 0;
// D18F3x7C - In-Flight Queue Buffer Allocation
// bits[5:0] CpuBC = 1
// bits[13:8] LoPriPBC = 1
// bits[21:16] LoPriNPBC = 1
// bits[29:24] FreePoolBC = 0x19
NbBufAllocation.D18F3x7C.Field.CpuBC = 1;
NbBufAllocation.D18F3x7C.Field.LoPriPBC = 1;
NbBufAllocation.D18F3x7C.Field.LoPriNPBC = 1;
NbBufAllocation.D18F3x7C.Field.FreePoolBC = 0x19;
// D18F3x17C - In-Flight Queue Extended Buffer Allocation
// bits[5:0] HiPriPBC = 0
// bits[13:8] HiPriNPBC = 0
NbBufAllocation.D18F3x17C.Field.HiPriPBC = 0;
NbBufAllocation.D18F3x17C.Field.HiPriNPBC = 0;
IDS_OPTION_HOOK (IDS_NBBUFFERALLOCATIONATEARLY, &NbBufAllocation, StdHeader);
PciAddr.AddressValue = MAKE_SBDFO (0, 0, 24, FUNC_3, D18F3x6C_ADDRESS);
LibAmdPciWrite (AccessWidth32, PciAddr, &NbBufAllocation.D18F3x6C.Value, StdHeader);
PciAddr.Address.Register = D18F3x74_ADDRESS;
LibAmdPciWrite (AccessWidth32, PciAddr, &NbBufAllocation.D18F3x74.Value, StdHeader);
PciAddr.Address.Register = D18F3x7C_ADDRESS;
LibAmdPciWrite (AccessWidth32, PciAddr, &NbBufAllocation.D18F3x7C.Value, StdHeader);
PciAddr.Address.Register = D18F3x17C_ADDRESS;
LibAmdPciWrite (AccessWidth32, PciAddr, &NbBufAllocation.D18F3x17C.Value, StdHeader);
}
}
/**
* Production Erratum for Family14h ON.
*
* This function implements production errata for Family14h ON.
* routine at AmdInitEarly.
*
* @param[in] FamilyServices The current Family Specific Services.
* @param[in] EarlyParams Service parameters.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F14OnProductionErrataAtEarly (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPU_LOGICAL_ID LogicalId;
PCI_ADDR PciAddr;
UINT32 PciData;
UINT64 MsrValue;
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
PciAddr.AddressValue = MAKE_SBDFO (0, 0, 24, FUNC_4, D18F4x164_ADDRESS);
LibAmdPciRead (AccessWidth32, PciAddr, &PciData, StdHeader);
if (((PciData & D18F4x164_FixedErrata_0_MASK) == 1) &&
((LogicalId.Revision & ~(AMD_F14_ON_Ax | AMD_F14_UNKNOWN)) != 0)) {
// Program MSRC001_1020[18] = 1 only when D18F4x164[0] == 1 on ON B0 and later parts.
LibAmdMsrRead (MSR_LS_CFG, &MsrValue, StdHeader);
MsrValue = MsrValue | BIT18;
LibAmdMsrWrite (MSR_LS_CFG, &MsrValue, StdHeader);
}
}

69
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.h
View File

@@ -1,69 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Implements the workaround for encrypted microcode patch loading.
*
* Returns the table of initialization steps to perform at
* AmdInitEarly.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x14/ON
* @e \$Revision: 37004 $ @e \$Date: 2010-08-28 02:23:00 +0800 (Sat, 28 Aug 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
VOID
F14NbBufferAllocationAtEarly (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
/// define NB buffer allocation setting
typedef struct _NB_BUFFER_ALLOCATION {
D18F3x6C_STRUCT D18F3x6C; ///< reg for D18F3x6C
D18F3x74_STRUCT D18F3x74; ///< reg for D18F3x74
D18F3x7C_STRUCT D18F3x7C; ///< reg for D18F3x7C
D18F3x17C_STRUCT D18F3x17C; ///< reg for D18F3x17C
} NB_BUFFER_ALLOCATION;
/// enum for ON Erratum 463 wrokaround
typedef enum {
ON_ERRATUM463_WORKAROUND_DISABLE = 0, ///< work around disable
ON_ERRATUM463_WORKAROUND_ENABLE = 1, ///< work around enable
} ON_ERRATUM463_WORKAROUND;

114
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c
View File

@@ -1,114 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 Ontario Logical ID Table
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x14
* @e \$Revision: 36248 $ @e \$Date: 2010-08-16 16:15:26 +0800 (Mon, 16 Aug 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_ON_F14ONLOGICALIDTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
GetF14OnLogicalIdAndRev (
OUT CONST CPU_LOGICAL_ID_XLAT **OnIdPtr,
OUT UINT8 *NumberOfElements,
OUT UINT64 *LogicalFamily,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF14OnLogicalIdAndRevArray[] =
{
{
0x5000,
AMD_F14_ON_A0
},
{
0x5001,
AMD_F14_ON_A1
},
{
0x5010,
AMD_F14_ON_B0
},
{
0x5020,
AMD_F14_ON_C0
}
};
VOID
GetF14OnLogicalIdAndRev (
OUT CONST CPU_LOGICAL_ID_XLAT **OnIdPtr,
OUT UINT8 *NumberOfElements,
OUT UINT64 *LogicalFamily,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
*NumberOfElements = (sizeof (CpuF14OnLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
*OnIdPtr = CpuF14OnLogicalIdAndRevArray;
*LogicalFamily = AMD_FAMILY_14_ON;
}

110
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c
View File

@@ -1,110 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 Ontario PCI tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x10
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuEarlyInit.h"
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_ON_F14ONMICROCODEPATCHTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
extern CONST MICROCODE_PATCHES ROMDATA *CpuF14OnMicroCodePatchArray[];
extern CONST UINT8 ROMDATA CpuF14OnNumberOfMicrocodePatches;
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
GetF14OnMicroCodePatchesStruct (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **OnUcodePtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Returns a table containing the appropriate microcode patches.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] OnUcodePtr Points to the first entry in the table.
* @param[out] NumberOfElements Number of valid entries in the table.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF14OnMicroCodePatchesStruct (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **OnUcodePtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
*NumberOfElements = CpuF14OnNumberOfMicrocodePatches;
*OnUcodePtr = &CpuF14OnMicroCodePatchArray[0];
}

105
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnPciTables.c
View File

@@ -1,105 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 Ontario PCI tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x14/ON
* @e \$Revision: 46389 $ @e \$Date: 2011-01-31 22:22:49 -0500 (Mon, 31 Jan 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Table.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_ON_F14ONPCITABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
// P C I T a b l e s
// ----------------------
STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14OnPciRegisters[] =
{
// Function 4
// D18F4x104 - TDP Lock Accumulator
// bits[1:0] TdpLockDivVal = 1
// bits[13:2] TdpLockDivRate = 0x190
// bits[16:15] TdpLockDivValCpu = 1
// bits[28:17] TdpLockDivRateCpu = 0x190
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ON_Cx // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x104), // Address
0x03208641, // regData
0x1FFFBFFF, // regMask
}}
},
};
CONST REGISTER_TABLE ROMDATA F14OnPciRegisterTable = {
PrimaryCores,
(sizeof (F14OnPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
F14OnPciRegisters,
};

6
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/Makefile.inc
View File

@@ -1,6 +0,0 @@
libagesa-y += F14OnCpb.c
libagesa-y += F14OnEquivalenceTable.c
libagesa-y += F14OnInitEarlyTable.c
libagesa-y += F14OnLogicalIdTables.c
libagesa-y += F14OnMicrocodePatchTables.c
libagesa-y += F14OnPciTables.c

539
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuCommonF14Utilities.c
View File

@@ -1,539 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 specific utility functions.
*
* Provides numerous utility functions specific to family 10h.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F14
* @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuRegisters.h"
#include "cpuFamilyTranslation.h"
#include "cpuCommonF14Utilities.h"
#include "cpuF14PowerMgmt.h"
#include "OptionFamily14hEarlySample.h"
#include "NbSmuLib.h"
#include "GnbRegistersON.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_CPUCOMMONF14UTILITIES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
extern F14_ES_CORE_SUPPORT F14EarlySampleCoreSupport;
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
CONST UINT16 ROMDATA F14MaxNbFreqAtMinVidFreqTable[] =
{
25, // 00000b
50, // 00001b
100, // 00010b
150, // 00011b
167, // 00100b
183, // 00101b
200, // 00110b
217, // 00111b
233, // 01000b
250, // 01001b
267, // 01010b
283, // 01011b
300, // 01100b
317, // 01101b
333, // 01110b
350, // 01111b
366, // 10000b
383, // 10001b
400, // 10010b
417, // 10011b
433, // 10100b
450, // 10101b
467, // 10110b
483, // 10111b
500, // 11000b
517, // 11001b
533, // 11010b
550, // 11011b
563, // 11100b
575, // 11101b
588, // 11110b
600 // 11111b
};
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
UINT32
F14GetApCoreNumber (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
);
CORE_ID_POSITION
F14CpuAmdCoreIdPositionInInitialApicId (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT32
STATIC
RoundedDivision (
IN UINT32 Dividend,
IN UINT32 Divisor
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Set warm reset status and count
*
* @CpuServiceMethod{::F_CPU_SET_WARM_RESET_FLAG}.
*
* This function will use bit9, and bit 10 of register F0x6C as a warm reset status and count.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
* @param[in] Request Indicate warm reset status
*
*/
VOID
F14SetAgesaWarmResetFlag (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader,
IN WARM_RESET_REQUEST *Request
)
{
PCI_ADDR PciAddress;
UINT32 PciData;
PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL);
LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
// bit[5] - indicate a warm reset is or is not required
PciData &= ~(HT_INIT_BIOS_RST_DET_0);
PciData = PciData | (Request->RequestBit << 5);
// bit[10,9] - indicate warm reset status and count
PciData &= ~(HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2);
PciData |= Request->StateBits << 9;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
* Get warm reset status and count
*
* @CpuServiceMethod{::F_CPU_GET_WARM_RESET_FLAG}.
*
* This function will bit9, and bit 10 of register F0x6C as a warm reset status and count.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] StdHeader Config handle for library and services
* @param[out] Request Indicate warm reset status
*
*/
VOID
F14GetAgesaWarmResetFlag (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader,
OUT WARM_RESET_REQUEST *Request
)
{
PCI_ADDR PciAddress;
UINT32 PciData;
PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL);
LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
// bit[5] - indicate a warm reset is or is not required
Request->RequestBit = (UINT8) ((PciData & HT_INIT_BIOS_RST_DET_0) >> 5);
// bit[10,9] - indicate warm reset status and count
Request->StateBits = (UINT8) ((PciData & (HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2)) >> 9);
}
/*---------------------------------------------------------------------------------------*/
/**
* Use the Mailbox Register to get the Ap Mailbox info for the current core.
*
* @CpuServiceMethod{::F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE}.
*
* Access the mailbox register used with this NB family. This is valid until the
* point that some init code initializes the mailbox register for its normal use.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] ApMailboxInfo The AP Mailbox info
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
*/
VOID
F14GetApMailboxFromHardware (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT AP_MAILBOXES *ApMailboxInfo,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
// For Family 14h, we will return socket 0, node 0, module 0, module type 0, and 0 for
// the system degree
ApMailboxInfo->ApMailInfo.Info = (UINT32) 0x00000000;
ApMailboxInfo->ApMailExtInfo.Info = (UINT32) 0x00000000;
}
/*---------------------------------------------------------------------------------------*/
/**
* Get this AP's system core number from hardware.
*
* @CpuServiceMethod{::F_CPU_GET_AP_CORE_NUMBER}.
*
* Returns the system core number. For family 14h, this is simply the
* initial APIC ID.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @return The AP's unique core number
*/
UINT32
F14GetApCoreNumber (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPUID_DATA Cpuid;
LibAmdCpuidRead (0x1, &Cpuid, StdHeader);
return ((Cpuid.EBX_Reg >> 24) & 0xFF);
}
/*---------------------------------------------------------------------------------------*/
/**
* Return a number zero or one, based on the Core ID position in the initial APIC Id.
*
* @CpuServiceMethod{::F_CORE_ID_POSITION_IN_INITIAL_APIC_ID}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @retval CoreIdPositionZero Core Id is not low
* @retval CoreIdPositionOne Core Id is low
*/
CORE_ID_POSITION
F14CpuAmdCoreIdPositionInInitialApicId (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return (CoreIdPositionOne);
}
/*---------------------------------------------------------------------------------------*/
/**
* Sets up a valid set of NB P-states based on the value of MEMCLK, transitions
* to the desired NB P-state, and returns the current NB frequency in megahertz.
*
* @param[in] TargetMemclk The target MEMCLK in megahertz, or zero to
* indicate NB P-state change only.
* @param[in] TargetMemclkEncoded The target MEMCLK's register encoding.
* @param[in] TargetNbPstate The NB P-state to exit in.
* @param[in] CurrentNbFreq Current NB operating frequency in megahertz.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @retval TRUE Transition to TargetNbPstate was successful.
* @retval FALSE Transition to TargetNbPstate was unsuccessful.
*/
BOOLEAN
F14NbPstateInit (
IN UINT32 TargetMemclk,
IN UINT32 TargetMemclkEncoded,
IN UINT32 TargetNbPstate,
OUT UINT32 *CurrentNbFreq,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 EncodedNbPs1Vid;
UINT32 EncodedNbPs0NclkDiv;
UINT32 EncodedNbPs1NclkDiv;
UINT32 NbP0Cof;
UINT32 NbP1Cof;
UINT32 NbPstateNumerator;
UINT32 TargetNumerator;
UINT32 TargetDenominator;
BOOLEAN ReturnStatus;
BOOLEAN WaitForTransition;
PCI_ADDR PciAddress;
D18F3xD4_STRUCT Cptc0;
D18F3xDC_STRUCT Cptc2;
D18F6x90_STRUCT NbPsCfgLow;
D18F6x98_STRUCT NbPsCtrlSts;
FCRxFE00_6000_STRUCT FCRxFE00_6000;
FCRxFE00_6002_STRUCT FCRxFE00_6002;
FCRxFE00_7006_STRUCT FCRxFE00_7006;
FCRxFE00_7009_STRUCT FCRxFE00_7009;
// F14 only supports NB P0 and NB P1
ASSERT (TargetNbPstate < 2);
WaitForTransition = FALSE;
ReturnStatus = TRUE;
// Get D18F3xD4[MainPllOpFreqId] frequency
PciAddress.AddressValue = CPTC0_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &Cptc0.Value, StdHeader);
// Calculate the numerator to be used for NB P-state calculations
NbPstateNumerator = (UINT32) (4 * ((Cptc0.Field.MainPllOpFreqId + 0x10) * 100));
if (TargetMemclk != 0) {
// Determine the appropriate numerator / denominator of the target memclk
switch (TargetMemclk) {
case DDR800_FREQUENCY:
TargetNumerator = 400;
TargetDenominator = 1;
break;
case DDR1066_FREQUENCY:
TargetNumerator = 1600;
TargetDenominator = 3;
break;
case DDR1333_FREQUENCY:
TargetNumerator = 2000;
TargetDenominator = 3;
break;
default:
// An invalid memclk has been passed in.
ASSERT (FALSE);
TargetNumerator = TargetMemclk;
TargetDenominator = 1;
break;
}
FCRxFE00_6000.Value = NbSmuReadEfuse (FCRxFE00_6000_ADDRESS, StdHeader);
FCRxFE00_6002.Value = NbSmuReadEfuse (FCRxFE00_6002_ADDRESS, StdHeader);
FCRxFE00_7006.Value = NbSmuReadEfuse (FCRxFE00_7006_ADDRESS, StdHeader);
FCRxFE00_7009.Value = NbSmuReadEfuse (FCRxFE00_7009_ADDRESS, StdHeader);
F14EarlySampleCoreSupport.F14NbPstateInitHook (&FCRxFE00_6000,
&FCRxFE00_6002,
&FCRxFE00_7006,
&FCRxFE00_7009,
NbPstateNumerator,
StdHeader);
// Determine NB P0 settings
if ((TargetNumerator * FCRxFE00_7009.Field.NbPs0NclkDiv) < (NbPstateNumerator * TargetDenominator)) {
// Program D18F3xDC[NbPs0NclkDiv] to the minimum divisor where
// (target memclk frequency >= (D18F3xD4[MainPllOpFreqId] freq) / divisor)
EncodedNbPs0NclkDiv = ((NbPstateNumerator * TargetDenominator) / TargetNumerator);
if (((NbPstateNumerator * TargetDenominator) % TargetNumerator) != 0) {
EncodedNbPs0NclkDiv++;
}
// Ensure that the encoded divisor is even to give 50% duty cycle
EncodedNbPs0NclkDiv = ((EncodedNbPs0NclkDiv + 1) & 0xFFFFFFFE);
ASSERT (EncodedNbPs0NclkDiv >= 8);
ASSERT (EncodedNbPs0NclkDiv <= 0x3F);
} else {
EncodedNbPs0NclkDiv = FCRxFE00_7009.Field.NbPs0NclkDiv;
}
// Check to see if the DIMMs are too fast for the CPU (NB P0 COF < (Memclk / 2))
if ((TargetNumerator * EncodedNbPs0NclkDiv) > (NbPstateNumerator * TargetDenominator * 2)) {
// Indicate the error to the memory code so the DIMMs can be derated.
ReturnStatus = FALSE;
}
// Apply the appropriate P0 frequency
PciAddress.AddressValue = CPTC2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader);
if (Cptc2.Field.NbPs0NclkDiv != EncodedNbPs0NclkDiv) {
WaitForTransition = TRUE;
Cptc2.Field.NbPs0NclkDiv = EncodedNbPs0NclkDiv;
LibAmdPciWrite (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader);
}
NbP0Cof = RoundedDivision (NbPstateNumerator, EncodedNbPs0NclkDiv);
// Determine NB P1 settings if necessary
PciAddress.AddressValue = NB_PSTATE_CFG_LOW_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader);
if (NbPsCfgLow.Field.NbPsCap == 1) {
if ((TargetNumerator * FCRxFE00_7006.Field.NbPs1NclkDiv) > (NbPstateNumerator * TargetDenominator * 2)) {
// Program D18F6x90[NbPs1NclkDiv] to the maximum divisor where
// (target memclk frequency / 2 <= (D18F3xD4[MainPllOpFreqId] freq) / divisor)
EncodedNbPs1NclkDiv = ((NbPstateNumerator * TargetDenominator * 2) / TargetNumerator);
// Ensure that the encoded divisor is even to give 50% duty cycle
EncodedNbPs1NclkDiv &= 0xFFFFFFFE;
ASSERT (EncodedNbPs1NclkDiv >= 8);
ASSERT (EncodedNbPs1NclkDiv <= 0x3F);
// Calculate the new effective P1 frequency to determine the voltage
NbP1Cof = RoundedDivision (NbPstateNumerator, EncodedNbPs1NclkDiv);
if (NbP1Cof <= F14MaxNbFreqAtMinVidFreqTable[FCRxFE00_7006.Field.MaxNbFreqAtMinVid]) {
// Program D18F6x90[NbPs1Vid] = FCRxFE00_6002[NbPs1VidAddl]
EncodedNbPs1Vid = FCRxFE00_6002.Field.NbPs1VidAddl;
} else {
// Program D18F6x90[NbPs1Vid] = FCRxFE00_6002[NbPs1VidHigh]
EncodedNbPs1Vid = FCRxFE00_6002.Field.NbPs1VidHigh;
}
} else {
// Fused frequency and voltage are legal
EncodedNbPs1Vid = FCRxFE00_6000.Field.NbPs1Vid;
EncodedNbPs1NclkDiv = FCRxFE00_7006.Field.NbPs1NclkDiv;
NbP1Cof = RoundedDivision (NbPstateNumerator, EncodedNbPs1NclkDiv);
}
if (NbP0Cof < NbP1Cof) {
// NB P1 frequency is faster than NB P0. Fix it up by slowing
// P1 to match P0.
EncodedNbPs1NclkDiv = EncodedNbPs0NclkDiv;
NbP1Cof = NbP0Cof;
}
// Program the new NB P1 settings
NbPsCfgLow.Field.NbPs1NclkDiv = EncodedNbPs1NclkDiv;
NbPsCfgLow.Field.NbPs1Vid = EncodedNbPs1Vid;
LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader);
} else {
// NB P-states are not enabled
NbP1Cof = 0;
}
*CurrentNbFreq = NbP0Cof;
if (WaitForTransition) {
// Ensure that the frequency has settled before returning to memory code.
PciAddress.AddressValue = CPTC2_PCI_ADDR;
do {
LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader);
} while (Cptc2.Field.NclkFreqDone != 1);
}
} else {
// Get NB P0 COF
PciAddress.AddressValue = CPTC2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader);
NbP0Cof = RoundedDivision (NbPstateNumerator, Cptc2.Field.NbPs0NclkDiv);
// Read NB P-state status
PciAddress.AddressValue = NB_PSTATE_CTRL_STS_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlSts.Value, StdHeader);
// Read low config register
PciAddress.AddressValue = NB_PSTATE_CFG_LOW_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader);
if (TargetNbPstate == 1) {
// If target is P1, the CPU MUST be in P0, otherwise the P1 settings
// cannot be realized. This is a programming error.
ASSERT (NbPsCtrlSts.Field.NbPs1Act == 0);
if (NbPsCfgLow.Field.NbPsCap == 1) {
// The part is capable of NB P-states. Transition to P1.
NbPsCfgLow.Field.NbPsForceSel = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader);
WaitForTransition = TRUE;
*CurrentNbFreq = RoundedDivision (NbPstateNumerator, NbPsCfgLow.Field.NbPs1NclkDiv);
} else {
// No NB P-states. Return FALSE, and set current frequency to P0.
*CurrentNbFreq = NbP0Cof;
ReturnStatus = FALSE;
}
} else {
// Target P0
*CurrentNbFreq = NbP0Cof;
if (NbPsCtrlSts.Field.NbPs1Act != 0) {
// Request transition to P0
NbPsCfgLow.Field.NbPsForceSel = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader);
WaitForTransition = TRUE;
}
}
if (WaitForTransition) {
// Ensure that the frequency has settled before returning to memory code.
PciAddress.AddressValue = NB_PSTATE_CTRL_STS_PCI_ADDR;
do {
LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlSts.Value, StdHeader);
} while (NbPsCtrlSts.Field.NbPs1Act != TargetNbPstate);
}
}
return ReturnStatus;
}
/*---------------------------------------------------------------------------------------*/
/**
* Performs integer division, and rounds the quotient up if the remainder is greater
* than or equal to 50% of the divisor.
*
* @param[in] Dividend The target MEMCLK in megahertz.
* @param[in] Divisor The target MEMCLK's register encoding.
*
* @return The rounded quotient
*/
UINT32
STATIC
RoundedDivision (
IN UINT32 Dividend,
IN UINT32 Divisor
)
{
UINT32 Quotient;
ASSERT (Divisor != 0);
Quotient = Dividend / Divisor;
if (((Dividend % Divisor) * 2) >= Divisor) {
Quotient++;
}
return Quotient;
}

104
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuCommonF14Utilities.h
View File

@@ -1,104 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family 14h specific utility functions
*
* Provides numerous utility functions specific to Family 14h
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x14
* @e \$Revision: 37640 $ @e \$Date: 2010-09-08 23:01:59 +0800 (Wed, 08 Sep 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _CPU_COMMON_F14_UTILITES_H_
#define _CPU_COMMON_F14_UTILITES_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
VOID
F14SetAgesaWarmResetFlag (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader,
IN WARM_RESET_REQUEST *Request
);
VOID
F14GetAgesaWarmResetFlag (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader,
OUT WARM_RESET_REQUEST *Request
);
VOID
F14GetApMailboxFromHardware (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT AP_MAILBOXES *ApMailboxInfo,
IN AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
F14NbPstateInit (
IN UINT32 TargetMemclk,
IN UINT32 TargetMemclkEncoded,
IN UINT32 TargetNbPstate,
OUT UINT32 *CurrentNbFreq,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _CPU_COMMON_F14_UTILITES_H_

155
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandId.c
View File

@@ -1,155 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD CPU BrandId related functions and structures.
*
* Contains code that provides CPU BrandId information
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 36556 $ @e \$Date: 2010-08-21 01:25:52 +0800 (Sat, 21 Aug 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuEarlyInit.h"
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14BRANDID_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
GetF14BrandIdString1 (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **BrandString1Ptr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
GetF14BrandIdString2 (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **BrandString2Ptr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
extern CPU_BRAND_TABLE *F14BrandIdString1Tables[];
extern CPU_BRAND_TABLE *F14BrandIdString2Tables[];
extern CONST UINT8 F14BrandIdString1TableCount;
extern CONST UINT8 F14BrandIdString2TableCount;
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Returns a table containing the appropriate beginnings of the CPU brandstring.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] BrandString1Ptr Points to the first entry in the table.
* @param[out] NumberOfElements Number of valid entries in the table.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF14BrandIdString1 (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **BrandString1Ptr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPU_BRAND_TABLE **TableEntryPtr;
TableEntryPtr = &F14BrandIdString1Tables[0];
*BrandString1Ptr = TableEntryPtr;
*NumberOfElements = F14BrandIdString1TableCount;
}
/*---------------------------------------------------------------------------------------*/
/**
* Returns a table containing the appropriate endings of the CPU brandstring.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] BrandString2Ptr Points to the first entry in the table.
* @param[out] NumberOfElements Number of valid entries in the table.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF14BrandIdString2 (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **BrandString2Ptr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPU_BRAND_TABLE **TableEntryPtr;
TableEntryPtr = &F14BrandIdString2Tables[0];
*BrandString2Ptr = TableEntryPtr;
*NumberOfElements = F14BrandIdString2TableCount;
}

161
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c
View File

@@ -1,161 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD CPU BrandId related functions and structures.
*
* Contains code that provides CPU BrandId information
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 45203 $ @e \$Date: 2011-01-13 12:36:39 -0700 (Thu, 13 Jan 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuEarlyInit.h"
#include "F14PackageType.h"
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
// String1
CONST CHAR8 ROMDATA str_AMD_C[] = "AMD C-";
CONST CHAR8 ROMDATA str_AMD_E[] = "AMD E-";
CONST CHAR8 ROMDATA str_AMD_G_T[] = "AMD G-T";
CONST CHAR8 ROMDATA str_AMD_Z[] = "AMD Z-";
// String2
CONST CHAR8 ROMDATA str___Processor[] = " Processor";
CONST CHAR8 ROMDATA str___0_Processor[] = "0 Processor";
CONST CHAR8 ROMDATA str_5_Processor[] = "5 Processor";
CONST CHAR8 ROMDATA str_0x_Processor[] = "0x Processor";
CONST CHAR8 ROMDATA str_5x_Processor[] = "5x Processor";
CONST CHAR8 ROMDATA str_x_Processor[] = "x Processor";
CONST CHAR8 ROMDATA str_L_Processor[] = "L Processor";
CONST CHAR8 ROMDATA str_N_Processor[] = "N Processor";
CONST CHAR8 ROMDATA str_R_Processor[] = "R Processor";
CONST CHAR8 ROMDATA str_E_Processor[] = "E Processor";
CONST CHAR8 ROMDATA str_0D_APU[] = "0D APU with Radeon(tm) HD Graphics";
CONST CHAR8 ROMDATA str_0_APU[] = "0 APU with Radeon(tm) HD Graphics";
CONST CHAR8 ROMDATA str_5_APU[] = "5 APU with Radeon(tm) HD Graphics";
CONST CHAR8 ROMDATA str_APU[] = " APU with Radeon(tm) HD Graphics";
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
CONST AMD_CPU_BRAND ROMDATA CpuF14OnBrandIdString1ArrayFt1[] =
{
// FT1
{1, 0, 1, ON_SOCKET_FT1, str_AMD_C, sizeof (str_AMD_C)},
{2, 0, 1, ON_SOCKET_FT1, str_AMD_C, sizeof (str_AMD_C)},
{1, 0, 2, ON_SOCKET_FT1, str_AMD_E, sizeof (str_AMD_E)},
{2, 0, 2, ON_SOCKET_FT1, str_AMD_E, sizeof (str_AMD_E)},
{2, 0, 3, ON_SOCKET_FT1, str_AMD_Z, sizeof (str_AMD_Z)},
{1, 0, 4, ON_SOCKET_FT1, str_AMD_G_T, sizeof (str_AMD_G_T)},
{2, 0, 4, ON_SOCKET_FT1, str_AMD_G_T, sizeof (str_AMD_G_T)}
}; //Cores, page, index, socket, stringstart, stringlength
CONST AMD_CPU_BRAND ROMDATA CpuF14OnBrandIdString2ArrayFt1[] =
{
// FT1
{1, 0, 0x01, ON_SOCKET_FT1, str___Processor, sizeof (str___Processor)},
{2, 0, 0x01, ON_SOCKET_FT1, str___Processor, sizeof (str___Processor)},
{1, 0, 0x02, ON_SOCKET_FT1, str___0_Processor, sizeof (str___0_Processor)},
{2, 0, 0x02, ON_SOCKET_FT1, str___0_Processor, sizeof (str___0_Processor)},
{1, 0, 0x03, ON_SOCKET_FT1, str_5_Processor, sizeof (str_5_Processor)},
{2, 0, 0x03, ON_SOCKET_FT1, str_5_Processor, sizeof (str_5_Processor)},
{1, 0, 0x04, ON_SOCKET_FT1, str_0x_Processor, sizeof (str_0x_Processor)},
{2, 0, 0x04, ON_SOCKET_FT1, str_0x_Processor, sizeof (str_0x_Processor)},
{1, 0, 0x05, ON_SOCKET_FT1, str_5x_Processor, sizeof (str_5x_Processor)},
{2, 0, 0x05, ON_SOCKET_FT1, str_5x_Processor, sizeof (str_5x_Processor)},
{1, 0, 0x06, ON_SOCKET_FT1, str_x_Processor, sizeof (str_x_Processor)},
{2, 0, 0x06, ON_SOCKET_FT1, str_x_Processor, sizeof (str_x_Processor)},
{1, 0, 0x07, ON_SOCKET_FT1, str_L_Processor, sizeof (str_L_Processor)},
{2, 0, 0x07, ON_SOCKET_FT1, str_L_Processor, sizeof (str_L_Processor)},
{1, 0, 0x08, ON_SOCKET_FT1, str_N_Processor, sizeof (str_N_Processor)},
{2, 0, 0x08, ON_SOCKET_FT1, str_N_Processor, sizeof (str_N_Processor)},
{1, 0, 0x09, ON_SOCKET_FT1, str_R_Processor, sizeof (str_R_Processor)},
{2, 0, 0x09, ON_SOCKET_FT1, str_0_APU, sizeof (str_0_APU)},
{1, 0, 0x0A, ON_SOCKET_FT1, str_0_APU, sizeof (str_0_APU)},
{2, 0, 0x0A, ON_SOCKET_FT1, str_5_APU, sizeof (str_5_APU)},
{1, 0, 0x0B, ON_SOCKET_FT1, str_5_APU, sizeof (str_5_APU)},
{2, 0, 0x0B, ON_SOCKET_FT1, str_APU, sizeof (str_APU)},
{1, 0, 0x0C, ON_SOCKET_FT1, str_APU, sizeof (str_APU)},
{2, 0, 0x0C, ON_SOCKET_FT1, str_E_Processor, sizeof (str_E_Processor)},
{1, 0, 0x0D, ON_SOCKET_FT1, str_0D_APU, sizeof (str_0D_APU)},
{2, 0, 0x0D, ON_SOCKET_FT1, str_0D_APU, sizeof (str_0D_APU)},
{1, 0, 0x0F, ON_SOCKET_FT1, 0, 0}, //Size 0 for no suffix
{2, 0, 0x0F, ON_SOCKET_FT1, 0, 0}, //Size 0 for no suffix
}; //Cores, page, index, socket, stringstart, stringlength
CONST CPU_BRAND_TABLE ROMDATA F14OnBrandIdString1ArrayFt1 = {
(sizeof (CpuF14OnBrandIdString1ArrayFt1) / sizeof (AMD_CPU_BRAND)),
CpuF14OnBrandIdString1ArrayFt1
};
CONST CPU_BRAND_TABLE ROMDATA F14OnBrandIdString2ArrayFt1 = {
(sizeof (CpuF14OnBrandIdString2ArrayFt1) / sizeof (AMD_CPU_BRAND)),
CpuF14OnBrandIdString2ArrayFt1
};

131
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c
View File

@@ -1,131 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 ROM Execution Cache Defaults
*
* Contains default values for ROM execution cache setup
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x14
* @e \$Revision: 36376 $ @e \$Date: 2010-08-18 00:17:10 +0800 (Wed, 18 Aug 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuCacheInit.h"
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14CACHEDEFAULTS_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
GetF14CacheInfo (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **CacheInfoPtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
#define BSP_STACK_SIZE 16384
#define CORE0_STACK_SIZE 16384
#define CORE1_STACK_SIZE 4096
#define MEM_TRAINING_BUFFER_SIZE 16384
#define VAR_MTRR_MASK 0x0000000FFFFFFFFF
#define HEAP_BASE_MASK 0x0000000FFFFFFFFF
#define SHARED_MEM_SIZE 0
CONST CACHE_INFO ROMDATA CpuF14CacheInfo =
{
BSP_STACK_SIZE,
CORE0_STACK_SIZE,
CORE1_STACK_SIZE,
MEM_TRAINING_BUFFER_SIZE,
SHARED_MEM_SIZE,
VAR_MTRR_MASK,
VAR_MTRR_MASK,
HEAP_BASE_MASK,
InfiniteExe
};
/*---------------------------------------------------------------------------------------*/
/**
* Returns the family specific properties of the cache, and its usage.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] CacheInfoPtr Points to the cache info properties on exit.
* @param[out] NumberOfElements Will be one to indicate one entry.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF14CacheInfo (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **CacheInfoPtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
*NumberOfElements = 1;
*CacheInfoPtr = &CpuF14CacheInfo;
}

326
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Dmi.c
View File

@@ -1,326 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD DMI Record Creation API, and related functions.
*
* Contains code that produce the DMI related information.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 38893 $ @e \$Date: 2010-10-01 23:54:37 +0800 (Fri, 01 Oct 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuRegisters.h"
#include "OptionDmi.h"
#include "cpuLateInit.h"
#include "cpuF14PowerMgmt.h"
#include "cpuFamilyTranslation.h"
#include "cpuPstateTables.h"
#include "cpuF14Utilities.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14DMI_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable;
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
DmiF14GetInfo (
IN OUT CPU_TYPE_INFO *CpuInfoPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT8
DmiF14GetVoltage (
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT16
DmiF14GetMaxSpeed (
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT16
DmiF14GetExtClock (
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
DmiF14GetMemInfo (
IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/* -----------------------------------------------------------------------------*/
/**
*
* DmiF14GetInfo
*
* Get CPU type information
*
* @param[in,out] CpuInfoPtr Pointer to CPU_TYPE_INFO struct.
* @param[in] StdHeader Standard Head Pointer
*
*/
VOID
DmiF14GetInfo (
IN OUT CPU_TYPE_INFO *CpuInfoPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPUID_DATA CpuId;
LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader);
CpuInfoPtr->ExtendedFamily = (UINT8) (CpuId.EAX_Reg >> 20) & 0xFF; // bit 27:20
CpuInfoPtr->ExtendedModel = (UINT8) (CpuId.EAX_Reg >> 16) & 0xF; // bit 19:16
CpuInfoPtr->BaseFamily = (UINT8) (CpuId.EAX_Reg >> 8) & 0xF; // bit 11:8
CpuInfoPtr->BaseModel = (UINT8) (CpuId.EAX_Reg >> 4) & 0xF; // bit 7:4
CpuInfoPtr->Stepping = (UINT8) (CpuId.EAX_Reg & 0xF); // bit 3:0
CpuInfoPtr->PackageType = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28
CpuInfoPtr->BrandId.Pg = (UINT8) (CpuId.EBX_Reg >> 15) & 0x1; // bit 15
CpuInfoPtr->BrandId.String1 = (UINT8) (CpuId.EBX_Reg >> 11) & 0xF; // bit 14:11
CpuInfoPtr->BrandId.Model = (UINT8) (CpuId.EBX_Reg >> 4) & 0x7F; // bit 10:4
CpuInfoPtr->BrandId.String2 = (UINT8) (CpuId.EBX_Reg & 0xF); // bit 3:0
LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuId, StdHeader);
CpuInfoPtr->TotalCoreNumber = (UINT8) (CpuId.ECX_Reg & 0xFF); // bit 7:0
CpuInfoPtr->EnabledCoreNumber = (UINT8) (CpuId.ECX_Reg & 0xFF); // bit 7:0
switch (CpuInfoPtr->PackageType) {
case ON_SOCKET_FT1:
CpuInfoPtr->ProcUpgrade = P_UPGRADE_NONE;
break;
default:
CpuInfoPtr->ProcUpgrade = P_UPGRADE_UNKNOWN;
break;
}
}
/* -----------------------------------------------------------------------------*/
/**
*
* DmiF14GetVoltage
*
* Get the voltage value according to SMBIOS SPEC's requirement.
*
* @param[in] StdHeader Standard Head Pointer
*
* @retval Voltage - CPU Voltage.
*
*/
UINT8
DmiF14GetVoltage (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 MaxVid;
UINT8 Voltage;
UINT8 NumberBoostStates;
UINT64 MsrData;
PCI_ADDR TempAddr;
CPU_LOGICAL_ID CpuFamilyRevision;
CPB_CTRL_REGISTER CpbCtrl;
// Voltage = 0x80 + (voltage at boot time * 10)
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) == 0) {
TempAddr.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, TempAddr, &CpbCtrl, StdHeader); // F4x15C
NumberBoostStates = (UINT8) CpbCtrl.NumBoostStates;
} else {
NumberBoostStates = 0;
}
LibAmdMsrRead ((MSR_PSTATE_0 + NumberBoostStates), &MsrData, StdHeader);
MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid);
if ((MaxVid >= 0x7C) && (MaxVid <= 0x7F)) {
Voltage = 0;
} else {
Voltage = (UINT8) ((15500 - (125 * MaxVid) + 500) / 1000);
}
Voltage += 0x80;
return (Voltage);
}
/* -----------------------------------------------------------------------------*/
/**
*
* DmiF14GetMaxSpeed
*
* Get the Max Speed
*
* @param[in] StdHeader Standard Head Pointer
*
* @retval MaxSpeed - CPU Max Speed.
*
*/
UINT16
DmiF14GetMaxSpeed (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 NumBoostStates;
UINT32 P0Frequency;
UINT32 PciData;
PCI_ADDR PciAddress;
PSTATE_CPU_FAMILY_SERVICES *FamilyServices;
CPU_LOGICAL_ID CpuFamilyRevision;
FamilyServices = NULL;
GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL);
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) == 0) {
PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_4, 0x15C);
LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
NumBoostStates = (UINT8) ((PciData >> 2) & 7);
} else {
NumBoostStates = 0;
}
FamilyServices->GetPstateFrequency (FamilyServices, NumBoostStates, &P0Frequency, StdHeader);
return ((UINT16) P0Frequency);
}
/* -----------------------------------------------------------------------------*/
/**
*
* DmiF14GetExtClock
*
* Get the external clock Speed
*
* @param[in, out] StdHeader Standard Head Pointer
*
* @retval ExtClock - CPU external clock Speed.
*
*/
UINT16
DmiF14GetExtClock (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return (EXTERNAL_CLOCK_100MHZ);
}
/* -----------------------------------------------------------------------------*/
/**
*
* DmiF14GetMemInfo
*
* Get memory information.
*
* @param[in,out] CpuGetMemInfoPtr Pointer to CPU_GET_MEM_INFO struct.
* @param[in] StdHeader Standard Head Pointer
*
*/
VOID
DmiF14GetMemInfo (
IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
// Ontario only has one DCT and does NOT support ECC DIMM
CpuGetMemInfoPtr->EccCapable = FALSE;
// Partition Row Position - 2 is for single channel memory
CpuGetMemInfoPtr->PartitionRowPosition = 2;
}
/*---------------------------------------------------------------------------------------
* Processor Family Table
*
* Note: 'x' means we don't care this field
* 046h = "AMD C-Series Processor"
* 047h = "AMD E-Series Processor"
* 048h = "AMD S-Series Processor"
* 049h = "AMD G-Series Processor"
* 002h = "Unknown"
*-------------------------------------------------------------------------------------*/
CONST DMI_BRAND_ENTRY ROMDATA Family14BrandList[] =
{
// Brand --> DMI ID translation table
// PackageType, PgOfBrandId, NumberOfCores, String1ofBrandId, ValueSetToDmiTable
{0, 0, 'x', 1, 0x46},
{0, 0, 'x', 2, 0x47},
{0, 0, 'x', 4, 0x49},
{'x', 'x', 'x', 'x', 0x02}
};
CONST PROC_FAMILY_TABLE ROMDATA ProcFamily14DmiTable =
{
AMD_FAMILY_14, // ID for Family 14h
&DmiF14GetInfo, // Transfer vectors for family
&DmiF14GetVoltage, // specific routines (above)
&DmiF14GetMaxSpeed,
&DmiF14GetExtClock,
&DmiF14GetMemInfo, // Get memory information
ARRAY_SIZE(Family14BrandList), // Number of entries in following table
&Family14BrandList[0]
};
/*---------------------------------------------------------------------------------------
* L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------
*/

149
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14LowPowerInit.c
View File

@@ -1,149 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 Optimizations for lower power consumption
*
* Sets some registers for tablet parts at AmdInitEarly.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/F14
* @e \$Revision: 45578 $ @e \$Date: 2011-01-18 19:20:41 -0500 (Tue, 18 Jan 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuFamilyTranslation.h"
#include "cpuF14PowerMgmt.h"
#include "cpuF14LowPowerInit.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14LOWPOWERINIT_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Family 14h model 0 - 0xF core 0 entry point for programming registers for lower
* power consumption.
*
* Set up D18F6x94[CpuPstateThrEn, CpuPstateThr], and D18F4x134[IntRateCC6DecrRate
* according to the BKDG.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParams Service parameters
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F14OptimizeForLowPowerInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 NumBoostStates;
UINT32 LocalPciRegister;
BOOLEAN OptimizeForLowPower;
BOOLEAN IsRevC;
PCI_ADDR PciAddress;
CPU_LOGICAL_ID CpuFamilyRevision;
PciAddress.AddressValue = PRODUCT_INFO_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if ((((PRODUCT_INFO_REGISTER *) &LocalPciRegister)->LowPowerDefault == 1) &&
(CpuEarlyParams->PlatformConfig.PlatformProfile.PlatformPowerPolicy == BatteryLife)) {
OptimizeForLowPower = TRUE;
} else {
OptimizeForLowPower = FALSE;
}
// Get F4x15C [4:2] NumBoostStates
// Get IsRevC
NumBoostStates = 0;
IsRevC = FALSE;
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
if ((CpuFamilyRevision.Revision & AMD_F14_ON_Cx) != 0) {
IsRevC = TRUE;
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
NumBoostStates = (UINT8) ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates;
}
// F6x94[2:0] CpuPstateThr
PciAddress.AddressValue = NB_PSTATE_CFG_HIGH_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (OptimizeForLowPower) {
((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 0;
} else {
if (NumBoostStates == 0) {
((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 1;
} else {
((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 2;
}
}
// F6x94[3] CpuPstateThrEn = 1
((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThrEn = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
// F4x134[31:27] IntRateCC6DecrRate
PciAddress.AddressValue = CSTATE_MON_CTRL3_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((CSTATE_MON_CTRL3_REGISTER *) &LocalPciRegister)->IntRateCC6DecrRate = (OptimizeForLowPower || IsRevC) ? 0x18 : 0x8;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}

77
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14LowPowerInit.h
View File

@@ -1,77 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 Optimizations for Low Power
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/F14
* @e \$Revision: 45578 $ @e \$Date: 2011-01-18 19:20:41 -0500 (Tue, 18 Jan 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef _F14_LOW_POWER_INIT_H_
#define _F14_LOW_POWER_INIT_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
VOID
F14OptimizeForLowPowerInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _F14_LOW_POWER_INIT_H_

213
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14MsrTables.c
View File

@@ -1,213 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 MSR tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 48588 $ @e \$Date: 2011-03-10 08:57:36 -0700 (Thu, 10 Mar 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Table.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14MSRTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] =
{
// M S R T a b l e s
// ----------------------
// MC0_CTL_MASK (0xC0010044)
// bit[6] = 1, erratum #628
{
MsrRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ON_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MSR_MC0_CTL_MASK, // MSR Address
0x0000000000000040, // OR Mask
0x0000000000000040, // NAND Mask
}}
},
// MSR_TOM2 (0xC001001D)
// bits[63:0] - TOP_MEM2 = 0
{
MsrRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MSR_TOM2, // MSR Address
0x0000000000000000, // OR Mask
0xFFFFFFFFFFFFFFFF, // NAND Mask
}}
},
// MSR_SYS_CFG (0xC0010010)
// bit[21] - MtrrTom2En = 1
{
MsrRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MSR_SYS_CFG, // MSR Address
(1 << 21), // OR Mask
(1 << 21), // NAND Mask
}}
},
// MSR_CPUID_EXT_FEATS (0xC0011005)
// bit[41] - OSVW = 0
{
MsrRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MSR_CPUID_EXT_FEATS, // MSR Address
0x0000000000000000, // OR Mask
0x0000020000000000, // NAND Mask
}}
},
// MSR_OSVW_ID_Length (0xC0010140)
// bit[15:0] = 4
{
MsrRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MSR_OSVW_ID_Length, // MSR Address
0x0000000000000004, // OR Mask
0x000000000000FFFF, // NAND Mask
}}
},
// MSR_HWCR (0xC0010015)
// Do not set bit[24] = 1, it will be set in AmdInitPost.
// This MSR should be set after the code that most errata would be applied in
// MSR_MC0_CTL (0x00000400)
// bits[63:0] = 0xFFFFFFFFFFFFFFFF
{
MsrRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MSR_MC0_CTL, // MSR Address
0xFFFFFFFFFFFFFFFF, // OR Mask
0xFFFFFFFFFFFFFFFF, // NAND Mask
}}
},
// MSR_LS_CFG (0xC0011020)
// bit[36] Reserved = 1, workaround for erratum #530
// bit[25] Reserved = 1, workaround for erratum #551
{
MsrRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MSR_LS_CFG, // MSR Address
0x0000001002000000, // OR Mask
0x0000001002000000, // NAND Mask
}}
},
// MSR_DC_CFG (0xC0011022)
// bit[57:56] Reserved = 2
{
MsrRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MSR_DC_CFG, // MSR Address
0x0200000000000000, // OR Mask
0x0300000000000000, // NAND Mask
}}
}
};
CONST REGISTER_TABLE ROMDATA F14MsrRegisterTable = {
AllCores,
(sizeof (F14MsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
(TABLE_ENTRY_FIELDS *) &F14MsrRegisters,
};

713
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PciTables.c
View File

@@ -1,713 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 PCI tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x14
* @e \$Revision: 38376 $ @e \$Date: 2010-09-23 11:39:55 +0800 (Thu, 23 Sep 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Table.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14PCITABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
// P C I T a b l e s
// ----------------------
STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
{
// Function 0 - Link Config
// D18F0x68 - Link Transaction Control
// bit[11] RespPassPW = 1
// bits[19:17] for 8bit APIC config
// bits[22:21] DsNpReqLmt = 1
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address
0x002E0800, // regData
0x006E0800, // regMask
}}
},
// Function 2 - DRAM Controller
// D18F2xB8
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_2, 0xB8), // Address
0x00000000, // regData
0xF000F000, // regMask
}}
},
// D18F2xBC
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_2, 0xBC), // Address
0x00000000, // regData
0xC0000000, // regMask
}}
},
// D18F2x118 - Memory Controller Configuration Low
// bits[7:6], MctPriHiWr = 10b
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118), // Address
0x00000080, // regData
0x000000C0, // regMask
}}
},
// D18F2x11C - Memory Controller Configuration High
// bits[24:22], PrefConf = 1
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_2, 0x11C), // Address
0x00400000, // regData
0x01C00000, // regMask
}}
},
// Function 3 - Misc. Control
// D18F3x40 - MCA NB Control
// bit[8] MstrAbortEn = 1
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x40), // Address
0x00000100, // regData
0x00000100, // regMask
}}
},
// D18F3x44 - MCA NB Configuration
// bit[27] NbMcaToMstCpuEn = 1
// bit[25] DisPciCfgCpuErrRsp = 1
// bit[21] SyncOnAnyErrEn = 1
// bit[20] SyncOnWDTEn = 1
// bits[13:12] WDTBaseSel = 0
// bits[11:9] WDTCntSel[2:0] = 0
// bit[6] CpuErrDis = 1
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x44), // Address
0x0A300040, // regData
0x0A303E40, // regMask
}}
},
// D18F3x84 - ACPI Power State Control High
// bit[18] Smaf6DramMemClkTri = 1
// bit[17] Smaf6DramSr = 1
// bit[2] Smaf4DramMemClkTri = 1
// bit[1] Smaf4DramSr = 1
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84), // Address
0x00060006, // regData
0x00060006, // regMask
}}
},
// D18F3x8C - NB Configuration High
// bit[26] EnConvertToNonIsoc = 1
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x8C), // Address
0x04000000, // regData
0x04000000, // regMask
}}
},
// D18F3xA0 - Power Control Miscellaneous
// bit[9] SviHighFreqSel = 1
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address
0x00000200, // regData
0x00000200, // regMask
}}
},
// D18F3xA4 - Reported Temperature Control
// bits[12:8] PerStepTimeDn = 0xF
// bit[7] TmpSlewDnEn = 1
// bits[6:5] TmpMaxDiffUp = 0x3
// bits[4:0] PerStepTimeUp = 0xF
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA4), // Address
0x00000FEF, // regData
0x00001FFF, // regMask
}}
},
// D18F3xD4 - Clock Power Timing Control 0
// bits[11:8] ClkRampHystSel = 0xF
// bits[15:12] OnionOutHyst = 0x4
// bit[17] ClockGatingEnDram = 1
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4), // Address
0x00024F00, // regData
0x0002FF00, // regMask
}}
},
// D18F3xDC - Clock Power Timing Control 2
// bits[29:27] NbClockGateHyst = 3
// bit[30] NbClockGateEn = 0 - erratum #596
// bit[31] CnbCifClockGateEn = 1
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address
0x98000000, // regData
0xF8000000, // regMask
}}
},
// D18F3x180 - Extended NB MCA Configuration
// bit[2] WDTCntSel[3] = 0
// bit[5] DisPciCfgCpuMstAbtRsp = 1
// bit[21] SyncFloodOnCpuLeakErr = 1
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address
0x00200020, // regData
0x00200024, // regMask
}}
},
// D18F3x188 - NB Extended Configuration
// bit[21] EnCpuSerWrBehindIoRd = 0
// bit[23] EnCpuSerRdBehindIoRd = 0
// bits[27:24] FeArbCpuWeightOverLoPrio = 0x0B
// bits[31:28] FeArbCpuWeightOverHiPrio = 1
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
0x1B000000, // regData
0xFFA00000, // regMask
}}
},
// Function 4 - Extended Misc. Control
// D18F4x118 - C-state Control 1
// bits[2:0] CstAct0 = 0
// bits[10:8] CstAct1 = 0
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x118), // Address
0x00000000, // regData
0x00000707, // regMask
}}
},
// D18F4x124 - C-state Monitor Control 1
// bit[15] TimerTickIntvlScale = 1
// bit[16] TrackTimerTickInterEn = 1
// bit[17] IntMonCC6En = 1
// bits[21:18] IntMonCC6Lmt = 4
// bit[22] IntMonPkgC6En = 0
// bits[26:23] IntMonPkgC6Lmt = 0x0A
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x124), // Address
0x05138000, // regData
0x07FF8000, // regMask
}}
},
// D18F4x134 - C-state Monitor Control 3
// bits[3:0] IntRatePkgC6MaxDepth = 0
// bits[7:4] IntRatePkgC6Threshold = 0
// bits[10:8] IntRatePkgC6BurstLen = 1
// bits[15:11] IntRatePkgC6DecrRate = 0x0A
// bits[19:16] IntRateCC6MaxDepth = 5
// bits[23:20] IntRateCC6Threshold = 4
// bits[26:24] IntRateCC6BurstLen = 5
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x134), // Address
0x05455100, // regData
0x07FFFFFF, // regMask
}}
},
// D18F4x13C - SMAF Code DID 1
// bits[4:0] Smaf4Did = 0x0F
// bits[20:16] Smaf6Did = 0x0F
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x13C), // Address
0x000F000F, // regData
0x001F001F, // regMask
}}
},
// D18F4x1A4 - C-state Monitor Mask
// bits[7:0] IntRateMonMask = 0xFC
// bits[15:8] TimerTickMonMask = 0xFF
// bits[23:16] NonC0MonMask = 0xFF
// bits[31:24] C0MonMask = 0xFF
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1A4), // Address
0xFFFFFFFC, // regData
0xFFFFFFFF, // regMask
}}
},
// D18F4x1A8 - CPU State Power Management Dynamic Control 0
// bits[4:0] SingleHaltCpuDid = 0x1E
// bits[9:5] AllHaltCpuDid = 0x1F
// bit[15] CpuProbEn = 0
// bits[22:20] PServiceTmr = 1
// bit[23] PServiceTmrEn = 1
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1A8), // Address
0x009003FE, // regData
0x00F083FF, // regMask
}}
},
// D18F4x1AC - CPU State Power Management Dynamic Control 1
// bits[9:5] C6Did = 0x1F
// bits[28] CoreC6Dis = 1
// bits[29] PkgC6Dis = 1
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1AC), // Address
0x300003E0, // regData
0x300003E0, // regMask
}}
},
// D18F6x50 - Configuration Register Access Control
// bit[1] CfgAccAddrMode = 0
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x50), // Address
0x00000000, // regData
0x00000002, // regMask
}}
},
// D18F6x54 - DRAM Arbitration Control FEQ Collision
// bits[7:0] FeqLoPrio = 0x20
// bits[15:8] FeqMedPrio = 0x10
// bits[23:16] FeqHiPrio = 8
// bit[31] PpMode = 0
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x54), // Address
0x00081020, // regData
0x80FFFFFF, // regMask
}}
},
// D18F6x58 - DRAM Arbitration Control Display Collision
// bits[7:0] DispLoPrio = 0x40
// bits[15:8] DispMedPrio = 0x20
// bits[23:16] DispHiPrio = 0x10
// bits[31:24] DispUrgPrio = 0
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x58), // Address
0x00102040, // regData
0xFFFFFFFF, // regMask
}}
},
// D18F6x5C - DRAM Arbitration Control FEQ Write Protect
// bits[7:0] FeqLoPrio = 0x20
// bits[15:8] FeqMedPrio = 0x10
// bits[23:16] FeqHiPrio = 0x08
// bit[31] PpMode = 0
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x5C), // Address
0x00081020, // regData
0x80FFFFFF, // regMask
}}
},
// D18F6x60 - DRAM Arbitration Control Display Write Protect
// bits[7:0] DispLoPri = 0x20
// bits[15:8] DispMedPrio = 0x10
// bits[23:16] DispHiPrio = 0x08
// bits[31:24] DispUrgPrio = 0
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x60), // Address
0x00081020, // regData
0xFFFFFFFF, // regMask
}}
},
// D18F6x64 - DRAM Arbitration Control FEQ Read Protect
// bits[7:0] FeqLoPrio = 0x10
// bits[15:8] FeqMedPrio = 8
// bits[23:16] FeqHiPrio = 4
// bit[31] PpMode = 0
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x64), // Address
0x00040810, // regData
0x80FFFFFF, // regMask
}}
},
// D18F6x68 - DRAM Arbitration Control Display Read Protect
// bits[7:0] DispLoPrio = 0x10
// bits[15:8] DispMedPrio = 8
// bits[23:16] DispHiPrio = 4
// bits[31:24] DispUrgPrio = 0
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x68), // Address
0x00040810, // regData
0xFFFFFFFF, // regMask
}}
},
// D18F6x6C - DRAM Arbitration Control FEQ Fairness Timer
// bits[7:0] FeqLoPrio = 0x80
// bits[15:8] FeqMedPrio = 0x40
// bits[23:16] FeqHiPrio = 0x20
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x6C), // Address
0x00204080, // regData
0x00FFFFFF, // regMask
}}
},
// D18F6x70 - DRAM Arbitration Control Display Fairness Timer
// bits[7:0] DispLoPrio = 0x80
// bits[15:8] DispMedPrio = 0x40
// bits[23:16] DispHiPrio = 0x20
// bits[31:24] DispUrPrio = 0
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x70), // Address
0x00204080, // regData
0xFFFFFFFF, // regMask
}}
},
// D18F6x74 - Dram Idle Page Close Limit
// bits[40] IdleLimit = 0x1E
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x74), // Address
0x0000001E, // regData
0x0000001F, // regMask
}}
},
// D18F6x78 - Dram Prioritization and Arbitration Control
// bits[1:0] DispDbePrioEn = 3
// bit[2] FeqDbePrioEn = 1
// bit[3] DispArbCtrl = 0
// bits[5:4] GlcEosDet = 3
// bit[6] GlcEosDetDis = 0
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x78), // Address
0x00000037, // regData
0x0000007F, // regMask
}}
},
// D18F6x90 - NB P-state Config Low
// As part of BIOS Requirements for NB P-state Initialization
// bit[30] NbPsCtrlDis = 1
// bit[29] NbPsForceSel = 0
// bit[28] NbPsForceReq = 1
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x90), // Address
0x50000000, // regData
0x70000000, // regMask
}}
},
// D18F6x94 - NB P-state Config High
// bits[25:23] NbPsC0Timer = 4
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x94), // Address
0x02000000, // regData
0x03800000, // regMask
}}
},
// D18F6x9C - NCLK Reduction Control
// bits[6:0] NclkRedDiv = 0x60
// bit[7] NclkRedSelfRefrAlways = 1
// bit[8] NclkRampWithDllRelock = 1
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x9C), // Address
0x000001E0, // regData
0x000001FF, // regMask
}}
}
};
CONST REGISTER_TABLE ROMDATA F14PciRegisterTable = {
PrimaryCores,
(sizeof (F14PciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
F14PciRegisters,
};

102
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PerCorePciTables.c
View File

@@ -1,102 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 Per Core PCI tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x14
* @e \$Revision: 36592 $ @e \$Date: 2010-08-21 05:31:55 +0800 (Sat, 21 Aug 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Table.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14PERCOREPCITABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
// Per Core P C I T a b l e s
// ----------------------
STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PerCorePciRegisters[] =
{
// D18F3x1CC - IBS Control
// bits[3:0] LvtOffset = 0
// bit[8] LvtOffsetVal = 1
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1CC), // Address
0x00000100, // regData
0x0000010F, // regMask
}}
}
};
CONST REGISTER_TABLE ROMDATA F14PerCorePciRegisterTable = {
AllCores,
(sizeof (F14PerCorePciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
F14PerCorePciRegisters,
};

454
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerCheck.c
View File

@@ -1,454 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 P-State power check
*
* Performs the "Processor-Systemboard Power Delivery Compatibility Check" as
* described in the BKDG.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F14
* @e \$Revision: 46951 $ @e \$Date: 2011-02-11 12:37:59 -0700 (Fri, 11 Feb 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuF14PowerMgmt.h"
#include "cpuRegisters.h"
#include "cpuApicUtilities.h"
#include "cpuServices.h"
#include "GeneralServices.h"
#include "cpuEarlyInit.h"
#include "cpuFamilyTranslation.h"
#include "cpuF14PowerCheck.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14POWERCHECK_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
STATIC
F14PmPwrCheckCore (
IN VOID *ErrorData,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
STATIC
F14PmPwrChkCopyPstate (
IN UINT8 Dest,
IN UINT8 Src,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Family 14h Ontario core 0 entry point for performing the family 14h Ontario Processor-
* Systemboard Power Delivery Check.
*
* The steps are as follows:
* 1. Starting with hardware P0, loop through all P-states until a passing state is
* found. A passing state is one in which the current required by the
* CPU is less than the maximum amount of current that the system can
* provide to the CPU. If P0 is under the limit, no further action is
* necessary.
* 2. If at least one P-State is under the limit & at least one P-State is
* over the limit, the BIOS must:
* a. Program D18F4x15C[BoostSrc]=0.
* b. If the processor's current P-State is disabled by the power check,
* then the BIOS must request a transition to an enabled P-state
* using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate]
* to reflect the new value.
* c. Copy the contents of the enabled P-state MSRs to the highest
* performance P-state locations.
* d. Request a P-state transition to the P-state MSR containing the
* COF/VID values currently applied.
* e. Adjust the following P-state parameters affected by the P-state
* MSR copy by subtracting the number of P-states that are disabled
* by the power check.
* 1. D18F3x64[HtcPstateLimit]
* 2. D18F3xDC[PstateMaxVal]
* 3. If all P-States are over the limit, the BIOS must:
* a. Program D18F4x15C[BoostSrc]=0.
* b. If the processor's current P-State is != D18F3xDC[PstateMaxVal], then
* write D18F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for
* MSRC001_0063[CurPstate] to reflect the new value.
* c. If D18F3xDC[PstateMaxVal]!= 000b, copy the contents of the P-state
* MSR pointed to by D18F3xDC[PstateMaxVal] to MSRC001_0064 and set
* MSRC001_0064[PstateEn]
* d. Write 000b to MSRC001_0062[PstateCmd] and wait for MSRC001_0063
* [CurPstate] to reflect the new value.
* e. Adjust the following P-state parameters to zero:
* 1. D18F3x64[HtcPstateLimit]
* 2. D18F3xDC[PstateMaxVal]
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParams Service parameters.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F14PmPwrCheck (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 DisHwPsNum;
UINT8 DisSwPsNum;
UINT8 PsMaxVal;
UINT8 Pstate;
UINT8 PstateLimit;
UINT8 NumberBoostStates;
UINT32 ProcIddMax;
UINT32 Socket;
UINT32 Module;
UINT32 Core;
PCI_ADDR PciAddress;
UINT64 LocalMsrRegister;
BOOLEAN ThermalPstateEn;
NB_CAPS_REGISTER NbCaps;
HTC_REGISTER HtcReg;
CLK_PWR_TIMING_CTRL2_REGISTER ClkPwrTimingCtrl2;
CPB_CTRL_REGISTER CpbCtrl;
CPU_LOGICAL_ID CpuFamilyRevision;
AP_TASK TaskPtr;
AGESA_STATUS IgnoredSts;
PWRCHK_ERROR_DATA ErrorData;
// get the socket number
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
ErrorData.SocketNumber = (UINT8) Socket;
ASSERT (Core == 0);
// save ThermalPstateEn
// TRUE if the P-state indicated by D18F3x64[HtcPstateLimit] is enabled;
// FALSE otherwise.
PciAddress.AddressValue = HTC_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader); // D18F3x64
LibAmdMsrRead (PS_REG_BASE + HtcReg.HtcPstateLimit, &LocalMsrRegister, StdHeader);
if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
ThermalPstateEn = TRUE;
} else {
ThermalPstateEn = FALSE;
}
// get the Max P-state value
for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) {
LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &LocalMsrRegister, StdHeader);
if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
break;
}
}
ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1);
// get NumberBoostStates
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) != 0) {
NumberBoostStates = 0;
} else {
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CpbCtrl, StdHeader); // D18F4x15C
NumberBoostStates = (UINT8) CpbCtrl.NumBoostStates;
}
// update PstateMaxVal if warranted by HtcPstateLimit
PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader);
if (NbCaps.HtcCapable == 1) {
if (HtcReg.HtcTmpLmt != 0) {
PciAddress.AddressValue = CPTC2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // D18F3xDC
if (HtcReg.HtcPstateLimit > ClkPwrTimingCtrl2.PstateMaxVal) {
ClkPwrTimingCtrl2.PstateMaxVal = HtcReg.HtcPstateLimit;
LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // D18F3xDC
}
}
}
DisHwPsNum = 0;
for (Pstate = 0; Pstate < ErrorData.HwPstateNumber; Pstate++) {
if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) {
if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit) {
// Add to event log the Pstate that exceeded the current limit
PutEventLog (AGESA_WARNING,
CPU_EVENT_PM_PSTATE_OVERCURRENT,
Socket, Pstate, 0, 0, StdHeader);
DisHwPsNum++;
} else {
break;
}
}
}
// get the number of software Pstate that is disabled by delivery check
if (NumberBoostStates < DisHwPsNum) {
DisSwPsNum = DisHwPsNum - NumberBoostStates;
} else {
DisSwPsNum = 0;
}
// If all P-state registers are disabled, move P[PsMaxVal] to P0
// and transition to P0, then wait for CurPstate = 0
ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisHwPsNum);
// We only need to log this event on the BSC
if (ErrorData.AllowablePstateNumber == 0) {
PutEventLog (AGESA_FATAL,
CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT,
Socket, 0, 0, 0, StdHeader);
}
if (DisHwPsNum != 0) {
// Program F4x15C[BoostSrc] = 0
if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) == 0) {
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CpbCtrl, StdHeader); // D18F4x15C
CpbCtrl.BoostSrc = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &CpbCtrl, StdHeader); // D18F4x15C
}
TaskPtr.FuncAddress.PfApTaskI = F14PmPwrCheckCore;
TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PWRCHK_ERROR_DATA);
TaskPtr.DataTransfer.DataPtr = &ErrorData;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParams);
// Final Step
// D18F3x64[HtPstatelimit] -= disPsNum
// D18F3xDC[PstateMaxVal]-= disPsNum
PciAddress.AddressValue = HTC_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader); // D18F3x64
PciAddress.AddressValue = NB_CAPS_PCI_ADDR; // D18F3xE8
LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader);
if (ThermalPstateEn || HtcReg.HtcTmpLmt == 0 || NbCaps.HtcCapable == 0) {
PstateLimit = (UINT8) HtcReg.HtcPstateLimit;
if (PstateLimit > DisHwPsNum) {
PstateLimit = (UINT8) (PstateLimit - DisSwPsNum);
} else {
PstateLimit = NumberBoostStates;
}
HtcReg.HtcPstateLimit = PstateLimit;
PciAddress.AddressValue = HTC_PCI_ADDR;
LibAmdPciWrite (AccessWidth32, PciAddress, &HtcReg, StdHeader); // D18F3x64
PciAddress.AddressValue = CPTC2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // D18F3xDC
PstateLimit = (UINT8) ClkPwrTimingCtrl2.PstateMaxVal;
if (PstateLimit > DisHwPsNum) {
PstateLimit = (UINT8) (PstateLimit - DisSwPsNum);
} else {
PstateLimit = NumberBoostStates;
}
ClkPwrTimingCtrl2.PstateMaxVal = PstateLimit;
LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // D18F3xDC
}
}
}
/*---------------------------------------------------------------------------------------*/
/**
* Core-level error handler called if any p-states were determined to be out
* of range for the mother board.
*
* This function implements steps 2b-d and 3b-d on each core.
*
* @param[in] ErrorData Details about the error condition.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
F14PmPwrCheckCore (
IN VOID *ErrorData,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 i;
UINT8 HardwarePsMaxVal;
UINT8 DisHwPsNum;
UINT8 DisSwPsNum;
UINT8 CurrentSoftwarePs;
UINT8 CurrentHardwarePs;
UINT8 NumberBoostStates;
UINT64 LocalMsrRegister;
CPU_LOGICAL_ID CpuFamilyRevision;
PCI_ADDR PciAddress;
CPB_CTRL_REGISTER CpbCtrl;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
HardwarePsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1);
DisHwPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber -
((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber);
LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader);
CurrentSoftwarePs = (UINT8) (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate);
if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) != 0) {
NumberBoostStates = 0;
} else {
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CpbCtrl, StdHeader); // D18F4x15C
NumberBoostStates = (UINT8) CpbCtrl.NumBoostStates;
}
CurrentHardwarePs = CurrentSoftwarePs + NumberBoostStates;
if (NumberBoostStates < DisHwPsNum) {
DisSwPsNum = DisHwPsNum - NumberBoostStates;
} else {
DisSwPsNum = 0;
}
if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) {
// Step 1
// Transition to Pstate Max if not there already
if (CurrentHardwarePs != HardwarePsMaxVal) {
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (HardwarePsMaxVal - NumberBoostStates), (BOOLEAN) TRUE, StdHeader);
CurrentSoftwarePs = HardwarePsMaxVal - NumberBoostStates;
}
// Step 2
// If CurrentSoftwarePs is not P0, copy CurrentSoftwarePs contents to Software P0 and switch
// to P0.
if (CurrentSoftwarePs != 0) {
F14PmPwrChkCopyPstate (NumberBoostStates, CurrentSoftwarePs, StdHeader);
LibAmdMsrRead ((PS_REG_BASE + NumberBoostStates), &LocalMsrRegister, StdHeader);
((PSTATE_MSR *) &LocalMsrRegister)->PsEnable = 1;
LibAmdMsrWrite ((PS_REG_BASE + NumberBoostStates), &LocalMsrRegister, StdHeader);
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader);
}
} else {
// move remaining P-state register(s) up
// Step 1
// Transition to a valid Pstate if current Pstate has been disabled
if (CurrentHardwarePs < DisHwPsNum) {
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (HardwarePsMaxVal - NumberBoostStates), (BOOLEAN) TRUE, StdHeader);
CurrentSoftwarePs = HardwarePsMaxVal - NumberBoostStates;
}
if (DisSwPsNum != 0) {
// Step 2
// Move enabled Pstates up and disable the remainder
for (i = 0; (i + DisHwPsNum) <= HardwarePsMaxVal; ++i) {
F14PmPwrChkCopyPstate ((i + NumberBoostStates), (i + DisHwPsNum), StdHeader);
}
// Step 3
// Transition to current COF/VID at shifted location
CurrentSoftwarePs = (CurrentSoftwarePs - DisSwPsNum);
FamilySpecificServices->TransitionPstate (FamilySpecificServices, CurrentSoftwarePs, (BOOLEAN) TRUE, StdHeader);
}
}
if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) {
// only software P0 should be enabled.
i = NumberBoostStates + 1;
} else {
if (DisSwPsNum == 0) {
// No software Pstate is disabed, set i = HardwarePsMaxVal + 1 to skip below 'while loop'.
i = HardwarePsMaxVal + 1;
} else {
// get the first software Pstate that should be disabled.
i = HardwarePsMaxVal - DisSwPsNum + 1;
}
}
while (i <= HardwarePsMaxVal) {
FamilySpecificServices->DisablePstate (FamilySpecificServices, i, StdHeader);
i++;
}
}
/*---------------------------------------------------------------------------------------*/
/**
* Copies the contents of one P-State MSR to another.
*
* @param[in] Dest Destination p-state number
* @param[in] Src Source p-state number
* @param[in] StdHeader Config handle for library and services
*
*/
VOID
STATIC
F14PmPwrChkCopyPstate (
IN UINT8 Dest,
IN UINT8 Src,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 LocalMsrRegister;
LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader);
LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader);
}

83
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerCheck.h
View File

@@ -1,83 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 Power related functions and structures
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F14
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _CPU_F14_POWER_CHECK_H_
#define _CPU_F14_POWER_CHECK_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/// Power Check Error Data
typedef struct {
UINT8 SocketNumber; ///< Socket Number
UINT8 HwPstateNumber; ///< Hardware P-state Number
UINT8 AllowablePstateNumber; ///< Allowable P-state Number
} PWRCHK_ERROR_DATA;
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
VOID
F14PmPwrCheck (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _CPU_F14_POWER_CHECK_H_

548
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerMgmt.h
View File

@@ -1,548 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 Power Management related stuff
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F14
* @e \$Revision: 46836 $ @e \$Date: 2011-02-10 12:22:59 -0700 (Thu, 10 Feb 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _CPUF14POWERMGMT_H_
#define _CPUF14POWERMGMT_H_
/*
* Family 14h CPU Power Management MSR definitions
*
*/
/* P-state Current Limit Register 0xC0010061 */
#define MSR_PSTATE_CURRENT_LIMIT 0xC0010061
/// Pstate Current Limit MSR Register
typedef struct {
UINT64 CurPstateLimit:3; ///< Current Pstate Limit
UINT64 :1; ///< Reserved
UINT64 PstateMaxVal:3; ///< Pstate Max Value
UINT64 :57; ///< Reserved
} PSTATE_CURLIM_MSR;
/* P-state Control Register 0xC0010062 */
#define MSR_PSTATE_CTL 0xC0010062
/// Pstate Control MSR Register
typedef struct {
UINT64 PstateCmd:3; ///< Pstate change command
UINT64 :61; ///< Reserved
} PSTATE_CTRL_MSR;
/* P-state Status Register 0xC0010063 */
#define MSR_PSTATE_STS 0xC0010063
/// Pstate Status MSR Register
typedef struct {
UINT64 CurPstate:3; ///< Current Pstate
UINT64 :61; ///< Reserved
} PSTATE_STS_MSR;
/* P-state Registers 0xC001006[B:4] */
#define MSR_PSTATE_0 0xC0010064
#define MSR_PSTATE_1 0xC0010065
#define MSR_PSTATE_2 0xC0010066
#define MSR_PSTATE_3 0xC0010067
#define MSR_PSTATE_4 0xC0010068
#define MSR_PSTATE_5 0xC0010069
#define MSR_PSTATE_6 0xC001006A
#define MSR_PSTATE_7 0xC001006B
#define PS_REG_BASE MSR_PSTATE_0 /* P-state Register base */
#define PS_MAX_REG MSR_PSTATE_7 /* Maximum P-State Register */
#define PS_MIN_REG MSR_PSTATE_0 /* Minimum P-State Register */
#define NM_PS_REG 8 /* number of P-state MSR registers */
/// Pstate MSR
typedef struct {
UINT64 CpuDidLSD:4; ///< CPU core divisor identifier least significant digit
UINT64 CpuDidMSD:5; ///< CPU core divisor identifier most significant digit
UINT64 CpuVid:7; ///< CPU core VID
UINT64 :16; ///< Reserved
UINT64 IddValue:8; ///< Current value field
UINT64 IddDiv:2; ///< Current divisor field
UINT64 :21; ///< Reserved
UINT64 PsEnable:1; ///< P-state Enable
} PSTATE_MSR;
/* COFVID Control Register 0xC0010070 */
#define MSR_COFVID_CTL 0xC0010070
/// COFVID Control MSR Register
typedef struct {
UINT64 CpuDid:4; ///< CPU core divisor identifier
UINT64 CpuDidMSD:5; ///< CPU core frequency identifier
UINT64 CpuVid:7; ///< CPU core VID
UINT64 PstateId:3; ///< P-state identifier
UINT64 IgnoreFidVidDid:1; ///< Ignore FID, VID, and DID
UINT64 :44; ///< Reserved
} COFVID_CTRL_MSR;
/* COFVID Status Register 0xC0010071 */
#define MSR_COFVID_STS 0xC0010071
/// COFVID Status MSR Register
typedef struct {
UINT64 CurCpuDid:4; ///< Current CPU core divisor ID
UINT64 CurCpuDidMSD:5; ///< Current CPU core frequency ID
UINT64 CurCpuVid:7; ///< Current CPU core VID
UINT64 CurPstate:3; ///< Current P-state
UINT64 :1; ///< Reserved
UINT64 PstateInProgress:1; ///< P-state change in progress
UINT64 :4; ///< Reserved
UINT64 CurNbVid:7; ///< Current northbridge VID
UINT64 StartupPstate:3; ///< Startup P-state number
UINT64 MaxVid:7; ///< Maximum voltage
UINT64 MinVid:7; ///< Minimum voltage
UINT64 MainPllOpFreqIdMax:6; ///< Main PLL operating frequency ID maximum
UINT64 :1; ///< Reserved
UINT64 CurPstateLimit:3; ///< Current P-state Limit
UINT64 :5; ///< Reserved
} COFVID_STS_MSR;
/* C-state Address Register 0xC0010073 */
#define MSR_CSTATE_ADDRESS 0xC0010073
/// C-state Address MSR Register
typedef struct {
UINT64 CstateAddr:16; ///< C-state address
UINT64 :48; ///< Reserved
} CSTATE_ADDRESS_MSR;
/* CPU Watchdog Timer Register 0xC0010074 */
#define MSR_CPU_WDT 0xC0010074
/// CPU Watchdog Timer Register
typedef struct {
UINT64 CpuWdtEn:1; ///< CPU watchdog timer enable
UINT64 CpuWdtTimeBase:2; ///< CPU watchdog timer time base
UINT64 CpuWdtCountSel:4; ///< CPU watchdog timer count select
UINT64 :57; ///< Reserved
} CPU_WDT_MSR;
/*
* Family 14h CPU Power Management PCI definitions
*
*/
/* Memory controller configuration low register D18F2x118 */
#define MEM_CFG_LOW_REG 0x118
#define MEM_CFG_LOW_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_2, MEM_CFG_LOW_REG))
/// Memory Controller Configuration Low
typedef struct {
UINT32 MctPriCpuRd:2; ///< CPU read priority
UINT32 MctPriCpuWr:2; ///< CPU write priority
UINT32 MctPriHiRd:2; ///< High-priority VC set read priority
UINT32 MctPriHiWr:2; ///< High-priority VC set write priority
UINT32 MctPriDefault:2; ///< Default non-write priority
UINT32 MctPriWr:2; ///< Default write priority
UINT32 :7; ///< Reserved
UINT32 C6DramLock:1; ///< C6 DRAM lock
UINT32 :8; ///< Reserved
UINT32 MctVarPriCntLmt:4; ///< Variable priority time limit
} MEM_CFG_LOW_REGISTER;
/* Hardware thermal control register D18F3x64 */
#define HTC_REG 0x64
#define HTC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, HTC_REG))
/// Hardware Thermal Control PCI Register
typedef struct {
UINT32 HtcEn:1; ///< HTC Enable
UINT32 :3; ///< Reserved
UINT32 HtcAct:1; ///< HTC Active State
UINT32 HtcActSts:1; ///< HTC Active Status
UINT32 PslApicHiEn:1; ///< P-state limit higher APIC int enable
UINT32 PslApicLoEn:1; ///< P-state limit lower APIC int enable
UINT32 :8; ///< Reserved
UINT32 HtcTmpLmt:7; ///< HTC temperature limit
UINT32 HtcSlewSel:1; ///< HTC slew-controlled temp select
UINT32 HtcHystLmt:4; ///< HTC hysteresis
UINT32 HtcPstateLimit:3; ///< HTC P-state limit select
UINT32 HtcLock:1; ///< HTC lock
} HTC_REGISTER;
/* Power Control Miscellaneous Register D18F3xA0 */
#define PW_CTL_MISC_REG 0xA0
#define PW_CTL_MISC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, PW_CTL_MISC_REG))
/// Power Control Miscellaneous PCI Register
typedef struct {
UINT32 PsiVid:7; ///< PSI_L VID threshold
UINT32 PsiVidEn:1; ///< PSI_L VID enable
UINT32 :1; ///< Reserved
UINT32 SviHighFreqSel:1; ///< SVI high frequency select
UINT32 :6; ///< Reserved
UINT32 ConfigId:12; ///< Configuration Identifier
UINT32 :3; ///< Reserved
UINT32 CofVidProg:1; ///< COF and VID of P-states programmed
} POWER_CTRL_MISC_REGISTER;
/* Clock Power/Timing Control 0 Register D18F3xD4 */
#define CPTC0_REG 0xD4
#define CPTC0_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC0_REG))
/// Clock Power Timing Control PCI Register
typedef struct {
UINT32 MainPllOpFreqId:6; ///< Main PLL Fid
UINT32 MainPllOpFreqIdEn:1; ///< Main PLL Fid Enable
UINT32 :1; ///< Reserved
UINT32 ClkRampHystSel:4; ///< Clock Ramp Hysteresis Select
UINT32 OnionOutHyst:4; ///< ONION outbound hysteresis
UINT32 DisNclkGatingIdle:1; ///< Disable NCLK gating when idle
UINT32 ClkGatingEnDram:1; ///< Clock gating enable DRAM
UINT32 :1; ///< Reserved
UINT32 PstateSpecFuseSel:8; ///< P-State Specification Fuse Select
UINT32 :5; ///< Reserved
} CLK_PWR_TIMING_CTRL_REGISTER;
/* Clock Power/Timing Control 1 Register D18F3xD8 */
#define CPTC1_REG 0xD8
#define CPTC1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC1_REG))
/// Clock Power Timing Control 1 PCI Register
typedef struct {
UINT32 :4; ///< Reserved
UINT32 VSRampSlamTime:3; ///< Voltage stabilization slam time
UINT32 :22; ///< Reserved
UINT32 SlamModeSelect:1; ///< Voltage slam mode select
UINT32 :2; ///< Reserved
} CLK_PWR_TIMING_CTRL1_REGISTER;
/* Clock Power/Timing Control 2 Register D18F3xDC */
#define CPTC2_REG 0xDC
#define CPTC2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC2_REG))
/// Clock Power Timing Control 2 PCI Register
typedef struct {
UINT32 :8; ///< Reserved
UINT32 PstateMaxVal:3; ///< P-state maximum value
UINT32 :1; ///< Reserved
UINT32 NbPs0Vid:7; ///< NB VID
UINT32 NclkFreqDone:1; ///< NCLK frequency change done
UINT32 NbPs0NclkDiv:7; ///< NCLK divisor
UINT32 NbClockGateHyst:3; ///< Northbridge clock gating hysteresis
UINT32 NbClockGateEn:1; ///< Northbridge clock gating enable
UINT32 CnbCifClockGateEn:1; ///< CNB CIF clock gating enable
} CLK_PWR_TIMING_CTRL2_REGISTER;
/* Northbridge Capabilities Register D18F3xE8 */
#define NB_CAPS_REG 0xE8
#define NB_CAPS_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, NB_CAPS_REG))
/// Northbridge Capabilities PCI Register
typedef struct {
UINT32 DctDualCap:1; ///< Two-channel DRAM capable
UINT32 :4; ///< Reserved
UINT32 DdrMaxRate:3; ///< Maximum DRAM data rate
UINT32 MctCap:1; ///< Memory controller capable
UINT32 SvmCapable:1; ///< SVM capable
UINT32 HtcCapable:1; ///< HTC capable
UINT32 :1; ///< Reserved
UINT32 CmpCap:2; ///< CMP capable
UINT32 :14; ///< Reserved
UINT32 LHtcCapable:1; ///< LHTC capable
UINT32 :3; ///< Reserved
} NB_CAPS_REGISTER;
/* Clock Power/Timing Control 3 Register D18F3x128 */
#define CPTC3_REG 0x128
#define CPTC3_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC3_REG))
/// Clock Power Timing Control 3 PCI Register
typedef struct {
UINT32 C6Vid:7; ///< C6 VID
UINT32 :1; ///< Reserved
UINT32 NbPsiVid:7; ///< NB PSI_L VID threshold
UINT32 NbPsiVidEn:1; ///< NB PSI_L enable
UINT32 :16; ///< Reserved
} CLK_PWR_TIMING_CTRL3_REGISTER;
/* Local hardware thermal control register D18F3x138 */
#define LHTC_REG 0x138
#define LHTC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, LHTC_REG))
/// Local Hardware Thermal Control PCI Register
typedef struct {
UINT32 LHtcEn:1; ///< Local HTC Enable
UINT32 :7; ///< Reserved
UINT32 LHtcAct:2; ///< Local HTC Active State
UINT32 :2; ///< Reserved
UINT32 LHtcActSts:2; ///< Local HTC Active Status
UINT32 :2; ///< Reserved
UINT32 LHtcTmpLmt:7; ///< Local HTC temperature limit
UINT32 LHtcSlewSel:1; ///< Local HTC slew-controlled temp select
UINT32 LHtcHystLmt:4; ///< Local HTC hysteresis
UINT32 LHtcPstateLimit:3; ///< Local HTC P-state limit select
UINT32 LHtcLock:1; ///< HTC lock
} LHTC_REGISTER;
/* Product Information Register D18F3x1FC */
#define PRODUCT_INFO_REG 0x1FC
#define PRODUCT_INFO_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, PRODUCT_INFO_REG))
/// Product Information PCI Register
typedef struct {
UINT32 :2; ///< Reserved
UINT32 LowPowerDefault:1; ///< Low Power Default
UINT32 :29; ///< Reserved
} PRODUCT_INFO_REGISTER;
/* C-state Control 1 Register D18F4x118 */
#define CSTATE_CTRL1_REG 0x118
#define CSTATE_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL1_REG))
/// C-state Control 1 Register
typedef struct {
UINT32 CstAct0:3; ///< C-state action field 0
UINT32 :5; ///< Reserved
UINT32 CstAct1:3; ///< C-state action field 1
UINT32 :5; ///< Reserved
UINT32 CstAct2:3; ///< C-state action field 2
UINT32 :5; ///< Reserved
UINT32 CstAct3:3; ///< C-state action field 3
UINT32 :5; ///< Reserved
} CSTATE_CTRL1_REGISTER;
/* C-state Control 2 Register D18F4x11C */
#define CSTATE_CTRL2_REG 0x11C
#define CSTATE_CTRL2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL2_REG))
/// C-state Control 2 Register
typedef struct {
UINT32 CstAct4:3; ///< C-state action field 4
UINT32 :5; ///< Reserved
UINT32 CstAct5:3; ///< C-state action field 5
UINT32 :5; ///< Reserved
UINT32 CstAct6:3; ///< C-state action field 6
UINT32 :5; ///< Reserved
UINT32 CstAct7:3; ///< C-state action field 7
UINT32 :5; ///< Reserved
} CSTATE_CTRL2_REGISTER;
/* C-state Monitor Control 3 Register D18F4x134 */
#define CSTATE_MON_CTRL3_REG 0x134
#define CSTATE_MON_CTRL3_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_MON_CTRL3_REG))
/// C-state Monitor Control 3 Register
typedef struct {
UINT32 IntRatePkgC6MaxDepth:4; ///< Interrupt rate monitor PC6 maximum counter depth
UINT32 IntRatePkgC6Threshold:4; ///< Interrupt rate monitor PC6 threshold
UINT32 IntRatePkgC6BurstLen:3; ///< Interrupt rate monitor PC6 burst length
UINT32 IntRatePkgC6DecrRate:5; ///< Interrupt rate monitor PC6 decrement rate
UINT32 IntRateCC6MaxDepth:4; ///< Interrupt rate monitor CC6 maximum counter depth
UINT32 IntRateCC6Threshold:4; ///< Interrupt rate monitor CC6 threshold
UINT32 IntRateCC6BurstLen:3; ///< Interrupt rate monitor CC6 burst length
UINT32 IntRateCC6DecrRate:5; ///< Interrupt rate monitor CC6 decrement rate
} CSTATE_MON_CTRL3_REGISTER;
/* LPMV Scalar 2 Register D18F4x14C */
#define LPMV_SCALAR2_REG 0x14C
#define LPMV_SCALAR2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, LPMV_SCALAR2_REG))
/// LPMV Scalar 2 Register
typedef struct {
UINT32 :24; ///< Reserved
UINT32 ApmCstExtPol:2; ///< Number of boosted states
UINT32 :6; ///< Reserved
} LPMV_SCALAR2_REGISTER;
/* Core Performance Boost Control Register D18F4x15C */
#define CPB_CTRL_REG 0x15C
#define CPB_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPB_CTRL_REG))
/// Core Performance Boost Control Register
typedef struct {
UINT32 BoostSrc:2; ///< Boost source
UINT32 NumBoostStates:3; ///< Number of boosted states
UINT32 :24; ///< Reserved
UINT32 BoostEnAllCores:1; ///< Boost enable all cores
UINT32 :2; ///< Reserved
} CPB_CTRL_REGISTER;
/* CPU State Power Management Dynamic Control 0 Register D18F4x1A8 */
#define CPU_STATE_PM_CTRL0_REG 0x1A8
#define CPU_STATE_PM_CTRL0_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPU_STATE_PM_CTRL0_REG))
/// CPU State Power Management Dynamic Control 0 Register
typedef struct {
UINT32 SingleHaltCpuDid:5; ///< Single hlt CPU DID
UINT32 AllHaltCpuDid:5; ///< All hlt CPU DID
UINT32 :5; ///< Reserved
UINT32 CpuProbEn:1; ///< CPU probe enable
UINT32 :1; ///< Reserved
UINT32 PService:3; ///< Service P-state
UINT32 PServiceTmr:3; ///< Service P-state timer
UINT32 PServiceTmrEn:1; ///< Service P-state timer enable
UINT32 DramSrEn:1; ///< DRAM self-refresh enable
UINT32 MemTriStateEn:1; ///< Memory clock tri-state enable
UINT32 DramSrHyst:3; ///< DRAM self-refresh hysteresis time
UINT32 DramSrHystEnable:1; ///< DRAM self-refresh hysteresis enable
UINT32 :2; ///< Reserved
} CPU_STATE_PM_CTRL0_REGISTER;
/* CPU State Power Management Dynamic Control 1 Register D18F4x1AC */
#define CPU_STATE_PM_CTRL1_REG 0x1AC
#define CPU_STATE_PM_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPU_STATE_PM_CTRL1_REG))
/// CPU State Power Management Dynamic Control 1 Register
typedef struct {
UINT32 :5; ///< Reserved
UINT32 C6Did:5; ///< CC6 divisor
UINT32 :6; ///< Reserved
UINT32 PstateIdCoreOffExit:3; ///< P-state ID core-off exit
UINT32 :7; ///< Reserved
UINT32 PkgC6Cap:1; ///< Package C6 capable
UINT32 CoreC6Cap:1; ///< Core C6 capable
UINT32 PkgC6Dis:1; ///< Package C6 disable
UINT32 CoreC6Dis:1; ///< Core C6 disable
UINT32 CstPminEn:1; ///< C-state Pmin enable
UINT32 :1; ///< Reserved
} CPU_STATE_PM_CTRL1_REGISTER;
/* C6 Base Register D18F4x12C */
#define C6_BASE_REG 0x12C
#define C6_BASE_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, C6_BASE_REG))
/// C6 Base Register
typedef struct {
UINT32 C6Base:12; ///< C6 base[35:24]
UINT32 :20; ///< Reserved
} C6_BASE_REGISTER;
/* NB P-state Config Low Register D18F6x90 */
#define NB_PSTATE_CFG_LOW_REG 0x90
#define NB_PSTATE_CFG_LOW_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_6, NB_PSTATE_CFG_LOW_REG))
/// NB P-state Config Low Register
typedef struct {
UINT32 NbPs1NclkDiv:7; ///< NBP1 NCLK divisor
UINT32 :1; ///< Reserved
UINT32 NbPs1Vid:7; ///< NBP1 NCLK VID
UINT32 :1; ///< Reserved
UINT32 NbPs1GnbSlowIgn:1; ///< NB P-state ignore GNB slow signal
UINT32 :3; ///< Reserved
UINT32 NbPsLock:1; ///< NB P-state lock
UINT32 :7; ///< Reserved
UINT32 NbPsForceReq:1; ///< NB P-state force request
UINT32 NbPsForceSel:1; ///< NB P-state force selection
UINT32 NbPsCtrlDis:1; ///< NB P-state control disable
UINT32 NbPsCap:1; ///< NB P-state capable
} NB_PSTATE_CFG_LOW_REGISTER;
/* NB P-state Config High Register D18F6x94 */
#define NB_PSTATE_CFG_HIGH_REG 0x94
#define NB_PSTATE_CFG_HIGH_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_6, NB_PSTATE_CFG_HIGH_REG))
/// NB P-state Config High Register
typedef struct {
UINT32 CpuPstateThr:3; ///< CPU P-state threshold
UINT32 CpuPstateThrEn:1; ///< CPU P-state threshold enable
UINT32 NbPs1NoTransOnDma:1; ///< NB P-state no transitions on DMA
UINT32 :15; ///< Reserved
UINT32 NbPsNonC0Timer:3; ///< NB P-state non-C0 timer
UINT32 NbPsC0Timer:3; ///< NB P-state C0 timer
UINT32 NbPs1ResTmrMin:3; ///< NBP1 minimum residency timer
UINT32 NbPs0ResTmrMin:3; ///< NBP0 minimum residency timer
} NB_PSTATE_CFG_HIGH_REGISTER;
/* NB P-state Control and Status Register D18F6x98 */
#define NB_PSTATE_CTRL_STS_REG 0x98
#define NB_PSTATE_CTRL_STS_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_6, NB_PSTATE_CTRL_STS_REG))
/// NB P-state Control and Status Register
typedef struct {
UINT32 NbPsTransInFlight:1; ///< NB P-state transition in flight
UINT32 NbPs1ActSts:1; ///< NB P-state 1 active status
UINT32 NbPs1Act:1; ///< NB P-state 1 active
UINT32 :27; ///< Reserved
UINT32 NbPsCsrAccSel:1; ///< NB P-state register accessibility select
UINT32 NbPsDbgEn:1; ///< NB P-state debug enable
} NB_PSTATE_CTRL_STS_REGISTER;
/* NCLK Reduction Control D18F6x9C */
#define NCLK_REDUCTION_CTRL_REG 0x9C
#define NCLK_REDUCTION_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_6, NCLK_REDUCTION_CTRL_REG))
/// NCLK Reduction Control
typedef struct {
UINT32 NclkRedDiv:7; ///< NCLK reduction divisor
UINT32 NclkRedSelfRefrAlways:1; ///< NCLK reduction always self refresh
UINT32 NclkRampWithDllRelock:1; ///< NCLK ramp mode
UINT32 :23; ///< Reserved
} NCLK_REDUCTION_CTRL_REGISTER;
/// enum for DSM workaround control
typedef enum {
CC6_DSM_WORK_AROUND_DISABLE = 0, ///< work around disable
CC6_DSM_WORK_AROUND_NORMAL_TRAFFIC, ///< work around With Normal Traffic
CC6_DSM_WORK_AROUND_HIGH_PRIORITY_CHANNEL, ///< work around With High Priority Channel
} CC6_DSM_WORK_AROUND;
#endif /* _CPUF14POWERMGMT_H */

149
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c
View File

@@ -1,149 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 Power Management Initialization Steps
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 45626 $ @e \$Date: 2011-01-19 09:58:02 -0700 (Wed, 19 Jan 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "Ids.h"
#include "cpuRegisters.h"
#include "cpuApicUtilities.h"
#include "cpuFamilyTranslation.h"
#include "cpuPowerMgmtSystemTables.h"
#include "cpuF14SoftwareThermal.h"
#include "cpuF14PowerPlane.h"
#include "cpuF14PowerCheck.h"
#include "cpuF14LowPowerInit.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14POWERMGMTSYSTEMTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
GetF14SysPmTable (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **SysPmTblPtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/* Family 14h Table */
/* ---------------------- */
CONST SYS_PM_TBL_STEP ROMDATA CpuF14SysPmTableArray[] =
{
IDS_INITIAL_F14_PM_STEP
// Step 1 - Power Plane Initialization
// Execute both cold & warm
{
0, // ExeFlags
F14PmPwrPlaneInit // Function Pointer
},
// Step x - Optimizations for lower power
// Execute both cold & warm
{
0, // ExeFlags
F14OptimizeForLowPowerInit // Function Pointer
},
// Step 2 - Current Delivery Check
// Execute both cold & warm
{
0, // ExeFlags
F14PmPwrCheck // Function Pointer
},
// Step x - Software Thermal Control Init
// Execute both cold & warm
{
0, // ExeFlags
F14PmThermalInit // Function Pointer
}
};
/*---------------------------------------------------------------------------------------*/
/**
* Returns the appropriate table of steps to perform to initialize the power management
* subsystem.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] SysPmTblPtr Points to the first entry in the table.
* @param[out] NumberOfElements Number of valid entries in the table.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF14SysPmTable (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **SysPmTblPtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
*NumberOfElements = (sizeof (CpuF14SysPmTableArray) / sizeof (SYS_PM_TBL_STEP));
*SysPmTblPtr = CpuF14SysPmTableArray;
}

273
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.c
View File

@@ -1,273 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 Power Plane Initialization
*
* Performs the "BIOS Requirements for Power Plane Initialization" as described
* in the BKDG.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F14
* @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuCacheInit.h"
#include "cpuRegisters.h"
#include "cpuFamilyTranslation.h"
#include "cpuServices.h"
#include "cpuF14PowerMgmt.h"
#include "cpuF14PowerPlane.h"
#include "OptionFamily14hEarlySample.h"
#include "NbSmuLib.h"
#include "GnbRegistersON.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14POWERPLANE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
extern F14_ES_CORE_SUPPORT F14EarlySampleCoreSupport;
// Register encodings for D18F3xD8[VSRampSlamTime]
STATIC CONST UINT32 ROMDATA F14VSRampSlamWaitTimes[8] =
{
625, // 000b: 6.25us
500, // 001b: 5.00us
417, // 010b: 4.17us
313, // 011b: 3.13us
250, // 100b: 2.50us
167, // 101b: 1.67us
125, // 110b: 1.25us
100 // 111b: 1.00us
};
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
STATIC
F14PmVrmLowPowerModeEnable (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Family 14h core 0 entry point for performing power plane initialization.
*
* The steps are as follows:
* 1. BIOS must initialize D18F3xD8[VSRampSlamTime].
* 2. BIOS must configure D18F3xA0[PsiVidEn & PsiVid] and
* D18F3x128[NbPsiVidEn & NbPsiVid].
* 3. BIOS must program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid] - 1.
* BIOS must program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid].
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParams Service parameters
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F14PmPwrPlaneInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 SystemSlewRate;
UINT32 PciReg;
UINT32 WaitTime;
UINT32 VSRampSlamTime;
PCI_ADDR PciAddress;
FCRxFE00_6000_STRUCT FCRxFE00_6000;
// Step 1 - Configure D18F3xD8[VSRampSlamTime] based on platform requirements.
// Voltage Ramp Time = maximum time to change voltage by 12.5mV rounded to the next higher encoding.
SystemSlewRate = (CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate <=
CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].SlewRate) ?
CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate :
CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].SlewRate;
ASSERT (SystemSlewRate != 0);
// First, calculate the time it takes to change 12.5mV using the VRM slew rate.
WaitTime = (12500 * 100) / SystemSlewRate;
if (((12500 * 100) % SystemSlewRate) != 0) {
WaitTime++;
}
// Next, round it to the appropriate encoded value. We will start from encoding 111b which corresponds
// to the fastest slew rate, and work our way down to 000b, which represents the slowest an acceptable
// VRM can be.
for (VSRampSlamTime = (ARRAY_SIZE(F14VSRampSlamWaitTimes)- 1); VSRampSlamTime > 0; VSRampSlamTime--) {
if (WaitTime <= F14VSRampSlamWaitTimes[VSRampSlamTime]) {
break;
}
}
if (WaitTime > F14VSRampSlamWaitTimes[0]) {
// The VRMs on this motherboard are too slow for this CPU.
IDS_ERROR_TRAP;
}
// Lastly, program D18F3xD8[VSRampSlamTime] with the appropriate encoded value.
PciAddress.AddressValue = CPTC1_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
((CLK_PWR_TIMING_CTRL1_REGISTER *) &PciReg)->VSRampSlamTime = VSRampSlamTime;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
// Step 2 - Configure D18F3xA0[PsiVidEn & PsiVid] and D18F3x128[NbPsiVidEn & NbPsiVid].
F14PmVrmLowPowerModeEnable (FamilySpecificServices, CpuEarlyParams, StdHeader);
// Step 3 - Program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid] - 1.
// Program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid].
FCRxFE00_6000.Value = NbSmuReadEfuse (FCRxFE00_6000_ADDRESS, StdHeader);
F14EarlySampleCoreSupport.F14PowerPlaneInitHook (&FCRxFE00_6000, StdHeader);
PciAddress.AddressValue = CPTC2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciReg)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid - 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciReg)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
* Sets up PSI_L operation.
*
* This function implements the AMD_CPU_EARLY_PARAMS.VrmLowPowerThreshold parameter.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParams Contains VrmLowPowerThreshold parameter.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
F14PmVrmLowPowerModeEnable (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Pstate;
UINT32 PstateMaxVal;
UINT32 PstateCurrent;
UINT32 NextPstateCurrent;
UINT32 NextPstateCurrentRaw;
UINT32 PciReg;
UINT32 PreviousVid;
UINT32 CurrentVid;
UINT64 PstateMsr;
UINT64 PstateLimitMsr;
BOOLEAN IsPsiEnabled;
PCI_ADDR PciAddress;
// Set up PSI_L for VDD
IsPsiEnabled = FALSE;
PreviousVid = 0x7F;
CurrentVid = 0x7F;
if (CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold != 0) {
LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &PstateLimitMsr, StdHeader);
PstateMaxVal = (UINT32) ((PSTATE_CURLIM_MSR *) &PstateLimitMsr)->PstateMaxVal;
FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) 0, &PstateCurrent, StdHeader);
for (Pstate = 0; Pstate <= PstateMaxVal; Pstate++) {
LibAmdMsrRead ((UINT32) (Pstate + PS_REG_BASE), &PstateMsr, StdHeader);
CurrentVid = (UINT32) ((PSTATE_MSR *) &PstateMsr)->CpuVid;
if (Pstate == PstateMaxVal) {
NextPstateCurrentRaw = 0;
NextPstateCurrent = 0;
} else {
FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) (Pstate + 1), &NextPstateCurrentRaw, StdHeader);
NextPstateCurrent = NextPstateCurrentRaw + CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].InrushCurrentLimit;
}
if ((PstateCurrent <= CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold) &&
(NextPstateCurrent <= CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold) &&
(CurrentVid != PreviousVid)) {
IsPsiEnabled = TRUE;
break;
} else {
PstateCurrent = NextPstateCurrentRaw;
PreviousVid = CurrentVid;
}
}
}
PciAddress.AddressValue = PW_CTL_MISC_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
if (IsPsiEnabled) {
((POWER_CTRL_MISC_REGISTER *) &PciReg)->PsiVid = CurrentVid;
((POWER_CTRL_MISC_REGISTER *) &PciReg)->PsiVidEn = 1;
} else {
((POWER_CTRL_MISC_REGISTER *) &PciReg)->PsiVidEn = 0;
}
LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
// Set up NBPSI_L for VDDNB
PciAddress.AddressValue = CPTC3_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
if (CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].LowPowerThreshold != 0) {
((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciReg)->NbPsiVid = 0;
((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciReg)->NbPsiVidEn = 1;
} else {
((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciReg)->NbPsiVidEn = 0;
}
LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
}

78
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.h
View File

@@ -1,78 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 Power Plane related functions and structures
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F14
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _CPU_F14_POWER_PLANE_H_
#define _CPU_F14_POWER_PLANE_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
VOID
F14PmPwrPlaneInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _CPU_F14_POWER_PLANE_H_

432
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Pstate.c
View File

@@ -1,432 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 Pstate feature support functions.
*
* Provides the functions necessary to initialize the Pstate feature.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F14
* @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuPstateTables.h"
#include "cpuFamilyTranslation.h"
#include "cpuRegisters.h"
#include "cpuF14Utilities.h"
#include "cpuF14PowerMgmt.h"
#include "CommonReturns.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14PSTATE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
AGESA_STATUS
F14GetPstateTransLatency (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN PSTATE_LEVELING *PStateLevelingBufferStructPtr,
IN PCI_ADDR *PciAddress,
OUT UINT32 *TransitionLatency,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F14GetPstateFrequency (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN UINT8 StateNumber,
OUT UINT32 *FrequencyInMHz,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F14GetPstatePower (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN UINT8 StateNumber,
OUT UINT32 *PowerInMw,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F14GetPstateMaxState (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
OUT UINT32 *MaxPStateNumber,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F14GetPstateRegisterInfo (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN UINT32 PState,
OUT BOOLEAN *PStateEnabled,
IN OUT UINT32 *IddVal,
IN OUT UINT32 *IddDiv,
OUT UINT32 *SwPstateNumber,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/**
* Family specific call to set core TscFreqSel.
*
* @param[in] PstateCpuServices Pstate CPU services.
* @param[in] StdHeader Config Handle for library, services.
*
*/
VOID
STATIC
F14SetTscFreqSel (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrValue;
LibAmdMsrRead (MSR_HWCR, &MsrValue, StdHeader);
MsrValue = MsrValue | BIT24;
LibAmdMsrWrite (MSR_HWCR, &MsrValue, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
* Family specific call to get Pstate Transition Latency.
*
* Follow BKDG, return zero currently.
*
* @param[in] PstateCpuServices Pstate CPU services.
* @param[in] PStateLevelingBufferStructPtr Pstate row data buffer pointer
* @param[in] PciAddress Pci address
* @param[out] TransitionLatency The transition latency.
* @param[in] StdHeader Header for library and services
*
* @retval AGESA_SUCCESS Always succeeds.
*/
AGESA_STATUS
F14GetPstateTransLatency (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN PSTATE_LEVELING *PStateLevelingBufferStructPtr,
IN PCI_ADDR *PciAddress,
OUT UINT32 *TransitionLatency,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
//
// TransitionLatency (us) = BusMasterLatency (us) = 0 us, calculation may
// change due to a potential new encoding.
//
*TransitionLatency = 0;
return (AGESA_SUCCESS);
}
/*---------------------------------------------------------------------------------------*/
/**
* Family specific call to calculates the frequency in megahertz of the desired P-state.
*
* @param[in] PstateCpuServices Pstate CPU services.
* @param[in] StateNumber The P-State to analyze.
* @param[out] FrequencyInMHz The P-State's frequency in MegaHertz
* @param[in] StdHeader Header for library and services
*
* @retval AGESA_SUCCESS Always Succeeds.
*/
AGESA_STATUS
F14GetPstateFrequency (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN UINT8 StateNumber,
OUT UINT32 *FrequencyInMHz,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 CpuDidLSD;
UINT32 CpuDidMSD;
UINT32 CoreClkDivisor;
UINT32 PciReg;
UINT64 MsrReg;
BOOLEAN FrequencyCalculated;
BOOLEAN ClockDivisorCalculated;
PCI_ADDR PciAddress;
UINT32 MainPllOpFreq;
UINT32 MainPllFid;
ASSERT (StateNumber < NM_PS_REG);
LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1);
CpuDidLSD = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuDidLSD);
CpuDidMSD = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuDidMSD);
FrequencyCalculated = FALSE;
ClockDivisorCalculated = FALSE;
CoreClkDivisor = 1;
if ((CpuDidLSD > 3) || (CpuDidMSD > 0x19)) {
// Either CpuDidLSD or CpuDidMSD is set to an undefined value.
// This is due to either a misfused CPU, or an invalid P-state MSR write.
ASSERT (FALSE);
ClockDivisorCalculated = TRUE;
FrequencyCalculated = TRUE;
CoreClkDivisor = 4;
*FrequencyInMHz = 100;
}
if (!ClockDivisorCalculated) {
CoreClkDivisor = (CpuDidMSD * 4) + CpuDidLSD + 4;
}
// Checking for supported divisor value
ASSERT (((CoreClkDivisor >= 4) && (CoreClkDivisor <= 63)) ||
((CoreClkDivisor >= 64) && (CoreClkDivisor <= 106) && ((CoreClkDivisor % 2) == 0)));
if (!FrequencyCalculated) {
// Get D18F3xD4[MainPllOpFreqId] frequency
PciAddress.AddressValue = CPTC0_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
if (((CLK_PWR_TIMING_CTRL_REGISTER *) &PciReg)->MainPllOpFreqIdEn == 1) {
MainPllFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciReg)->MainPllOpFreqId;
} else {
MainPllFid = 0;
}
MainPllOpFreq = ((MainPllFid + 0x10) * 100);
*FrequencyInMHz = MainPllOpFreq * 4 / CoreClkDivisor;
}
return (AGESA_SUCCESS);
}
/*--------------------------------------------------------------------------------------*/
/**
*
* Family specific call to calculates the power in milliWatts of the desired P-state.
*
* @param[in] PstateCpuServices Pstate CPU services.
* @param[in] StateNumber Which P-state to analyze
* @param[out] PowerInMw The Power in milliWatts of that P-State
* @param[in] StdHeader Header for library and services
*
* @retval AGESA_SUCCESS Always succeeds.
*/
AGESA_STATUS
F14GetPstatePower (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN UINT8 StateNumber,
OUT UINT32 *PowerInMw,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 CpuVid;
UINT32 IddValue;
UINT32 IddDiv;
UINT32 V_x10000;
UINT32 Power;
UINT64 MsrReg;
ASSERT (StateNumber < NM_PS_REG);
LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1);
CpuVid = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuVid);
IddValue = (UINT32) (((PSTATE_MSR *) &MsrReg)->IddValue);
IddDiv = (UINT32) (((PSTATE_MSR *) &MsrReg)->IddDiv);
if (CpuVid >= 0x7C) {
V_x10000 = 0;
} else {
V_x10000 = 15500L - (125L * CpuVid);
}
Power = V_x10000 * IddValue;
switch (IddDiv) {
case 0:
*PowerInMw = Power / 10L;
break;
case 1:
*PowerInMw = Power / 100L;
break;
case 2:
*PowerInMw = Power / 1000L;
break;
default:
// IddDiv is set to an undefined value. This is due to either a misfused CPU, or
// an invalid P-state MSR write.
ASSERT (FALSE);
*PowerInMw = 0;
break;
}
return (AGESA_SUCCESS);
}
/*---------------------------------------------------------------------------------------*/
/**
* Family specific call to get CPU pstate max state.
*
* @param[in] PstateCpuServices Pstate CPU services.
* @param[out] MaxPStateNumber Boolean flag return pstate enable.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*/
AGESA_STATUS
F14GetPstateMaxState (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
OUT UINT32 *MaxPStateNumber,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrValue;
UINT32 PciReg;
PCI_ADDR PciAddress;
// For F14 CPU, skip boosted p-state. The boosted p-state number = D18F4x15C[NumBoostStates].
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader); // D18F4x15C
//
// Read PstateMaxVal [6:4] from MSR C001_0061
// So, we will know the max pstate state in this socket.
//
LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrValue, StdHeader);
*MaxPStateNumber = (UINT32) (((PSTATE_CURLIM_MSR *) &MsrValue)->PstateMaxVal) + (UINT32) (((CPB_CTRL_REGISTER *) &PciReg)->NumBoostStates);
return (AGESA_SUCCESS);
}
/*---------------------------------------------------------------------------------------*/
/**
* Family specific call to get CPU pstate register information.
*
* @param[in] PstateCpuServices Pstate CPU services.
* @param[in] PState Input Pstate number for query.
* @param[out] PStateEnabled Boolean flag return pstate enable.
* @param[in,out] IddVal Pstate current value.
* @param[in,out] IddDiv Pstate current divisor.
* @param[out] SwPstateNumber Software P-state number.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*/
AGESA_STATUS
F14GetPstateRegisterInfo (
IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
IN UINT32 PState,
OUT BOOLEAN *PStateEnabled,
IN OUT UINT32 *IddVal,
IN OUT UINT32 *IddDiv,
OUT UINT32 *SwPstateNumber,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 LocalMsrReg;
UINT32 LocalPciReg;
PCI_ADDR PciAddress;
CPU_LOGICAL_ID CpuFamilyRevision;
ASSERT (PState < NM_PS_REG);
// Read PSTATE MSRs
LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &LocalMsrReg, StdHeader);
*SwPstateNumber = PState;
if (((PSTATE_MSR *) &LocalMsrReg)->PsEnable == 1) {
// PState enable = bit 63
*PStateEnabled = TRUE;
// For F14 CPU, skip boosted p-state. The boosted p-state number = D18F4x15C[NumBoostStates].
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) == 0) {
// ON_Ax & ON_Bx don't have boosted p-state function
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciReg, StdHeader); // D18F4x15C
//
// Check input pstate belongs to Boosted-Pstate, if yes, return *PStateEnabled = FALSE.
//
if (PState < ((CPB_CTRL_REGISTER *) &LocalPciReg)->NumBoostStates) {
*PStateEnabled = FALSE;
} else {
*SwPstateNumber = PState - ((CPB_CTRL_REGISTER *) &LocalPciReg)->NumBoostStates;
}
}
} else {
*PStateEnabled = FALSE;
}
// Bits 39:32 (high 32 bits [7:0])
*IddVal = (UINT32) ((PSTATE_MSR *) &LocalMsrReg)->IddValue;
// Bits 41:40 (high 32 bits [9:8])
*IddDiv = (UINT32) ((PSTATE_MSR *) &LocalMsrReg)->IddDiv;
return (AGESA_SUCCESS);
}
CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F14PstateServices =
{
0,
(PF_PSTATE_PSD_IS_NEEDED) CommonReturnTrue,
(PF_PSTATE_PSD_IS_DEPENDENT) CommonReturnTrue,
F14SetTscFreqSel,
F14GetPstateTransLatency,
F14GetPstateFrequency,
(PF_CPU_SET_PSTATE_LEVELING_REG) CommonReturnAgesaSuccess,
F14GetPstatePower,
F14GetPstateMaxState,
F14GetPstateRegisterInfo
};

127
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c
View File

@@ -1,127 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 thermal initialization
*
* Performs processor thermal initialization.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F14
* @e \$Revision: 46836 $ @e \$Date: 2011-02-10 12:22:59 -0700 (Thu, 10 Feb 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuRegisters.h"
#include "cpuFamilyTranslation.h"
#include "cpuF14PowerMgmt.h"
#include "cpuF14SoftwareThermal.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14SOFTWARETHERMAL_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------*/
/**
* Main entry point for initializing the SW Thermal Control
* safety net feature.
*
* This must be run by all Family 14h core 0s in the system.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParamsPtr Service parameters.
* @param[in] StdHeader Config handle for library and services.
*/
VOID
F14PmThermalInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 NbCaps;
UINT32 LocalPciRegister;
PCI_ADDR PciAddress;
CPU_LOGICAL_ID CpuFamilyRevision;
PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader);
if (((NB_CAPS_REGISTER *) &NbCaps)->HtcCapable == 1) {
PciAddress.AddressValue = HTC_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (((HTC_REGISTER *) &LocalPciRegister)->HtcTmpLmt != 0) {
// Enable HTC
((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
}
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
if ((CpuFamilyRevision.Revision & AMD_F14_ON_Cx) != 0) {
PciAddress.AddressValue = LHTC_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (((NB_CAPS_REGISTER *) &NbCaps)->LHtcCapable == 1) {
if (((LHTC_REGISTER *) &LocalPciRegister)->LHtcTmpLmt != 0) {
// Enable local HTC
((LHTC_REGISTER *) &LocalPciRegister)->LHtcEn = 1;
}
}
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
}

80
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14SoftwareThermal.h
View File

@@ -1,80 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 thermal initialization related functions and structures
*
* Performs processor thermal initialization.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F14
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _CPU_F14_SOFTWARE_THERMAL_H_
#define _CPU_F14_SOFTWARE_THERMAL_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
VOID
F14PmThermalInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _CPU_F14_SOFTWARE_THERMAL_H_

571
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c
View File

@@ -1,571 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 specific utility functions.
*
* Provides numerous utility functions specific to family 14h.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F14
* @e \$Revision: 37640 $ @e \$Date: 2010-09-08 23:01:59 +0800 (Wed, 08 Sep 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuRegisters.h"
#include "cpuFamilyTranslation.h"
#include "cpuPstateTables.h"
#include "cpuF14PowerMgmt.h"
#include "cpuServices.h"
#include "GeneralServices.h"
#include "cpuF14Utilities.h"
#include "cpuPostInit.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14UTILITIES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable;
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
F14ConvertEnabledBitsIntoCount (
OUT UINT8 *EnabledCoreCountPtr,
IN UINT8 FusedCoreCount,
IN UINT8 EnabledCores
);
BOOLEAN
F14GetNbPstateInfo (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN PCI_ADDR *PciAddress,
IN UINT32 NbPstate,
OUT UINT32 *FreqNumeratorInMHz,
OUT UINT32 *FreqDivisor,
OUT UINT32 *VoltageInuV,
IN AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
F14IsNbPstateEnabled (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
F14GetProcIddMax (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT8 Pstate,
OUT UINT32 *ProcIddMax,
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT8
F14GetNumberOfCoresForBrandstring (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
F14ConvertEnabledBitsIntoCount (
OUT UINT8 *EnabledCoreCountPtr,
IN UINT8 FusedCoreCount,
IN UINT8 EnabledCores
)
{
UINT8 i;
UINT8 j;
UINT8 EnabledCoreCount;
EnabledCoreCount = 0;
for (i = 0; i < FusedCoreCount+1; i++) {
j = 1;
if (!((BOOLEAN) (EnabledCores) & (j << i))) {
EnabledCoreCount++;
}
}
*EnabledCoreCountPtr = EnabledCoreCount;
}
/*---------------------------------------------------------------------------------------*/
/**
* Disables the desired P-state.
*
* @CpuServiceMethod{::F_CPU_DISABLE_PSTATE}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] StateNumber The P-State to disable.
* @param[in] StdHeader Header for library and services
*
* @retval AGESA_SUCCESS Always succeeds.
*/
AGESA_STATUS
F14DisablePstate (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT8 StateNumber,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrReg;
ASSERT (StateNumber < NM_PS_REG);
LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
((PSTATE_MSR *) &MsrReg)->PsEnable = 0;
LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
return (AGESA_SUCCESS);
}
/*---------------------------------------------------------------------------------------*/
/**
* Transitions the executing core to the desired P-state.
*
* @CpuServiceMethod{::F_CPU_TRANSITION_PSTATE}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] StateNumber The new P-State to make effective.
* @param[in] WaitForTransition True if the caller wants the transition completed upon return.
* @param[in] StdHeader Header for library and services
*
* @retval AGESA_SUCCESS Always Succeeds
*/
AGESA_STATUS
F14TransitionPstate (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT8 StateNumber,
IN BOOLEAN WaitForTransition,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrReg;
ASSERT (StateNumber < NM_PS_REG);
LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1);
LibAmdMsrRead (MSR_PSTATE_CTL, &MsrReg, StdHeader);
((PSTATE_CTRL_MSR *) &MsrReg)->PstateCmd = (UINT64) StateNumber;
LibAmdMsrWrite (MSR_PSTATE_CTL, &MsrReg, StdHeader);
if (WaitForTransition) {
do {
LibAmdMsrRead (MSR_PSTATE_STS, &MsrReg, StdHeader);
} while (((PSTATE_STS_MSR *) &MsrReg)->CurPstate != (UINT64) StateNumber);
}
return (AGESA_SUCCESS);
}
/*---------------------------------------------------------------------------------------*/
/**
* Determines the rate at which the executing core's time stamp counter is
* incrementing.
*
* @CpuServiceMethod{::F_CPU_GET_TSC_RATE}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] FrequencyInMHz TSC actual frequency.
* @param[in] StdHeader Header for library and services.
*
* @return The most severe status of all called services
*/
AGESA_STATUS
F14GetTscRate (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT UINT32 *FrequencyInMHz,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrReg;
PSTATE_CPU_FAMILY_SERVICES *FamilyServices;
FamilyServices = NULL;
GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL);
LibAmdMsrRead (0xC0010015, &MsrReg, StdHeader);
if ((MsrReg & 0x01000000) != 0) {
return (FamilyServices->GetPstateFrequency (FamilyServices, 0, FrequencyInMHz, StdHeader));
} else {
return (FamilySpecificServices->GetCurrentNbFrequency (FamilySpecificServices, FrequencyInMHz, StdHeader));
}
}
/*---------------------------------------------------------------------------------------*/
/**
* Determines the NB clock on the desired node.
*
* @CpuServiceMethod{::F_CPU_GET_NB_FREQ}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] FrequencyInMHz Northbridge clock frequency in MHz.
* @param[in] StdHeader Header for library and services
*
* @retval AGESA_SUCCESS Always succeeds.
*/
AGESA_STATUS
F14GetCurrentNbFrequency (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT UINT32 *FrequencyInMHz,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 PciReg;
UINT32 MainPllFid;
PCI_ADDR PciAddress;
PciAddress.AddressValue = CPTC0_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
if (((CLK_PWR_TIMING_CTRL_REGISTER *) &PciReg)->MainPllOpFreqIdEn == 1) {
MainPllFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciReg)->MainPllOpFreqId;
} else {
MainPllFid = 0;
}
*FrequencyInMHz = ((MainPllFid + 0x10) * 100);
ASSERT (*FrequencyInMHz <= 4000);
return (AGESA_SUCCESS);
}
/*---------------------------------------------------------------------------------------*/
/**
* Determines the NB clock on the desired node.
*
* @CpuServiceMethod{::F_CPU_GET_NB_PSTATE_INFO}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[in] PciAddress The segment, bus, and device numbers of the CPU in question.
* @param[in] NbPstate The NB P-state number to check.
* @param[out] FreqNumeratorInMHz The desired node's frequency numerator in megahertz.
* @param[out] FreqDivisor The desired node's frequency divisor.
* @param[out] VoltageInuV The desired node's voltage in microvolts.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @retval TRUE NbPstate is valid
* @retval FALSE NbPstate is disabled or invalid
*/
BOOLEAN
F14GetNbPstateInfo (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN PCI_ADDR *PciAddress,
IN UINT32 NbPstate,
OUT UINT32 *FreqNumeratorInMHz,
OUT UINT32 *FreqDivisor,
OUT UINT32 *VoltageInuV,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 NbVid;
UINT32 PciReg;
UINT32 MainPllFreq;
BOOLEAN PstateIsValid;
PstateIsValid = FALSE;
if ((NbPstate == 0) || ((NbPstate == 1) && FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, PlatformConfig, StdHeader))) {
FamilySpecificServices->GetCurrentNbFrequency (FamilySpecificServices, &MainPllFreq, StdHeader);
*FreqNumeratorInMHz = (MainPllFreq * 4);
if (NbPstate == 0) {
PciAddress->Address.Function = FUNC_3;
PciAddress->Address.Register = CPTC2_REG;
LibAmdPciRead (AccessWidth32, *PciAddress, &PciReg, StdHeader);
*FreqDivisor = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciReg)->NbPs0NclkDiv;
NbVid = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciReg)->NbPs0Vid;
} else {
PciAddress->Address.Function = FUNC_6;
PciAddress->Address.Register = NB_PSTATE_CFG_LOW_REG;
LibAmdPciRead (AccessWidth32, *PciAddress, &PciReg, StdHeader);
*FreqDivisor = ((NB_PSTATE_CFG_LOW_REGISTER *) &PciReg)->NbPs1NclkDiv;
NbVid = ((NB_PSTATE_CFG_LOW_REGISTER *) &PciReg)->NbPs1Vid;
}
*VoltageInuV = (1550000 - (12500 * NbVid));
PstateIsValid = TRUE;
}
return PstateIsValid;
}
/*---------------------------------------------------------------------------------------*/
/**
* Is the Northbridge PState feature enabled?
*
* @CpuServiceMethod{::F_IS_NB_PSTATE_ENABLED}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @retval TRUE The NB PState feature is enabled.
* @retval FALSE The NB PState feature is not enabled.
*/
BOOLEAN
F14IsNbPstateEnabled (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 PciReg;
PCI_ADDR PciAddress;
PciAddress.AddressValue = NB_PSTATE_CFG_LOW_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
return ((BOOLEAN) (((NB_PSTATE_CFG_LOW_REGISTER *) &PciReg)->NbPsCap == 1));
}
/*---------------------------------------------------------------------------------------*/
/**
* Returns whether or not BIOS is responsible for configuring the NB COFVID.
*
* @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] PciAddress The northbridge to query by pci base address.
* @param[out] NbCofVidUpdateRequired TRUE, perform northbridge frequency and voltage config,
* FALSE, do not configure them.
* @param[in] StdHeader Header for library and services
*
* @retval AGESA_SUCCESS Always succeeds.
*/
BOOLEAN
F14GetNbCofVidUpdate (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PCI_ADDR *PciAddress,
OUT BOOLEAN *NbCofVidUpdateRequired,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
*NbCofVidUpdateRequired = FALSE;
return FALSE;
}
/*---------------------------------------------------------------------------------------*/
/**
* Initially launches the desired core to run from the reset vector.
*
* @CpuServiceMethod{::F_CPU_AP_INITIAL_LAUNCH}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] SocketNum The Processor on which the core is to be launched
* @param[in] ModuleNum The Module in that processor containing that core
* @param[in] CoreNum The Core to launch
* @param[in] PrimaryCoreNum The id of the module's primary core.
* @param[in] StdHeader Header for library and services
*
* @retval TRUE The core was launched
* @retval FALSE The core was previously launched
*/
BOOLEAN
F14LaunchApCore (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT32 SocketNum,
IN UINT32 ModuleNum,
IN UINT32 CoreNum,
IN UINT32 PrimaryCoreNum,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 NodeRelativeCoreNum;
UINT32 PciReg;
PCI_ADDR PciAddress;
BOOLEAN LaunchFlag;
// Code Start
LaunchFlag = FALSE;
NodeRelativeCoreNum = CoreNum - PrimaryCoreNum;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, PCI_DEV_BASE, FUNC_0, 0);
switch (NodeRelativeCoreNum) {
case 1:
PciAddress.Address.Register = HT_TRANS_CTRL;
LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
if ((PciReg & HT_TRANS_CTRL_CPU1_EN) == 0) {
PciReg |= HT_TRANS_CTRL_CPU1_EN;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
LaunchFlag = TRUE;
} else {
LaunchFlag = FALSE;
}
break;
default:
break;
}
return (LaunchFlag);
}
/*---------------------------------------------------------------------------------------*/
/**
* Get CPU Specific Platform Type Info.
*
* @CpuServiceMethod{::F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO}.
*
* This function returns Returns the platform features.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in,out] Features The Features supported by this platform.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*/
AGESA_STATUS
F14GetPlatformTypeSpecificInfo (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN OUT PLATFORM_FEATS *Features,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return (AGESA_SUCCESS);
}
/*---------------------------------------------------------------------------------------*/
/**
* Get CPU pstate current.
*
* @CpuServiceMethod{::F_CPU_GET_IDD_MAX}.
*
* This function returns the ProcIddMax.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] Pstate The P-state to check.
* @param[out] ProcIddMax P-state current in mA.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @retval TRUE P-state is enabled
* @retval FALSE P-state is disabled
*/
BOOLEAN
F14GetProcIddMax (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT8 Pstate,
OUT UINT32 *ProcIddMax,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 IddDiv;
UINT32 CmpCap;
UINT32 PciReg;
UINT32 MsrAddress;
UINT64 PstateMsr;
BOOLEAN IsPstateEnabled;
PCI_ADDR PciAddress;
IsPstateEnabled = FALSE;
MsrAddress = (UINT32) (Pstate + PS_REG_BASE);
ASSERT (MsrAddress <= PS_MAX_REG);
LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader);
if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) {
PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader); // F3xE8
CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &PciReg)->CmpCap);
CmpCap++;
switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) {
case 0:
IddDiv = 1000;
break;
case 1:
IddDiv = 100;
break;
case 2:
IddDiv = 10;
break;
default: // IddDiv = 3 is reserved. Use 10
ASSERT (FALSE);
IddDiv = 10;
break;
}
*ProcIddMax = (UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap;
IsPstateEnabled = TRUE;
}
return IsPstateEnabled;
}
/*---------------------------------------------------------------------------------------*/
/**
* Get number of processor cores to be used in determining the brand string.
*
* @CpuServiceMethod{::F_CPU_NUMBER_OF_BRANDSTRING_CORES}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @return The number of cores to be used in brand string calculation.
*/
UINT8
F14GetNumberOfCoresForBrandstring (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPUID_DATA CpuId;
//
//CPUID.80000008h.ECX.NC + 1, 000b = 1, 001b = 2, etc.
//
LibAmdCpuidRead (CPUID_LONG_MODE_ADDR, &CpuId, StdHeader);
return ((UINT8) ((CpuId.ECX_Reg & 0xff) + 1));
}

132
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.h
View File

@@ -1,132 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 specific utility functions.
*
* Provides numerous utility functions specific to family 14h.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _CPU_F14_UTILITES_H_
#define _CPU_F14_UTILITES_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
AGESA_STATUS
F14DisablePstate (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT8 StateNumber,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F14TransitionPstate (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT8 StateNumber,
IN BOOLEAN WaitForTransition,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F14GetTscRate (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT UINT32 *FrequencyInMHz,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F14GetCurrentNbFrequency (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT UINT32 *FrequencyInMHz,
IN AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
F14GetNbCofVidUpdate (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PCI_ADDR *PciAddress,
OUT BOOLEAN *NbCofVidUpdateRequired,
IN AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
F14LaunchApCore (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT32 SocketNum,
IN UINT32 ModuleNum,
IN UINT32 CoreNum,
IN UINT32 PrimaryCoreNum,
IN AMD_CONFIG_PARAMS *StdHeader
);
CORE_ID_POSITION
F14CpuAmdCoreIdPositionInInitialApicId (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F14GetPlatformTypeSpecificInfo (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN OUT PLATFORM_FEATS *Features,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _CPU_F14_UTILITES_H_

125
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c
View File

@@ -1,125 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_14 WHEA initial Data
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuLateInit.h"
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14WHEAINITDATATABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
GetF14WheaInitData (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **F14WheaInitDataPtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
AMD_HEST_BANK_INIT_DATA F14HestBankInitData[] = {
{0xFFFFFFFF,0xFFFFFFFF,0x400,0x401,0x402,0x403},
{0xFFFFFFFF,0xFFFFFFFF,0x404,0x405,0x406,0x407},
{0xFFFFFFFF,0xFFFFFFFF,0x408,0x409,0x40A,0x40B},
{0xFFFFFFFF,0xFFFFFFFF,0x410,0x411,0x412,0x413},
{0xFFFFFFFF,0xFFFFFFFF,0x414,0x415,0x416,0x417},
};
AMD_WHEA_INIT_DATA F14WheaInitData = {
0x000000000, // AmdGlobCapInitDataLsd
0x000000000, // AmdGlobCapInitDataMsd
0x00000003F, // AmdGlobCtrlInitDataLsd
0x000000000, // AmdGlobCtrlInitDataMsd
0x00, // AmdMcbClrStatusOnInit
0x02, // AmdMcbStatusDataFormat
0x00, // AmdMcbConfWriteEn
ARRAY_SIZE(F14HestBankInitData), // HestBankNum
&F14HestBankInitData[0] // Pointer to Initial data of HEST Bank
};
/*---------------------------------------------------------------------------------------*/
/**
* Returns the family specific WHEA table properties.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] F14WheaInitDataPtr Points to the family 12h WHEA properties.
* @param[out] NumberOfElements Will be one to indicate one structure.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF14WheaInitData (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **F14WheaInitDataPtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
*NumberOfElements = 1;
*F14WheaInitDataPtr = &F14WheaInitData;
}

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