soc/intel/tigerlake: Hook up SMBus device to devicetree

Hook up `SmbusEnable` FSP setting to devicetree state and drop its
redundant devicetree setting `SmbusEnable`.

The following mainboards enable the SMBus device in the devicetree
despite `SmbusEnable` is not being set.

  * google/deltaur
  * starlabs/laptop

Thus, set it to off to keep the current state unchanged.

Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/mainboard/google/deltaur/variants/baseboard/devicetree.cb

@@ -291,7 +291,7 @@ chip soc/intel/tigerlake
 		device pci 1f.1 off end # P2SB
 		device pci 1f.2 hidden end # PMC
 		device pci 1f.3 on  end # Intel HDA
-		device pci 1f.4 on  end # SMBus
+		device pci 1f.4 off end # SMBus
 		device pci 1f.5 on  end # PCH SPI Flash Controller
 		device pci 1f.6 off end # GbE Controller
 		device pci 1f.7 off end # Intel Trace Hub

src/mainboard/google/volteer/variants/baseboard/devicetree.cb

@@ -92,7 +92,6 @@ chip soc/intel/tigerlake
 
 	# FSP configuration
 	register "SaGv" = "SaGv_Enabled"
-	register "SmbusEnable" = "0"
 
 	register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A0
 	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A1

src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb

@@ -13,7 +13,6 @@ chip soc/intel/tigerlake
 
 	# FSP configuration
 	register "SaGv" = "SaGv_Enabled"
-	register "SmbusEnable" = "1"
 
 	# CNVi BT enable/disable
 	register "CnviBtCore" = "true"

src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb

@@ -13,7 +13,6 @@ chip soc/intel/tigerlake
 
 	# FSP configuration
 	register "SaGv" = "SaGv_Disabled"
-	register "SmbusEnable" = "1"
 
 	# CNVi BT enable/disable
 	register "CnviBtCore" = "true"

src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb

@@ -232,7 +232,7 @@ chip soc/intel/tigerlake
 			subsystemid 0x10ec 0x1200
 			register "PchHdaAudioLinkHdaEnable"	= "1"
 		end
-		device pci 1f.4 on  end						# SMBus
+		device pci 1f.4 off end						# SMBus
 		device pci 1f.5 on  end						# PCH SPI
 		device pci 1f.6 off end						# GbE
 		device pci 1f.7 off end						# TH

src/mainboard/system76/darp7/devicetree.cb

@@ -329,9 +329,7 @@ chip soc/intel/tigerlake
 		device ref hda on
 			register "PchHdaAudioLinkHdaEnable" = "1"
 		end
-		device ref smbus on
-			register "SmbusEnable" = "1"
-		end
+		device ref smbus on end
 		device ref fast_spi on end
 	end
 end

src/mainboard/system76/galp5/devicetree.cb

@@ -333,9 +333,7 @@ chip soc/intel/tigerlake
 		device ref hda on
 			register "PchHdaAudioLinkHdaEnable" = "1"
 		end
-		device ref smbus on
-			register "SmbusEnable" = "1"
-		end
+		device ref smbus on end
 		device ref fast_spi on end
 	end
 end

src/mainboard/system76/gaze16/devicetree.cb

@@ -145,9 +145,7 @@ chip soc/intel/tigerlake
 		device ref hda on
 			register "PchHdaAudioLinkHdaEnable" = "1"
 		end
-		device ref smbus on
-			register "SmbusEnable" = "1"
-		end
+		device ref smbus on end
 		device ref fast_spi on end
 	end
 end

src/mainboard/system76/lemp10/devicetree.cb

@@ -294,9 +294,7 @@ chip soc/intel/tigerlake
 		device ref hda on
 			register "PchHdaAudioLinkHdaEnable" = "1"
 		end
-		device ref smbus on
-			register "SmbusEnable" = "1"
-		end
+		device ref smbus on end
 		device ref fast_spi on end
 	end
 end

src/mainboard/system76/oryp8/devicetree.cb

@@ -212,7 +212,6 @@ chip soc/intel/tigerlake
 			register "PchHdaAudioLinkHdaEnable" = "1"
 		end
 		device ref smbus on
-			register "SmbusEnable" = "1"
 			chip drivers/i2c/tas5825m
 				register "id" = "0"
 				device i2c 4e on end # (8bit address: 0x9c)

src/soc/intel/tigerlake/chip.h

@@ -272,9 +272,6 @@ struct soc_intel_tigerlake_config {
 	/* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */
 	uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];
 
-	/* SMBus */
-	uint8_t SmbusEnable;
-
 	/* Gfx related */
 	uint8_t SkipExtGfxScan;
 

src/soc/intel/tigerlake/romstage/fsp_params.c

@@ -130,7 +130,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 	/* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */
 	m_cfg->ChHashMask = 0x30CC;
 	/* Enable SMBus controller based on config */
-	m_cfg->SmbusEnable = config->SmbusEnable;
+	m_cfg->SmbusEnable = is_devfn_enabled(PCH_DEVFN_SMBUS);
 	/* Set debug probe type */
 	m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT;