soc/intel/*: drop broken LPC mmio code

The code for setting the LPC generic memory range uses an array of fixed
address ranges not needing explicit decoding, to decide if the address
needs to be written to the LGMR register. Most platforms only mistakenly
add the PCH reserved mmio range, that is not decoded generally,
effectively breaking the mechanism. Only APL uses the array correctly.

That code, in it's current state, does not work (except for APL) and
currently, there is not a single user. Thus, drop it before people start
using it.

Change-Id: I723415fedd1b1d95c502badf7b0510a1338b11ac
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/soc/intel/skylake/lpc.c

@@ -15,20 +15,6 @@
 
 #include "chip.h"
 
-/**
-  PCH preserved MMIO range, 24 MB, from 0xFD000000 to 0xFE7FFFFF
-**/
-
-static const struct lpc_mmio_range skl_lpc_fixed_mmio_ranges[] = {
-	{ PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },
-	{ 0, 0 }
-};
-
-const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void)
-{
-	return skl_lpc_fixed_mmio_ranges;
-}
-
 void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
 {
 	const config_t *config = config_of_soc();