fix up iwill board compilation. Untested, trivial
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2930 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
committed by
Stefan Reinauer
Stefan Reinauer
parent
894562f4eb
commit
7162cf7278
@@ -50,6 +50,26 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
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## ATI Rage XL framebuffering graphics driver
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dir /drivers/ati/ragexl
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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makerule ./auto.o
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
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end
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else
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makerule ./auto.inc
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
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action "perl -e 's/.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/.text/.section .rom.text/g' -pi $@"
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end
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end
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else
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##
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## Romcc output
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##
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@@ -72,13 +92,27 @@ makerule ./auto.inc
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action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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end
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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##
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mainboardinit cpu/x86/16bit/entry16.inc
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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end
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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ldscript /cpu/x86/32bit/entry32.lds
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end
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if CONFIG_USE_INIT
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ldscript /cpu/amd/car/cache_as_ram.lds
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end
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end
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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@@ -91,8 +125,11 @@ else
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ldscript /cpu/x86/32bit/reset32.lds
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end
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if USE_DCACHE_RAM
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else
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### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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end
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##
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## Include an id string (For safe flashing)
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@@ -100,20 +137,44 @@ mainboardinit arch/i386/lib/cpu_reset.inc
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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if USE_DCACHE_RAM
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##
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## Setup Cache-As-Ram
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##
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mainboardinit cpu/amd/car/cache_as_ram.inc
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end
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###
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### This is the early phase of linuxBIOS startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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if USE_DCACHE_RAM
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ldscript /arch/i386/lib/failover.lds
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else
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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end
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## Setup RAM
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##
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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initobject auto.o
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else
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mainboardinit ./auto.inc
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end
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else
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##
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## Setup RAM
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##
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@@ -123,11 +184,11 @@ mainboardinit cpu/x86/sse/enable_sse.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/x86/sse/disable_sse.inc
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mainboardinit cpu/x86/mmx/disable_mmx.inc
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end
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##
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## Include the secondary Configuration files
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##
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dir /pc80
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config chip.h
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# config for iwill/dk8s2
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@@ -48,7 +48,9 @@ uses CROSS_COMPILE
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uses CC
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uses HOSTCC
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uses OBJCOPY
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uses USE_DCACHE_RAM
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uses DCACHE_RAM_BASE
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uses DCACHE_RAM_SIZE
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uses CONFIG_USE_INIT
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## ROM_SIZE is the size of boot ROM that this board will use.
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@@ -110,6 +112,14 @@ default CONFIG_MAX_PHYSICAL_CPUS=2
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##
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default CONFIG_IOAPIC=1
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##
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## enable CACHE_AS_RAM specifics
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##
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default USE_DCACHE_RAM=1
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default DCACHE_RAM_BASE=0xcf000
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default DCACHE_RAM_SIZE=0x1000
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default CONFIG_USE_INIT=0
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##
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## Clean up the motherboard id strings
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##
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@@ -69,49 +69,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
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}
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}
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static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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{
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/* Routing Table Node i
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*
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* F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
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* i: 0, 1, 2, 3, 4, 5, 6, 7
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*
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* [ 0: 3] Request Route
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* [0] Route to this node
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* [1] Route to Link 0
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* [2] Route to Link 1
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* [3] Route to Link 2
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* [11: 8] Response Route
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* [0] Route to this node
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* [1] Route to Link 0
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* [2] Route to Link 1
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* [3] Route to Link 2
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* [19:16] Broadcast route
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* [0] Route to this node
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* [1] Route to Link 0
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* [2] Route to Link 1
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* [3] Route to Link 2
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*/
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uint32_t ret=0x00010101; /* default row entry */
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static const unsigned int rows_2p[2][2] = {
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{ 0x00050101, 0x00010404 },
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{ 0x00010404, 0x00050101 }
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};
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if(maxnodes>2) {
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print_debug("this mainboard is only designed for 2 cpus\r\n");
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maxnodes=2;
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}
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if (!(node>=maxnodes || row>=maxnodes)) {
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ret=rows_2p[node][row];
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}
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return ret;
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}
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static inline void activate_spd_rom(const struct mem_controller *ctrl)
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{
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/* nothing to do */
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333
src/mainboard/iwill/dk8s2/cache_as_ram_auto.c
Normal file
333
src/mainboard/iwill/dk8s2/cache_as_ram_auto.c
Normal file
@@ -0,0 +1,333 @@
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#define ASSEMBLY 1
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#define __ROMCC__
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#define RAMINIT_SYSINFO 1
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#define CACHE_AS_RAM_ADDRESS_DEBUG 0
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#define SET_NB_CFG_54 1
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//used by raminit
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#define QRANK_DIMM_SUPPORT 1
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//used by incoherent_ht
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//#define K8_SCAN_PCI_BUS 1
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//#define K8_ALLOCATE_IO_RANGE 1
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//used by init_cpus and fidvid
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#define K8_SET_FIDVID 0
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//if we want to wait for core1 done before DQS training, set it to 0
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#define K8_SET_FIDVID_CORE0_ONLY 1
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#if K8_REV_F_SUPPORT == 1
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#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
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#endif
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <cpu/x86/lapic.h>
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#include "option_table.h"
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#include "pc80/mc146818rtc_early.c"
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#if USE_FAILOVER_IMAGE==0
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include <cpu/amd/model_fxx_rev.h>
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#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
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#include "northbridge/amd/amdk8/raminit.h"
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#include "cpu/amd/model_fxx/apic_timer.c"
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#endif
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#include "cpu/x86/lapic/boot_cpu.c"
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#include "northbridge/amd/amdk8/reset_test.c"
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#if USE_FAILOVER_IMAGE==0
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#include "cpu/x86/bist.h"
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#include "lib/delay.c"
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#if CONFIG_USE_INIT == 0
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#include "lib/memcpy.c"
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// TODO: This doesn't compile at the moment. Fix later.
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// #if CONFIG_USE_PRINTK_IN_CAR == 1
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// #include "lib/uart8250.c"
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// #include "console/vtxprintf.c"
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// #include "arch/i386/lib/printk_init.c"
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// #endif
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#endif
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#include "northbridge/amd/amdk8/debug.c"
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#include "cpu/amd/mtrr/amd_earlymtrr.c"
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#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
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#include "northbridge/amd/amdk8/setup_resource_map.c"
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
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/*
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* GPIO28 of 8111 will control H0_MEMRESET_L
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* GPIO29 of 8111 will control H1_MEMRESET_L
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*/
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static void memreset_setup(void)
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{
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if (is_cpu_pre_c0()) {
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/* Set the memreset low */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
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/* Ensure the BIOS has control of the memory lines */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
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} else {
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/* Ensure the CPU has controll of the memory lines */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
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}
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}
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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if (is_cpu_pre_c0()) {
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udelay(800);
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/* Set memreset_high */
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outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
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udelay(90);
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}
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}
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static inline void activate_spd_rom(const struct mem_controller *ctrl)
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{
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}
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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}
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#include "northbridge/amd/amdk8/amdk8.h"
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#include "northbridge/amd/amdk8/coherent_ht_car.c"
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#include "northbridge/amd/amdk8/incoherent_ht.c"
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#include "northbridge/amd/amdk8/raminit.c"
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#include "sdram/generic_sdram.c"
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#include "ram/ramtest.c"
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/* tyan does not want the default */
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#include "northbridge/amd/amdk8/resourcemap.c"
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#include "cpu/amd/dualcore/dualcore.c"
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#define DIMM0 0x50
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#define DIMM1 0x51
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#define DIMM2 0x52
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#define DIMM3 0x53
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#define DIMM4 0x54
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#define DIMM5 0x55
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#define DIMM6 0x56
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#define DIMM7 0x57
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#include "cpu/amd/car/copy_and_run.c"
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#include "cpu/amd/car/post_cache_as_ram.c"
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#include "cpu/amd/model_fxx/init_cpus.c"
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#include "cpu/amd/model_fxx/fidvid.c"
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#endif
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#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
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#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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unsigned last_boot_normal_x = last_boot_normal();
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/* Is this a cpu only reset? or Is this a secondary cpu? */
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if ((cpu_init_detectedx) || (!boot_cpu())) {
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if (last_boot_normal_x) {
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goto normal_image;
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} else {
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goto fallback_image;
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}
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}
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/* Nothing special needs to be done to find bus 0 */
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/* Allow the HT devices to be found */
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enumerate_ht_chain();
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/* Setup the rom access for 4M */
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amd8111_enable_rom();
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/* Is this a deliberate reset by the bios */
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if (bios_reset_detected() && last_boot_normal_x) {
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goto normal_image;
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}
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/* This is the primary cpu how should I boot? */
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else if (do_normal_boot()) {
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goto normal_image;
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}
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else {
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goto fallback_image;
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}
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normal_image:
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__asm__ volatile ("jmp __normal_image"
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: /* outputs */
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: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
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);
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fallback_image:
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#if HAVE_FAILOVER_BOOT==1
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__asm__ volatile ("jmp __fallback_image"
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: /* outputs */
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: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
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)
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#endif
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;
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}
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#endif
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void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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#if HAVE_FAILOVER_BOOT==1
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#if USE_FAILOVER_IMAGE==1
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failover_process(bist, cpu_init_detectedx);
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#else
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real_main(bist, cpu_init_detectedx);
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#endif
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#else
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#if USE_FALLBACK_IMAGE == 1
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failover_process(bist, cpu_init_detectedx);
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#endif
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real_main(bist, cpu_init_detectedx);
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#endif
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}
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#if USE_FAILOVER_IMAGE==0
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void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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static const uint16_t spd_addr[] = {
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//first node
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DIMM0, DIMM2, 0, 0,
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DIMM1, DIMM3, 0, 0,
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#if CONFIG_MAX_PHYSICAL_CPUS > 1
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//second node
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DIMM4, DIMM6, 0, 0,
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DIMM5, DIMM7, 0, 0,
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#endif
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};
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struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
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int needs_reset; int i;
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unsigned bsp_apicid = 0;
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if (bist == 0) {
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bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
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}
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w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
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uart_init();
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console_init();
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/* Halt if there was a built in self test failure */
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report_bist_failure(bist);
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print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
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setup_default_resource_map();
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print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
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#if MEM_TRAIN_SEQ == 1
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set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
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#endif
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setup_coherent_ht_domain(); // routing table and start other core0
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wait_all_core0_started();
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#if CONFIG_LOGICAL_CPUS==1
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// It is said that we should start core1 after all core0 launched
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/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
|
||||
* So here need to make sure last core0 is started, esp for two way system,
|
||||
* (there may be apic id conflicts in that case)
|
||||
*/
|
||||
start_other_cores();
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
#endif
|
||||
|
||||
/* it will set up chains and store link pair for optimization later */
|
||||
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
|
||||
|
||||
|
||||
#if K8_SET_FIDVID == 1
|
||||
|
||||
{
|
||||
msr_t msr;
|
||||
msr=rdmsr(0xc0010042);
|
||||
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
|
||||
|
||||
}
|
||||
|
||||
enable_fid_change();
|
||||
|
||||
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
|
||||
|
||||
init_fidvid_bsp(bsp_apicid);
|
||||
|
||||
// show final fid and vid
|
||||
{
|
||||
msr_t msr;
|
||||
msr=rdmsr(0xc0010042);
|
||||
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
needs_reset = optimize_link_coherent_ht();
|
||||
needs_reset |= optimize_link_incoherent_ht(sysinfo);
|
||||
|
||||
// fidvid change will issue one LDTSTOP and the HT change will be effective too
|
||||
if (needs_reset) {
|
||||
print_info("ht reset -\r\n");
|
||||
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
|
||||
}
|
||||
|
||||
allow_all_aps_stop(bsp_apicid);
|
||||
|
||||
//It's the time to set ctrl in sysinfo now;
|
||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
||||
|
||||
enable_smbus();
|
||||
|
||||
#if 0
|
||||
dump_smbus_registers();
|
||||
#endif
|
||||
|
||||
memreset_setup();
|
||||
|
||||
//do we need apci timer, tsc...., only debug need it for better output
|
||||
/* all ap stopped? */
|
||||
init_timer(); // Need to use TMICT to synconize FID/VID
|
||||
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
|
||||
|
||||
|
||||
#if 0
|
||||
dump_pci_devices();
|
||||
#endif
|
||||
|
||||
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
|
||||
|
||||
}
|
||||
#endif
|
||||
@@ -47,6 +47,26 @@ if HAVE_MP_TABLE object mptable.o end
|
||||
if HAVE_PIRQ_TABLE object irq_tables.o end
|
||||
#object reset.o
|
||||
|
||||
if USE_DCACHE_RAM
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
|
||||
makerule ./auto.o
|
||||
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
|
||||
end
|
||||
|
||||
else
|
||||
|
||||
makerule ./auto.inc
|
||||
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
|
||||
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
|
||||
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
|
||||
end
|
||||
|
||||
end
|
||||
else
|
||||
##
|
||||
## Romcc output
|
||||
##
|
||||
@@ -69,13 +89,27 @@ makerule ./auto.inc
|
||||
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit linuxBIOS entry code
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
end
|
||||
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
|
||||
if USE_DCACHE_RAM
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/amd/car/cache_as_ram.lds
|
||||
end
|
||||
end
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where linuxBIOS is entered)
|
||||
@@ -88,8 +122,11 @@ else
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
|
||||
if USE_DCACHE_RAM
|
||||
else
|
||||
### Should this be in the northbridge code?
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
end
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
@@ -97,20 +134,44 @@ mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
if USE_DCACHE_RAM
|
||||
##
|
||||
## Setup Cache-As-Ram
|
||||
##
|
||||
mainboardinit cpu/amd/car/cache_as_ram.inc
|
||||
end
|
||||
|
||||
###
|
||||
### This is the early phase of linuxBIOS startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
if USE_DCACHE_RAM
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
else
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
end
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
if USE_DCACHE_RAM
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
initobject auto.o
|
||||
else
|
||||
mainboardinit ./auto.inc
|
||||
end
|
||||
|
||||
else
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
@@ -120,11 +181,11 @@ mainboardinit cpu/x86/sse/enable_sse.inc
|
||||
mainboardinit ./auto.inc
|
||||
mainboardinit cpu/x86/sse/disable_sse.inc
|
||||
mainboardinit cpu/x86/mmx/disable_mmx.inc
|
||||
end
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/amd/amdk8/root_complex
|
||||
|
||||
@@ -48,7 +48,9 @@ uses CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses OBJCOPY
|
||||
|
||||
uses USE_DCACHE_RAM
|
||||
uses DCACHE_RAM_BASE
|
||||
uses DCACHE_RAM_SIZE
|
||||
uses CONFIG_USE_INIT
|
||||
|
||||
## ROM_SIZE is the size of boot ROM that this board will use.
|
||||
@@ -110,6 +112,14 @@ default CONFIG_MAX_PHYSICAL_CPUS=2
|
||||
##
|
||||
default CONFIG_IOAPIC=1
|
||||
|
||||
##
|
||||
## enable CACHE_AS_RAM specifics
|
||||
##
|
||||
default USE_DCACHE_RAM=1
|
||||
default DCACHE_RAM_BASE=0xcf000
|
||||
default DCACHE_RAM_SIZE=0x1000
|
||||
default CONFIG_USE_INIT=0
|
||||
|
||||
##
|
||||
## Clean up the motherboard id strings
|
||||
##
|
||||
|
||||
@@ -70,50 +70,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
|
||||
{
|
||||
/* Routing Table Node i
|
||||
*
|
||||
* F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
|
||||
* i: 0, 1, 2, 3, 4, 5, 6, 7
|
||||
*
|
||||
* [ 0: 3] Request Route
|
||||
* [0] Route to this node
|
||||
* [1] Route to Link 0
|
||||
* [2] Route to Link 1
|
||||
* [3] Route to Link 2
|
||||
* [11: 8] Response Route
|
||||
* [0] Route to this node
|
||||
* [1] Route to Link 0
|
||||
* [2] Route to Link 1
|
||||
* [3] Route to Link 2
|
||||
* [19:16] Broadcast route
|
||||
* [0] Route to this node
|
||||
* [1] Route to Link 0
|
||||
* [2] Route to Link 1
|
||||
* [3] Route to Link 2
|
||||
*/
|
||||
|
||||
uint32_t ret=0x00010101; /* default row entry */
|
||||
|
||||
static const unsigned int rows_2p[2][2] = {
|
||||
{ 0x00050101, 0x00010404 },
|
||||
{ 0x00010404, 0x00050101 }
|
||||
};
|
||||
|
||||
if(maxnodes>2) {
|
||||
print_debug("this mainboard is only designed for 2 cpus\r\n");
|
||||
maxnodes=2;
|
||||
}
|
||||
|
||||
|
||||
if (!(node>=maxnodes || row>=maxnodes)) {
|
||||
ret=rows_2p[node][row];
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline void activate_spd_rom(const struct mem_controller *ctrl)
|
||||
{
|
||||
/* nothing to do */
|
||||
|
||||
333
src/mainboard/iwill/dk8x/cache_as_ram_auto.c
Normal file
333
src/mainboard/iwill/dk8x/cache_as_ram_auto.c
Normal file
@@ -0,0 +1,333 @@
|
||||
#define ASSEMBLY 1
|
||||
#define __ROMCC__
|
||||
|
||||
#define RAMINIT_SYSINFO 1
|
||||
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
|
||||
|
||||
#define SET_NB_CFG_54 1
|
||||
|
||||
//used by raminit
|
||||
#define QRANK_DIMM_SUPPORT 1
|
||||
|
||||
//used by incoherent_ht
|
||||
//#define K8_SCAN_PCI_BUS 1
|
||||
//#define K8_ALLOCATE_IO_RANGE 1
|
||||
|
||||
|
||||
//used by init_cpus and fidvid
|
||||
#define K8_SET_FIDVID 0
|
||||
//if we want to wait for core1 done before DQS training, set it to 0
|
||||
#define K8_SET_FIDVID_CORE0_ONLY 1
|
||||
|
||||
#if K8_REV_F_SUPPORT == 1
|
||||
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include "option_table.h"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
|
||||
#if USE_FAILOVER_IMAGE==0
|
||||
#include "pc80/serial.c"
|
||||
#include "arch/i386/lib/console.c"
|
||||
#include <cpu/amd/model_fxx_rev.h>
|
||||
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
|
||||
#include "northbridge/amd/amdk8/raminit.h"
|
||||
#include "cpu/amd/model_fxx/apic_timer.c"
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
#include "northbridge/amd/amdk8/reset_test.c"
|
||||
|
||||
#if USE_FAILOVER_IMAGE==0
|
||||
#include "cpu/x86/bist.h"
|
||||
|
||||
#include "lib/delay.c"
|
||||
|
||||
#if CONFIG_USE_INIT == 0
|
||||
#include "lib/memcpy.c"
|
||||
// TODO: This doesn't compile at the moment. Fix later.
|
||||
// #if CONFIG_USE_PRINTK_IN_CAR == 1
|
||||
// #include "lib/uart8250.c"
|
||||
// #include "console/vtxprintf.c"
|
||||
// #include "arch/i386/lib/printk_init.c"
|
||||
// #endif
|
||||
#endif
|
||||
#include "northbridge/amd/amdk8/debug.c"
|
||||
#include "cpu/amd/mtrr/amd_earlymtrr.c"
|
||||
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
|
||||
|
||||
#include "northbridge/amd/amdk8/setup_resource_map.c"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
|
||||
|
||||
#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
|
||||
|
||||
/*
|
||||
* GPIO28 of 8111 will control H0_MEMRESET_L
|
||||
* GPIO29 of 8111 will control H1_MEMRESET_L
|
||||
*/
|
||||
static void memreset_setup(void)
|
||||
{
|
||||
if (is_cpu_pre_c0()) {
|
||||
/* Set the memreset low */
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
|
||||
/* Ensure the BIOS has control of the memory lines */
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
|
||||
} else {
|
||||
/* Ensure the CPU has controll of the memory lines */
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
|
||||
}
|
||||
}
|
||||
|
||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||
{
|
||||
if (is_cpu_pre_c0()) {
|
||||
udelay(800);
|
||||
/* Set memreset_high */
|
||||
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
|
||||
udelay(90);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void activate_spd_rom(const struct mem_controller *ctrl)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/amd/amdk8/amdk8.h"
|
||||
#include "northbridge/amd/amdk8/coherent_ht_car.c"
|
||||
|
||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||
|
||||
#include "northbridge/amd/amdk8/raminit.c"
|
||||
|
||||
#include "sdram/generic_sdram.c"
|
||||
#include "ram/ramtest.c"
|
||||
|
||||
/* tyan does not want the default */
|
||||
#include "northbridge/amd/amdk8/resourcemap.c"
|
||||
|
||||
#include "cpu/amd/dualcore/dualcore.c"
|
||||
|
||||
#define DIMM0 0x50
|
||||
#define DIMM1 0x51
|
||||
#define DIMM2 0x52
|
||||
#define DIMM3 0x53
|
||||
#define DIMM4 0x54
|
||||
#define DIMM5 0x55
|
||||
#define DIMM6 0x56
|
||||
#define DIMM7 0x57
|
||||
|
||||
|
||||
#include "cpu/amd/car/copy_and_run.c"
|
||||
#include "cpu/amd/car/post_cache_as_ram.c"
|
||||
|
||||
#include "cpu/amd/model_fxx/init_cpus.c"
|
||||
|
||||
#include "cpu/amd/model_fxx/fidvid.c"
|
||||
#endif
|
||||
|
||||
#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
|
||||
|
||||
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
|
||||
#include "northbridge/amd/amdk8/early_ht.c"
|
||||
|
||||
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
|
||||
unsigned last_boot_normal_x = last_boot_normal();
|
||||
|
||||
/* Is this a cpu only reset? or Is this a secondary cpu? */
|
||||
if ((cpu_init_detectedx) || (!boot_cpu())) {
|
||||
if (last_boot_normal_x) {
|
||||
goto normal_image;
|
||||
} else {
|
||||
goto fallback_image;
|
||||
}
|
||||
}
|
||||
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
|
||||
enumerate_ht_chain();
|
||||
|
||||
/* Setup the rom access for 4M */
|
||||
amd8111_enable_rom();
|
||||
|
||||
/* Is this a deliberate reset by the bios */
|
||||
if (bios_reset_detected() && last_boot_normal_x) {
|
||||
goto normal_image;
|
||||
}
|
||||
/* This is the primary cpu how should I boot? */
|
||||
else if (do_normal_boot()) {
|
||||
goto normal_image;
|
||||
}
|
||||
else {
|
||||
goto fallback_image;
|
||||
}
|
||||
normal_image:
|
||||
__asm__ volatile ("jmp __normal_image"
|
||||
: /* outputs */
|
||||
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
|
||||
);
|
||||
|
||||
fallback_image:
|
||||
#if HAVE_FAILOVER_BOOT==1
|
||||
__asm__ volatile ("jmp __fallback_image"
|
||||
: /* outputs */
|
||||
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
|
||||
)
|
||||
#endif
|
||||
;
|
||||
}
|
||||
#endif
|
||||
|
||||
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
#if HAVE_FAILOVER_BOOT==1
|
||||
#if USE_FAILOVER_IMAGE==1
|
||||
failover_process(bist, cpu_init_detectedx);
|
||||
#else
|
||||
real_main(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
#else
|
||||
#if USE_FALLBACK_IMAGE == 1
|
||||
failover_process(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
real_main(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if USE_FAILOVER_IMAGE==0
|
||||
|
||||
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
static const uint16_t spd_addr[] = {
|
||||
//first node
|
||||
DIMM0, DIMM2, 0, 0,
|
||||
DIMM1, DIMM3, 0, 0,
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 1
|
||||
//second node
|
||||
DIMM4, DIMM6, 0, 0,
|
||||
DIMM5, DIMM7, 0, 0,
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
|
||||
|
||||
int needs_reset; int i;
|
||||
unsigned bsp_apicid = 0;
|
||||
|
||||
if (bist == 0) {
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
|
||||
}
|
||||
|
||||
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
|
||||
|
||||
setup_default_resource_map();
|
||||
|
||||
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
|
||||
|
||||
#if MEM_TRAIN_SEQ == 1
|
||||
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
|
||||
#endif
|
||||
setup_coherent_ht_domain(); // routing table and start other core0
|
||||
|
||||
wait_all_core0_started();
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
// It is said that we should start core1 after all core0 launched
|
||||
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
|
||||
* So here need to make sure last core0 is started, esp for two way system,
|
||||
* (there may be apic id conflicts in that case)
|
||||
*/
|
||||
start_other_cores();
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
#endif
|
||||
|
||||
/* it will set up chains and store link pair for optimization later */
|
||||
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
|
||||
|
||||
|
||||
#if K8_SET_FIDVID == 1
|
||||
|
||||
{
|
||||
msr_t msr;
|
||||
msr=rdmsr(0xc0010042);
|
||||
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
|
||||
|
||||
}
|
||||
|
||||
enable_fid_change();
|
||||
|
||||
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
|
||||
|
||||
init_fidvid_bsp(bsp_apicid);
|
||||
|
||||
// show final fid and vid
|
||||
{
|
||||
msr_t msr;
|
||||
msr=rdmsr(0xc0010042);
|
||||
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
needs_reset = optimize_link_coherent_ht();
|
||||
needs_reset |= optimize_link_incoherent_ht(sysinfo);
|
||||
|
||||
// fidvid change will issue one LDTSTOP and the HT change will be effective too
|
||||
if (needs_reset) {
|
||||
print_info("ht reset -\r\n");
|
||||
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
|
||||
}
|
||||
|
||||
allow_all_aps_stop(bsp_apicid);
|
||||
|
||||
//It's the time to set ctrl in sysinfo now;
|
||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
||||
|
||||
enable_smbus();
|
||||
|
||||
#if 0
|
||||
dump_smbus_registers();
|
||||
#endif
|
||||
|
||||
memreset_setup();
|
||||
|
||||
//do we need apci timer, tsc...., only debug need it for better output
|
||||
/* all ap stopped? */
|
||||
init_timer(); // Need to use TMICT to synconize FID/VID
|
||||
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
|
||||
|
||||
|
||||
#if 0
|
||||
dump_pci_devices();
|
||||
#endif
|
||||
|
||||
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
|
||||
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user