From 7195cee17f0c2ac74806ae3a1005333c26f126e5 Mon Sep 17 00:00:00 2001 From: Krishna P Bhat D Date: Thu, 21 Apr 2022 12:20:44 +0530 Subject: [PATCH] soc/intel/alderlake: Add check for CSE FW sync in romstage Some Alder Lake-N boards will use compressed ME RW blobs to obtain savings on the SPI size (1916KB before compression, ~1132KB after compression). So add an additional check before calling cse_fw_sync() from romstage. When compressed blobs are used, the call to CSE firmware update has to be in post-RAM stages. BRANCH=firmware-brya-14505.B Change-Id: I0d9ede52cb493974e4ba6e2e2cf11c9789b3b087 Signed-off-by: Krishna P Bhat D Reviewed-on: https://review.coreboot.org/c/coreboot/+/63760 Reviewed-by: Kangheui Won Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi Reviewed-by: Eric Lai --- src/soc/intel/alderlake/romstage/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index 31e629ccb5..f133910197 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -140,7 +140,7 @@ void mainboard_romstage_entry(void) s3wake = pmc_fill_power_state(ps) == ACPI_S3; - if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && !s3wake) { + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) { timestamp_add_now(TS_CSE_FW_SYNC_START); cse_fw_sync(); timestamp_add_now(TS_CSE_FW_SYNC_END);