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failed attempt to do early init for cs5535. Almost there but

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still get garbage reading smbus.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2192 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Li-Ta Lo
2006-03-13 21:58:43 +00:00
parent ec9cdc980f
commit 71eae20b30
5 changed files with 110 additions and 118 deletions
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31
src/include/cpu/amd/gx2def.h
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@@ -0,0 +1,31 @@
#ifndef CPU_AMD_GX2DEF_H
#define CPU_AMD_GX2DEF_H
/* GeodeLink Control Processor Registers, GLIU1, Port 3 */
#define GLCP_CLK_DIS_DELAY 0x4c000008
#define GLCP_PMCLKDISABLE 0x4c000009
#define GLCP_DELAY_CONTROLS 0x4c00000f
#define GLCP_SYS_RSTPLL 0x4c000014
#define GLCP_DOTPLL 0x4c000015
/* Upper 32 bits */
#define GLCP_SYS_RSTPLL_MDIV_SHIFT 9
#define GLCP_SYS_RSTPLL_VDIV_SHIFT 6
#define GLCP_SYS_RSTPLL_FBDIV_SHIFT 0
/* Lower 32 bits */
#define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26
#define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26)
#define GLCP_SYS_RSTPLL_LOCKWAIT 24
#define GLCP_SYS_RSTPLL_HOLDCOUNT 16
#define GLCP_SYS_RSTPLL_BYPASS 15
#define GLCP_SYS_RSTPLL_PD 14
#define GLCP_SYS_RSTPLL_RESETPLL 13
#define GLCP_SYS_RSTPLL_DDRMODE 10
#define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE 9
#define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE 8
#define GLCP_SYS_RSTPLL_CHIP_RESET 0
#endif /* CPU_AMD_GX2DEF_H */