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gaze18-40x0: enable NVIDIA GPU

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Change-Id: Iefb6de5bdc481934d7c661516c05ee945e8717db
This commit is contained in:
Jeremy Soller
2023-02-10 12:43:57 -07:00
parent d30cad4127
commit 71f18f129f
3 changed files with 5 additions and 3 deletions
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4
src/mainboard/system76/rpl/variants/gaze18-40x0/gpio.c
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@@ -148,7 +148,7 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_F6, NONE), PAD_NC(GPP_F6, NONE),
PAD_CFG_GPI(GPP_F7, NONE, PLTRST), PAD_CFG_GPI(GPP_F7, NONE, PLTRST),
PAD_CFG_GPI(GPP_F8, NONE, DEEP), PAD_CFG_GPI(GPP_F8, NONE, DEEP),
PAD_CFG_GPO(GPP_F9, 1, DEEP), // GPP_F9 (DGPU_PWR_EN) configured in bootblock
PAD_NC(GPP_F10, NONE), PAD_NC(GPP_F10, NONE),
PAD_NC(GPP_F11, NONE), PAD_NC(GPP_F11, NONE),
PAD_NC(GPP_F12, NONE), PAD_NC(GPP_F12, NONE),
@@ -270,7 +270,7 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_R13, NONE), PAD_NC(GPP_R13, NONE),
PAD_NC(GPP_R14, NONE), PAD_NC(GPP_R14, NONE),
PAD_NC(GPP_R15, NONE), PAD_NC(GPP_R15, NONE),
PAD_CFG_GPO(GPP_R16, 1, DEEP), // GPP_R16 (DGPU_RST#_PCH) configured in bootblock
PAD_NC(GPP_R17, NONE), PAD_NC(GPP_R17, NONE),
PAD_NC(GPP_R18, NONE), PAD_NC(GPP_R18, NONE),
PAD_NC(GPP_R19, NONE), PAD_NC(GPP_R19, NONE),

2
src/mainboard/system76/rpl/variants/gaze18-40x0/gpio_early.c
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@@ -6,6 +6,8 @@
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN
PAD_CFG_GPO(GPP_R16, 0, DEEP), // DGPU_RST#_PCH
}; };
void mainboard_configure_early_gpios(void) void mainboard_configure_early_gpios(void)

2
src/mainboard/system76/rpl/variants/gaze18-40x0/overridetree.cb
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@@ -19,7 +19,7 @@ chip soc/intel/alderlake
end end
#TODO: Reversed #TODO: Reversed
device ref pcie5_1 off device ref pcie5_0 on
# CPU PCIe RP#2 x8, Clock 14 (DGPU) # CPU PCIe RP#2 x8, Clock 14 (DGPU)
register "cpu_pcie_rp[CPU_RP(2)]" = "{ register "cpu_pcie_rp[CPU_RP(2)]" = "{
.clk_src = 14, .clk_src = 14,