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Rename SANDYBRIDGE_BCLK to NEHALEM_BCLK in 2065x.

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2065x is with nehalem and not sandybridge.

I don't care much eitherway but it clears some confusion.

Change-Id: Ib2b8e570b830a12ed8d0d313ee4eb56755796d4b
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4046
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Vladimir Serbinenko 2013-11-12 23:32:52 +01:00 committed by Kyösti Mälkki
parent e2b6795e04
commit 71f35ebdaa
4 changed files with 6 additions and 6 deletions
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4
src/cpu/intel/model_2065x/acpi.c
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@ -237,7 +237,7 @@ static int generate_P_state_entries(int core, int cores_per_package)
/* Max Non-Turbo Ratio */ /* Max Non-Turbo Ratio */
ratio_max = (msr.lo >> 8) & 0xff; ratio_max = (msr.lo >> 8) & 0xff;
} }
clock_max = ratio_max * SANDYBRIDGE_BCLK + ratio_max / 3; clock_max = ratio_max * NEHALEM_BCLK + ratio_max / 3;
/* Calculate CPU TDP in mW */ /* Calculate CPU TDP in mW */
power_max = 25000; power_max = 25000;
@ -298,7 +298,7 @@ static int generate_P_state_entries(int core, int cores_per_package)
/* Calculate power at this ratio */ /* Calculate power at this ratio */
power = calculate_power(power_max, ratio_max, ratio); power = calculate_power(power_max, ratio_max, ratio);
clock = ratio * SANDYBRIDGE_BCLK + ratio / 3; clock = ratio * NEHALEM_BCLK + ratio / 3;
len_pss += acpigen_write_PSS_package( len_pss += acpigen_write_PSS_package(
clock, /*MHz*/ clock, /*MHz*/

4
src/cpu/intel/model_2065x/model_2065x.h
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@ -22,8 +22,8 @@
#ifndef _CPU_INTEL_MODEL_2065X_H #ifndef _CPU_INTEL_MODEL_2065X_H
#define _CPU_INTEL_MODEL_2065X_H #define _CPU_INTEL_MODEL_2065X_H
/* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ /* Nehalem bus clock is fixed at 133MHz */
#define SANDYBRIDGE_BCLK 133 #define NEHALEM_BCLK 133
#define IA32_FEATURE_CONTROL 0x3a #define IA32_FEATURE_CONTROL 0x3a
#define CPUID_VMX (1 << 5) #define CPUID_VMX (1 << 5)

2
src/cpu/intel/model_2065x/model_2065x_init.c
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@ -311,7 +311,7 @@ static void set_max_ratio(void)
wrmsr(IA32_PERF_CTL, perf_ctl); wrmsr(IA32_PERF_CTL, perf_ctl);
printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n", printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n",
((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK); ((perf_ctl.lo >> 8) & 0xff) * NEHALEM_BCLK);
} }
static void set_energy_perf_bias(u8 policy) static void set_energy_perf_bias(u8 policy)

2
src/cpu/intel/model_2065x/tsc_freq.c
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@ -27,5 +27,5 @@ unsigned long tsc_freq_mhz(void)
msr_t platform_info; msr_t platform_info;
platform_info = rdmsr(MSR_PLATFORM_INFO); platform_info = rdmsr(MSR_PLATFORM_INFO);
return SANDYBRIDGE_BCLK * ((platform_info.lo >> 8) & 0xff); return NEHALEM_BCLK * ((platform_info.lo >> 8) & 0xff);
} }