inteltool: add 300 and C240 Series PCH
Values from - Intel doc 337347 rev4 - coreboot soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h On Coffeelake H (using Cannonlake / Cannonpoint PCH) p2sb is not accessible. Using a static value instead. 0xfd000000 is a common value chosen by coreboot and non-coreboot firmware. Change-Id: Id637f703ab0a99eb0908ecdc3da27ba80db1c6b8 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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committed by
Patrick Georgi
parent
02bd77379b
commit
725369fd0c
@@ -71,6 +71,8 @@ void pcr_init(struct pci_dev *const sb)
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bool error_exit = false;
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bool p2sb_revealed = false;
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struct pci_dev *p2sb;
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bool use_p2sb = true;
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pciaddr_t sbbar_phys;
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if (sbbar)
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return;
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@@ -103,38 +105,54 @@ void pcr_init(struct pci_dev *const sb)
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case PCI_DEVICE_ID_INTEL_APL_LPC:
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p2sb = pci_get_dev(sb->access, 0, 0, 0x0d, 0);
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break;
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case PCI_DEVICE_ID_INTEL_H310:
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case PCI_DEVICE_ID_INTEL_H370:
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case PCI_DEVICE_ID_INTEL_Z390:
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case PCI_DEVICE_ID_INTEL_Q370:
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case PCI_DEVICE_ID_INTEL_B360:
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case PCI_DEVICE_ID_INTEL_C246:
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case PCI_DEVICE_ID_INTEL_C242:
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case PCI_DEVICE_ID_INTEL_QM370:
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case PCI_DEVICE_ID_INTEL_HM370:
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case PCI_DEVICE_ID_INTEL_CM246:
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sbbar_phys = 0xfd000000;
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use_p2sb = false;
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break;
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default:
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perror("Unknown LPC device.");
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exit(1);
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}
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if (!p2sb) {
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perror("Can't allocate device node for P2SB.");
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exit(1);
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}
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/* do not fill bases here, libpci refuses to refill later */
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pci_fill_info(p2sb, PCI_FILL_IDENT);
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if (p2sb->vendor_id == 0xffff && p2sb->device_id == 0xffff) {
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printf("Trying to reveal Primary to Sideband Bridge "
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"(P2SB),\nlet's hope the OS doesn't mind... ");
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/* Do not use pci_write_long(). Bytes
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surrounding 0xe0 must be maintained. */
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pci_write_byte(p2sb, 0xe0 + 1, 0);
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pci_fill_info(p2sb, PCI_FILL_IDENT | PCI_FILL_RESCAN);
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if (p2sb->vendor_id != 0xffff ||
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p2sb->device_id != 0xffff) {
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printf("done.\n");
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p2sb_revealed = true;
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} else {
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printf("failed.\n");
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if (use_p2sb) {
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if (!p2sb) {
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perror("Can't allocate device node for P2SB.");
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exit(1);
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}
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}
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pci_fill_info(p2sb, PCI_FILL_BASES | PCI_FILL_CLASS);
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const pciaddr_t sbbar_phys = p2sb->base_addr[0] & ~0xfULL;
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/* do not fill bases here, libpci refuses to refill later */
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pci_fill_info(p2sb, PCI_FILL_IDENT);
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if (p2sb->vendor_id == 0xffff && p2sb->device_id == 0xffff) {
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printf("Trying to reveal Primary to Sideband Bridge "
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"(P2SB),\nlet's hope the OS doesn't mind... ");
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/* Do not use pci_write_long(). Bytes
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surrounding 0xe0 must be maintained. */
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pci_write_byte(p2sb, 0xe0 + 1, 0);
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pci_fill_info(p2sb, PCI_FILL_IDENT | PCI_FILL_RESCAN);
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if (p2sb->vendor_id != 0xffff ||
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p2sb->device_id != 0xffff) {
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printf("done.\n");
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p2sb_revealed = true;
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} else {
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printf("failed.\n");
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exit(1);
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}
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}
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pci_fill_info(p2sb, PCI_FILL_BASES | PCI_FILL_CLASS);
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sbbar_phys = p2sb->base_addr[0] & ~0xfULL;
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}
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printf("SBREG_BAR = 0x%08"PRIx64" (MEM)\n\n", (uint64_t)sbbar_phys);
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sbbar = map_physical(sbbar_phys, SBBAR_SIZE);
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if (sbbar == NULL) {
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@@ -142,11 +160,13 @@ void pcr_init(struct pci_dev *const sb)
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error_exit = true;
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}
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if (p2sb_revealed) {
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printf("Hiding Primary to Sideband Bridge (P2SB).\n");
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pci_write_byte(p2sb, 0xe0 + 1, 1);
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if (use_p2sb) {
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if (p2sb_revealed) {
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printf("Hiding Primary to Sideband Bridge (P2SB).\n");
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pci_write_byte(p2sb, 0xe0 + 1, 1);
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}
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pci_free_dev(p2sb);
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}
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pci_free_dev(p2sb);
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if (error_exit)
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exit(1);
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