From 726051be6926ea38bc4dea99f47a150c58252abc Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jeremy@system76.com>
Date: Thu, 17 Jun 2021 13:37:24 -0600
Subject: [PATCH] soc/intel/tigerlake: Set correct PCH-H
 PCR_PSF3_T0_SHDW_PMC_REG_BASE

Change-Id: Id5b0cfeed35d1be0dc6ca03cb0c7a2fca4277676
---
 src/soc/intel/tigerlake/bootblock/pch.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c
index 5a63b40c21..eb387d3843 100644
--- a/src/soc/intel/tigerlake/bootblock/pch.c
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@@ -28,7 +28,11 @@
 #include <soc/pcr_ids.h>
 #include <soc/pm.h>
 
+#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H)
+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE	0x1000
+#else
 #define PCR_PSF3_TO_SHDW_PMC_REG_BASE	0x1100
+#endif
 #define PCR_PSFX_TO_SHDW_BAR0	0
 #define PCR_PSFX_TO_SHDW_BAR1	0x4
 #define PCR_PSFX_TO_SHDW_BAR2	0x8