From 729a256348f59dfc7b291d3763146948b7f12b07 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Wed, 19 Aug 2020 11:35:27 -0600 Subject: [PATCH] soc/intel/cannonlake: Allow PCIe root port #1 to use clockreq --- src/soc/intel/cannonlake/fsp_params.c | 2 ++ src/soc/intel/cannonlake/include/soc/pch.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 57e26ec0b4..7fb695ba98 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -468,6 +468,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { if (config->PcieClkSrcUsage[i] == 0) config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED; + else if (config->PcieClkSrcUsage[i] == PCIE_CLK_RP0) + config->PcieClkSrcUsage[i] = 0; } memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage, sizeof(config->PcieClkSrcUsage)); diff --git a/src/soc/intel/cannonlake/include/soc/pch.h b/src/soc/intel/cannonlake/include/soc/pch.h index 778b26981b..6eda85755a 100644 --- a/src/soc/intel/cannonlake/include/soc/pch.h +++ b/src/soc/intel/cannonlake/include/soc/pch.h @@ -11,5 +11,7 @@ #define PCIE_CLK_NOTUSED 0xFF #define PCIE_CLK_LAN 0x70 #define PCIE_CLK_FREE 0x80 +// Converted to 0, allows 0 to be notused +#define PCIE_CLK_RP0 0xFE #endif