From 72bc5f2b46cccfc8c8cc11fa769ff88e6acba69e Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Wed, 27 Jan 2021 09:35:44 -0700 Subject: [PATCH] mb/system76: Don't set SaGv for H series boards Per the FSP integration guides, Geyserville only affects ULX/ULT CPUs. Change-Id: I25edc19ae9d3ea949a214c04d8af11c2cc1f3082 --- src/mainboard/system76/addw1/devicetree.cb | 1 - src/mainboard/system76/addw2/devicetree.cb | 1 - src/mainboard/system76/gaze14/devicetree.cb | 1 - src/mainboard/system76/gaze15/devicetree.cb | 1 - src/mainboard/system76/oryp5/devicetree.cb | 1 - src/mainboard/system76/oryp6/devicetree.cb | 1 - src/mainboard/system76/thelio-b1/devicetree.cb | 1 - 7 files changed, 7 deletions(-) diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb index 95c8d62f9f..cfaf57502b 100644 --- a/src/mainboard/system76/addw1/devicetree.cb +++ b/src/mainboard/system76/addw1/devicetree.cb @@ -20,7 +20,6 @@ chip soc/intel/cannonlake register "eist_enable" = "1" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "SaGv" = "SaGv_Enabled" register "enable_c6dram" = "1" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) diff --git a/src/mainboard/system76/addw2/devicetree.cb b/src/mainboard/system76/addw2/devicetree.cb index d224d0f14d..fb46d9fe1c 100644 --- a/src/mainboard/system76/addw2/devicetree.cb +++ b/src/mainboard/system76/addw2/devicetree.cb @@ -20,7 +20,6 @@ chip soc/intel/cannonlake register "eist_enable" = "1" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "SaGv" = "SaGv_Enabled" register "enable_c6dram" = "1" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) diff --git a/src/mainboard/system76/gaze14/devicetree.cb b/src/mainboard/system76/gaze14/devicetree.cb index 147c85bca0..0f1c156422 100644 --- a/src/mainboard/system76/gaze14/devicetree.cb +++ b/src/mainboard/system76/gaze14/devicetree.cb @@ -23,7 +23,6 @@ chip soc/intel/cannonlake register "eist_enable" = "1" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "SaGv" = "SaGv_Enabled" register "enable_c6dram" = "1" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index 2077c63837..f7eaf30c46 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -20,7 +20,6 @@ chip soc/intel/cannonlake register "eist_enable" = "1" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "SaGv" = "SaGv_Enabled" register "enable_c6dram" = "1" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index 9f60d1822e..256cd5300c 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -20,7 +20,6 @@ chip soc/intel/cannonlake register "eist_enable" = "1" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "SaGv" = "SaGv_Enabled" register "enable_c6dram" = "1" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index f594bdb090..78f5807259 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -20,7 +20,6 @@ chip soc/intel/cannonlake register "eist_enable" = "1" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "SaGv" = "SaGv_Enabled" register "enable_c6dram" = "1" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) diff --git a/src/mainboard/system76/thelio-b1/devicetree.cb b/src/mainboard/system76/thelio-b1/devicetree.cb index 930a8499e8..488e7681f0 100644 --- a/src/mainboard/system76/thelio-b1/devicetree.cb +++ b/src/mainboard/system76/thelio-b1/devicetree.cb @@ -21,7 +21,6 @@ chip soc/intel/cannonlake register "eist_enable" = "1" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "SaGv" = "SaGv_Enabled" #register "enable_c6dram" = "1" # FSP Silicon (soc/intel/cannonlake/fsp_params.c)