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soc/intel/tigerlake: Switch to runtime generation of Intel Power Engine

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The pep.asl file is being obsoleted by runtime generation, therefore
switch tigerlake boards to this method.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8e97c589273e934e89d69d8829680b9cac1ff9f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Tim Wawrzynczak
2021-07-01 08:25:11 -06:00
parent 90f9cbbfc4
commit 72d94026ce
3 changed files with 16 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/intel/tigerlake/Kconfig
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@@ -48,6 +48,8 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_ACPI
select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
select SOC_INTEL_COMMON_BLOCK_ACPI_PEP
select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ
select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CAR
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CNVI select SOC_INTEL_COMMON_BLOCK_CNVI

3
src/soc/intel/tigerlake/acpi/southbridge.asl
View File

@@ -42,8 +42,5 @@
/* PCI _OSC */ /* PCI _OSC */
#include <soc/intel/common/acpi/pci_osc.asl> #include <soc/intel/common/acpi/pci_osc.asl>
/* Intel Power Engine Plug-in */
#include <soc/intel/common/block/acpi/acpi/pep.asl>
/* GbE 0:1f.6 */ /* GbE 0:1f.6 */
#include <soc/intel/common/block/acpi/acpi/pch_glan.asl> #include <soc/intel/common/block/acpi/acpi/pch_glan.asl>

14
src/soc/intel/tigerlake/pmc.c
View File

@@ -11,10 +11,12 @@
#include <device/mmio.h> #include <device/mmio.h>
#include <device/device.h> #include <device/device.h>
#include <drivers/intel/pmc_mux/chip.h> #include <drivers/intel/pmc_mux/chip.h>
#include <intelblocks/acpi.h>
#include <intelblocks/pmc.h> #include <intelblocks/pmc.h>
#include <intelblocks/pmclib.h> #include <intelblocks/pmclib.h>
#include <intelblocks/pmc_ipc.h> #include <intelblocks/pmc_ipc.h>
#include <intelblocks/rtc.h> #include <intelblocks/rtc.h>
#include <soc/lpm.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/pm.h> #include <soc/pm.h>
#include <soc/soc_chip.h> #include <soc/soc_chip.h>
@@ -121,6 +123,18 @@ static void soc_pmc_fill_ssdt(const struct device *dev)
acpigen_pop_len(); /* PMC Device */ acpigen_pop_len(); /* PMC Device */
acpigen_pop_len(); /* Scope */ acpigen_pop_len(); /* Scope */
if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP)) {
const struct soc_pmc_lpm tgl_pmc_lpm = {
.num_substates = 8,
.num_req_regs = 6,
.lpm_ipc_offset = 0x1000,
.req_reg_stride = 0x30,
.lpm_enable_mask = get_supported_lpm_mask(config_of_soc()),
};
generate_acpi_power_engine_with_lpm(&tgl_pmc_lpm);
}
printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name, printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name,
dev_path(dev)); dev_path(dev));
} }