arch/x86: Make RELOCATABLE_RAMSTAGE the default

No need to provide an option to try disable this.

Also remove explicit ´select RELOCATABLE_MODULES'
lines from platform Kconfigs.

Change-Id: I5fb169f90331ce37b4113378405323ec856d6fee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/Kconfig

@@ -233,8 +233,9 @@ config NO_RELOCATABLE_RAMSTAGE
 	default y
 
 config RELOCATABLE_RAMSTAGE
+	bool
 	depends on EARLY_CBMEM_INIT
-	bool "Build the ramstage to be relocatable in 32-bit address space."
+	default !NO_RELOCATABLE_RAMSTAGE
 	select RELOCATABLE_MODULES
 	help
 	 The reloctable ramstage support allows for the ramstage to be built

src/cpu/intel/haswell/Kconfig

@@ -18,8 +18,6 @@ config CPU_SPECIFIC_OPTIONS
 	select UDELAY_TSC
 	select TSC_CONSTANT_RATE
 	select SMM_TSEG
-	select RELOCATABLE_MODULES
-	select RELOCATABLE_RAMSTAGE
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	#select AP_IN_SIPI_WAIT
 	select TSC_SYNC_MFENCE
@@ -46,7 +44,6 @@ config SMM_RESERVED_SIZE
 config RESET_ON_INVALID_RAMSTAGE_CACHE
 	bool "Reset the system on S3 wake when ramstage cache invalid."
 	default n
-	depends on RELOCATABLE_RAMSTAGE
 	help
 	  The haswell romstage code caches the loaded ramstage program
 	  in SMM space. On S3 wake the romstage will copy over a fresh

src/northbridge/amd/agesa/Kconfig

@@ -16,7 +16,6 @@
 config NORTHBRIDGE_AMD_AGESA
 	bool
 	default CPU_AMD_AGESA
-	select RELOCATABLE_RAMSTAGE if EARLY_CBMEM_INIT
 	select CBMEM_TOP_BACKUP
 
 if NORTHBRIDGE_AMD_AGESA

src/northbridge/amd/pi/Kconfig

@@ -18,7 +18,6 @@ config NORTHBRIDGE_AMD_PI
 	default y if CPU_AMD_PI
 	default n
 	select CBMEM_TOP_BACKUP
-	select RELOCATABLE_RAMSTAGE
 
 if NORTHBRIDGE_AMD_PI
 

src/northbridge/intel/e7505/Kconfig

@@ -22,7 +22,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select NO_MMCONF_SUPPORT
 	select HAVE_DEBUG_RAM_SETUP
-	select RELOCATABLE_RAMSTAGE
 	select POSTCAR_STAGE
 
 config HW_SCRUBBER

src/northbridge/intel/gm45/Kconfig

@@ -26,7 +26,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
 	select INTEL_EDID
 	select INTEL_GMA_ACPI
 	select INTEL_GMA_SSC_ALTERNATE_REF
-	select RELOCATABLE_RAMSTAGE
 	select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
 	select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
 	select POSTCAR_STAGE

src/northbridge/intel/haswell/Kconfig

@@ -19,7 +19,6 @@ config NORTHBRIDGE_INTEL_HASWELL
 	select CACHE_MRC_SETTINGS
 	select INTEL_DDI
 	select INTEL_GMA_ACPI
-	select RELOCATABLE_RAMSTAGE
 	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
 	select POSTCAR_STAGE
 	select POSTCAR_CONSOLE

src/northbridge/intel/i945/Kconfig

@@ -25,7 +25,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
 	select VGA
 	select INTEL_GMA_ACPI
 	select INTEL_GMA_SSC_ALTERNATE_REF
-	select RELOCATABLE_RAMSTAGE
 	select INTEL_EDID
 	select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
 	select POSTCAR_STAGE

src/northbridge/intel/nehalem/Kconfig

@@ -20,7 +20,6 @@ config NORTHBRIDGE_INTEL_NEHALEM
 	select INTEL_EDID
 	select TSC_MONOTONIC_TIMER
 	select INTEL_GMA_ACPI
-	select RELOCATABLE_RAMSTAGE
 	select CACHE_MRC_SETTINGS
 	select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
 	select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT

src/northbridge/intel/pineview/Kconfig

@@ -27,7 +27,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
 	select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
 	select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT
-	select RELOCATABLE_RAMSTAGE
 	select INTEL_GMA_ACPI
 	select POSTCAR_STAGE
 	select POSTCAR_CONSOLE

src/northbridge/intel/sandybridge/Kconfig

@@ -20,7 +20,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE
 	select CPU_INTEL_MODEL_206AX
 	select HAVE_DEBUG_RAM_SETUP
 	select INTEL_GMA_ACPI
-	select RELOCATABLE_RAMSTAGE
 	select POSTCAR_STAGE
 	select POSTCAR_CONSOLE
 
@@ -30,7 +29,6 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE
 	select CPU_INTEL_MODEL_306AX
 	select HAVE_DEBUG_RAM_SETUP
 	select INTEL_GMA_ACPI
-	select RELOCATABLE_RAMSTAGE
 	select POSTCAR_STAGE
 	select POSTCAR_CONSOLE
 

src/northbridge/intel/x4x/Kconfig

@@ -25,7 +25,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
 	select LAPIC_MONOTONIC_TIMER
 	select VGA
 	select INTEL_GMA_ACPI
-	select RELOCATABLE_RAMSTAGE
 	select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
 	select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
 	select CACHE_MRC_SETTINGS

src/soc/amd/stoneyridge/Kconfig

@@ -56,13 +56,11 @@ config CPU_SPECIFIC_OPTIONS
 	select BOOTBLOCK_CONSOLE
 	select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
 	select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
-	select RELOCATABLE_MODULES
 	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
 	select PARALLEL_MP
 	select PARALLEL_MP_AP_WORK
 	select HAVE_SMI_HANDLER
 	select SMM_TSEG
-	select RELOCATABLE_RAMSTAGE
 	select POSTCAR_STAGE
 	select POSTCAR_CONSOLE
 	select SSE

src/soc/intel/apollolake/Kconfig

@@ -40,7 +40,7 @@ config CPU_SPECIFIC_OPTIONS
 	# Misc options
 	select C_ENVIRONMENT_BOOTBLOCK
 	select CACHE_MRC_SETTINGS
-	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE
+	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
 	select COLLECT_TIMESTAMPS
 	select COMMON_FADT
 	select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
@@ -62,7 +62,6 @@ config CPU_SPECIFIC_OPTIONS
 	select POSTCAR_STAGE
 	select PMC_INVALID_READ_AFTER_WRITE
 	select REG_SCRIPT
-	select RELOCATABLE_RAMSTAGE	# Build fails if this is not selected
 	select RTC
 	select SMM_TSEG
 	select SA_ENABLE_IMR

src/soc/intel/baytrail/Kconfig

@@ -19,8 +19,6 @@ config CPU_SPECIFIC_OPTIONS
 	select HAVE_SMI_HANDLER
 	select HAVE_HARD_RESET
 	select NO_FIXED_XIP_ROM_SIZE
-	select RELOCATABLE_MODULES
-	select RELOCATABLE_RAMSTAGE
 	select PARALLEL_MP
 	select PCIEXP_ASPM
 	select PCIEXP_COMMON_CLOCK
@@ -137,7 +135,6 @@ config DCACHE_RAM_MRC_VAR_SIZE
 config RESET_ON_INVALID_RAMSTAGE_CACHE
 	bool "Reset the system on S3 wake when ramstage cache invalid."
 	default n
-	depends on RELOCATABLE_RAMSTAGE
 	help
 	  The baytrail romstage code caches the loaded ramstage program
 	  in SMM space. On S3 wake the romstage will copy over a fresh

src/soc/intel/braswell/Kconfig

@@ -14,7 +14,7 @@ config CPU_SPECIFIC_OPTIONS
 	select ARCH_VERSTAGE_X86_32
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CACHE_MRC_SETTINGS
-	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE
+	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
 	select COLLECT_TIMESTAMPS
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
@@ -22,8 +22,6 @@ config CPU_SPECIFIC_OPTIONS
 	select HAVE_SMI_HANDLER
 	select HAVE_HARD_RESET
 	select NO_FIXED_XIP_ROM_SIZE
-	select RELOCATABLE_MODULES
-	select RELOCATABLE_RAMSTAGE
 	select PARALLEL_MP
 	select PCIEXP_ASPM
 	select PCIEXP_CLK_PM
@@ -106,7 +104,6 @@ config DCACHE_RAM_SIZE
 config RESET_ON_INVALID_RAMSTAGE_CACHE
 	bool "Reset the system on S3 wake when ramstage cache invalid."
 	default n
-	depends on RELOCATABLE_RAMSTAGE
 	help
 	  The haswell romstage code caches the loaded ramstage program
 	  in SMM space. On S3 wake the romstage will copy over a fresh

src/soc/intel/broadwell/Kconfig

@@ -15,7 +15,7 @@ config CPU_SPECIFIC_OPTIONS
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CACHE_MRC_SETTINGS
 	select MRC_SETTINGS_PROTECT
-	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE
+	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select HAVE_MONOTONIC_TIMER
@@ -23,8 +23,6 @@ config CPU_SPECIFIC_OPTIONS
 	select HAVE_HARD_RESET
 	select HAVE_USBDEBUG
 	select IOAPIC
-	select RELOCATABLE_MODULES
-	select RELOCATABLE_RAMSTAGE
 	select REG_SCRIPT
 	select PARALLEL_MP
 	select RTC
@@ -159,7 +157,6 @@ config PRE_GRAPHICS_DELAY
 config RESET_ON_INVALID_RAMSTAGE_CACHE
 	bool "Reset the system on S3 wake when ramstage cache invalid."
 	default n
-	depends on RELOCATABLE_RAMSTAGE
 	help
 	  The romstage code caches the loaded ramstage program in SMM space.
 	  On S3 wake the romstage will copy over a fresh ramstage that was

src/soc/intel/cannonlake/Kconfig

@@ -17,7 +17,7 @@ config CPU_SPECIFIC_OPTIONS
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select C_ENVIRONMENT_BOOTBLOCK
 	select CACHE_MRC_SETTINGS
-	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE
+	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
 	select COMMON_FADT
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select GENERIC_GPIO_LIB
@@ -37,8 +37,6 @@ config CPU_SPECIFIC_OPTIONS
 	select POSTCAR_CONSOLE
 	select POSTCAR_STAGE
 	select REG_SCRIPT
-	select RELOCATABLE_MODULES
-	select RELOCATABLE_RAMSTAGE
 	select SMM_TSEG
 	select SMP
 	select SOC_AHCI_PORT_IMPLEMENTED_INVERT

src/soc/intel/denverton_ns/Kconfig

@@ -40,7 +40,6 @@ config CPU_SPECIFIC_OPTIONS
 	select HAVE_SMI_HANDLER
 	select SMM_TSEG
 	select CACHE_MRC_SETTINGS
-	select RELOCATABLE_RAMSTAGE     # Build fails if this is not selected
 	select PARALLEL_MP
 	select PCR_COMMON_IOSF_1_0
 	select SMP

src/soc/intel/quark/Kconfig

@@ -32,7 +32,6 @@ config CPU_SPECIFIC_OPTIONS
 	select HAVE_MONOTONIC_TIMER
 	select NO_MMCONF_SUPPORT
 	select REG_SCRIPT
-	select RELOCATABLE_RAMSTAGE
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_RESET
 	select SOC_SETS_MSRS

src/soc/intel/skylake/Kconfig

@@ -24,7 +24,7 @@ config CPU_SPECIFIC_OPTIONS
 	select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
 	select BOOT_DEVICE_SUPPORTS_WRITES
 	select CACHE_MRC_SETTINGS
-	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE
+	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
 	select COLLECT_TIMESTAMPS
 	select COMMON_FADT
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
@@ -47,8 +47,6 @@ config CPU_SPECIFIC_OPTIONS
 	select PCIEXP_L1_SUB_STATE
 	select PCIEX_LENGTH_64MB
 	select REG_SCRIPT
-	select RELOCATABLE_MODULES
-	select RELOCATABLE_RAMSTAGE
 	select RTC
 	select SA_ENABLE_DPR
 	select SMM_TSEG