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mb/google/skyrim/var/crystaldrift: Update the STT settings

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Adjust the STT settings.

BRANCH=none
BUG=b:270112575
TEST=emerge-skyrim coreboot chromeos-bootimage
Then the thermal team has verified.

Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I1df9bbf820b5a760007dcfd7bceb21063fc24696
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78523
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Yunlong Jia
2023-10-20 13:23:20 +00:00
committed by Felix Held
parent ad1eec9df6
commit 731e28a938
1 changed files with 13 additions and 4 deletions
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17
src/mainboard/google/skyrim/variants/crystaldrift/overridetree.cb
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@@ -22,10 +22,6 @@ end
chip soc/amd/mendocino chip soc/amd/mendocino
# Set Package Power Parameters
# Remove the sustained_power_limit_mW when STT is enabled
register "sustained_power_limit_mW" = "15000"
device domain 0 on device domain 0 on
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref xhci_1 on # XHCI1 controller device ref xhci_1 on # XHCI1 controller
@@ -131,4 +127,17 @@ chip soc/amd/mendocino
end end
end end
end # I2C2 end # I2C2
# Enable STT support
register "stt_control" = "1"
register "stt_pcb_sensor_count" = "2"
register "stt_min_limit" = "15000"
register "stt_m1" = "0x0555"
register "stt_m2" = "0xFDE4"
register "stt_c_apu" = "0x021A"
register "stt_alpha_apu" = "0x199A"
register "stt_skin_temp_apu" = "0x3000"
register "stt_error_coeff" = "0xA4"
register "stt_error_rate_coefficient" = "0x0E98"
end # chip soc/amd/mendocino end # chip soc/amd/mendocino