treewide: Replace CONFIG(ARCH_xx) tests

Once we support building stages for different architectures,
such CONFIG(ARCH_xx) tests do not evaluate correctly anymore.

Change-Id: I599995b3ed5c4dfd578c87067fe8bfc8c75b9d43
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42183
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/device/device.c

@@ -12,7 +12,7 @@
 #include <stdlib.h>
 #include <string.h>
 #include <smp/spinlock.h>
-#if CONFIG(ARCH_X86)
+#if ENV_X86
 #include <arch/ebda.h>
 #endif
 #include <timer.h>
@@ -566,7 +566,7 @@ void dev_initialize(void)
 
 	printk(BIOS_INFO, "Initializing devices...\n");
 
-#if CONFIG(ARCH_X86)
+#if ENV_X86
 	/* Ensure EBDA is prepared before Option ROMs. */
 	setup_default_ebda();
 #endif

src/device/oprom/include/io.h

@@ -3,7 +3,7 @@
 #ifndef __OPROM_IO_H__
 #define __OPROM_IO_H__
 
-#if CONFIG(ARCH_X86)
+#if ENV_X86
 #include <arch/io.h>
 #else
 void outb(u8 val, u16 port);

src/device/oprom/yabel/compat/functions.c

@@ -72,7 +72,7 @@ unsigned long tb_freq = 0;
 u64 get_time(void)
 {
 	u64 act = 0;
-#if CONFIG(ARCH_X86)
+#if ENV_X86
 	u32 eax, edx;
 
 	__asm__ __volatile__(

src/device/oprom/yabel/device.h

@@ -151,7 +151,7 @@ u8 biosemu_dev_translate_address(int type, unsigned long * addr);
 static inline void
 out32le(void *addr, u32 val)
 {
-#if CONFIG(ARCH_X86) || CONFIG(ARCH_ARM)
+#if ENV_X86 || ENV_ARM || ENV_ARM64
 	*((u32*) addr) = cpu_to_le32(val);
 #else
 	asm volatile ("stwbrx  %0, 0, %1"::"r" (val), "r"(addr));
@@ -162,7 +162,7 @@ static inline u32
 in32le(void *addr)
 {
 	u32 val;
-#if CONFIG(ARCH_X86) || CONFIG(ARCH_ARM)
+#if ENV_X86 || ENV_ARM || ENV_ARM64
 	val = cpu_to_le32(*((u32 *) addr));
 #else
 	asm volatile ("lwbrx  %0, 0, %1":"=r" (val):"r"(addr));
@@ -173,7 +173,7 @@ in32le(void *addr)
 static inline void
 out16le(void *addr, u16 val)
 {
-#if CONFIG(ARCH_X86) || CONFIG(ARCH_ARM)
+#if ENV_X86 || ENV_ARM || ENV_ARM64
 	*((u16*) addr) = cpu_to_le16(val);
 #else
 	asm volatile ("sthbrx  %0, 0, %1"::"r" (val), "r"(addr));
@@ -184,7 +184,7 @@ static inline u16
 in16le(void *addr)
 {
 	u16 val;
-#if CONFIG(ARCH_X86) || CONFIG(ARCH_ARM)
+#if ENV_X86 || ENV_ARM || ENV_ARM64
 	val = cpu_to_le16(*((u16*) addr));
 #else
 	asm volatile ("lhbrx %0, 0, %1":"=r" (val):"r"(addr));

src/drivers/elog/elog.c

@@ -748,7 +748,7 @@ static bool elog_do_add_boot_count(void)
 /* Check and log POST codes from previous boot */
 static void log_last_boot_post(void)
 {
-#if CONFIG(ARCH_X86)
+#if ENV_X86
 	u8 code;
 	u32 extra;
 

src/include/cbmem.h

@@ -145,7 +145,7 @@ void cbmem_add_records_to_cbtable(struct lb_header *header);
  * and CBMEM_CONSOLE. Sometimes it is necessary to have cbmem_top()
  * value stored in nvram to enable early recovery on S3 path.
  */
-#if CONFIG(ARCH_X86)
+#if ENV_X86
 void backup_top_of_low_cacheable(uintptr_t ramtop);
 uintptr_t restore_top_of_low_cacheable(void);
 #endif

src/include/rules.h

@@ -247,7 +247,7 @@
 	(ENV_DECOMPRESSOR || ENV_BOOTBLOCK || ENV_ROMSTAGE || \
 	(ENV_SEPARATE_VERSTAGE && !CONFIG(VBOOT_STARTS_IN_ROMSTAGE)))
 
-#if CONFIG(ARCH_X86)
+#if ENV_X86
 /* Indicates memory layout is determined with arch/x86/car.ld. */
 #define ENV_CACHE_AS_RAM		(ENV_ROMSTAGE_OR_BEFORE && !CONFIG(RESET_VECTOR_IN_RAM))
 /* No .data sections with execute-in-place from ROM.  */

src/include/symbols.h

@@ -63,7 +63,7 @@ DECLARE_REGION(bl31)
  * (Does not necessarily mean that the memory is accessible.) */
 static inline int preram_symbols_available(void)
 {
-	return !CONFIG(ARCH_X86) || ENV_ROMSTAGE_OR_BEFORE;
+	return !ENV_X86 || ENV_ROMSTAGE_OR_BEFORE;
 }
 
 #endif /* __SYMBOLS_H */

src/lib/edid.c

@@ -501,7 +501,7 @@ detailed_block(struct edid *result_edid, unsigned char *x, int in_extension,
 	 * another call to edid_set_framebuffer_bits_per_pixel(). As a cheap
 	 * heuristic, assume that X86 systems require a 64-byte row alignment
 	 * (since that seems to be true for most Intel chipsets). */
-	if (CONFIG(ARCH_X86))
+	if (ENV_X86)
 		edid_set_framebuffer_bits_per_pixel(out, 32, 64);
 	else
 		edid_set_framebuffer_bits_per_pixel(out, 32, 0);

src/lib/hardwaremain.c

@@ -425,7 +425,7 @@ void main(void)
 
 	/* TODO: Understand why this is here and move to arch/platform code. */
 	/* For MMIO UART this needs to be called before any other printk. */
-	if (CONFIG(ARCH_X86))
+	if (ENV_X86)
 		init_timer();
 
 	/* console_init() MUST PRECEDE ALL printk()! Additionally, ensure

src/lib/libgcc.c

@@ -7,8 +7,13 @@
  * <lib.h> in case GCC does not have an assembly version for this arch.
  */
 
-#if !CONFIG(ARCH_X86)	       /* work around lack of --gc-sections on x86 */ \
+/*
-	&& !CONFIG(ARCH_RISCV_RV32) /* defined in rv32 libgcc.a */
+ * FIXME
+ * work around lack of --gc-sections on x86
+ * defined in rv32 libgcc.a
+ */
+
+#if !ENV_X86 && !ENV_RISCV
 int __clzsi2(u32 a);
 int __clzsi2(u32 a)
 {

src/lib/prog_loaders.c

@@ -46,7 +46,7 @@ void run_romstage(void)
 
 	vboot_run_logic();
 
-	if (CONFIG(ARCH_X86) && CONFIG(BOOTBLOCK_NORMAL)) {
+	if (ENV_X86 && CONFIG(BOOTBLOCK_NORMAL)) {
 		if (legacy_romstage_selector(&romstage))
 			goto fail;
 	} else {
@@ -119,8 +119,7 @@ void run_ramstage(void)
 	 * Only x86 systems using ramstage stage cache currently take the same
 	 * firmware path on resume.
 	 */
-	if (CONFIG(ARCH_X86) &&
+	if (ENV_X86 && !CONFIG(NO_STAGE_CACHE))
-	    !CONFIG(NO_STAGE_CACHE))
 		run_ramstage_from_resume(&ramstage);
 
 	vboot_run_logic();

src/lib/ramtest.c

@@ -3,7 +3,7 @@
 #include <console/console.h>
 #include <device/mmio.h>
 
-#if CONFIG(ARCH_X86) && CONFIG(SSE2)
+#if ENV_X86 && CONFIG(SSE2)
 /* Assembler in lib/ is ugly. */
 static void write_phys(uintptr_t addr, u32 value)
 {

src/lib/reg_script.c

@@ -11,7 +11,7 @@
 #include <stdint.h>
 #include <reg_script.h>
 
-#if CONFIG(ARCH_X86)
+#if ENV_X86
 #include <cpu/x86/msr.h>
 #endif
 
@@ -363,7 +363,7 @@ static void reg_script_write_iosf(struct reg_script_context *ctx)
 
 static uint64_t reg_script_read_msr(struct reg_script_context *ctx)
 {
-#if CONFIG(ARCH_X86)
+#if ENV_X86
 	const struct reg_script *step = reg_script_get_step(ctx);
 	msr_t msr = rdmsr(step->reg);
 	uint64_t value = msr.hi;
@@ -375,7 +375,7 @@ static uint64_t reg_script_read_msr(struct reg_script_context *ctx)
 
 static void reg_script_write_msr(struct reg_script_context *ctx)
 {
-#if CONFIG(ARCH_X86)
+#if ENV_X86
 	const struct reg_script *step = reg_script_get_step(ctx);
 	msr_t msr;
 	msr.hi = step->value >> 32;

src/lib/timestamp.c

@@ -71,7 +71,7 @@ static int timestamp_should_run(void)
 	 * Only check boot_cpu() in other stages than
 	 * ENV_PAYLOAD_LOADER on x86.
 	 */
-	if ((!ENV_PAYLOAD_LOADER && CONFIG(ARCH_X86)) && !boot_cpu())
+	if ((!ENV_PAYLOAD_LOADER && ENV_X86) && !boot_cpu())
 		return 0;
 
 	return 1;

src/security/memory/memory_clear.c

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#if CONFIG(ARCH_X86)
+#if ENV_X86
 #include <cpu/x86/pae.h>
 #else
 #define memset_pae(a, b, c, d, e) 0
@@ -83,7 +83,7 @@ static void clear_memory(void *unused)
 	cbmem_get_region(&baseptr, &size);
 	memranges_insert(&mem, (uintptr_t)baseptr, size, BM_MEM_TABLE);
 
-	if (CONFIG(ARCH_X86)) {
+	if (ENV_X86) {
 		/* Find space for PAE enabled memset */
 		pgtbl = get_free_memory_range(&mem, MEMSET_PAE_PGTL_ALIGN,
 					MEMSET_PAE_PGTL_SIZE);
@@ -114,7 +114,7 @@ static void clear_memory(void *unused)
 			       range_entry_size(r));
 		}
 		/* Use PAE if available */
-		else if (CONFIG(ARCH_X86)) {
+		else if (ENV_X86) {
 			if (memset_pae(range_entry_base(r), 0,
 			    range_entry_size(r), (void *)pgtbl,
 			    (void *)vmem_addr))
@@ -126,7 +126,7 @@ static void clear_memory(void *unused)
 		}
 	}
 
-	if (CONFIG(ARCH_X86)) {
+	if (ENV_X86) {
 		/* Clear previously skipped memory reserved for pagetables */
 		printk(BIOS_DEBUG, "%s: Clearing DRAM %016lx-%016lx\n",
 		__func__, pgtbl, pgtbl + MEMSET_PAE_PGTL_SIZE);