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soc/intel/cnl: drop lpit.asl in favor of common version

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Drop lpit.asl from CNL and switch to the common one in the three boards
currently using it.

The only difference between the two is the usage on macros in common
code instead of plain integer values.

Change-Id: Iefbd18db7f4c560dce16c4119fde4f4cfbeafb84
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Michael Niewöhner
2020-09-19 11:49:05 +02:00
parent c8e309779f
commit 733c462c13
4 changed files with 3 additions and 101 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/drallion/dsdt.asl
View File

@@ -40,7 +40,7 @@ DefinitionBlock(
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Low power idle table */ /* Low power idle table */
#include <soc/intel/cannonlake/acpi/lpit.asl> #include <soc/intel/common/acpi/lpit.asl>
/* Chrome OS Embedded Controller */ /* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB) Scope (\_SB.PCI0.LPCB)

2
src/mainboard/google/hatch/dsdt.asl
View File

@@ -37,7 +37,7 @@ DefinitionBlock(
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Low power idle table */ /* Low power idle table */
#include <soc/intel/cannonlake/acpi/lpit.asl> #include <soc/intel/common/acpi/lpit.asl>
/* Chrome OS Embedded Controller */ /* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB) Scope (\_SB.PCI0.LPCB)

2
src/mainboard/google/sarien/dsdt.asl
View File

@@ -40,7 +40,7 @@ DefinitionBlock(
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Low power idle table */ /* Low power idle table */
#include <soc/intel/cannonlake/acpi/lpit.asl> #include <soc/intel/common/acpi/lpit.asl>
#if CONFIG(EC_GOOGLE_WILCO) #if CONFIG(EC_GOOGLE_WILCO)
/* Chrome OS Embedded Controller */ /* Chrome OS Embedded Controller */

98
src/soc/intel/cannonlake/acpi/lpit.asl
View File

@@ -1,98 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
External(\_SB.MS0X, MethodObj)
External(\_SB.PCI0.LPCB.EC0.S0IX, MethodObj)
External(\_SB.PCI0.EGPM, MethodObj)
External(\_SB.PCI0.RGPM, MethodObj)
scope(\_SB)
{
Device(LPID) {
Name(_ADR, 0x00000000)
Name(_CID, EISAID("PNP0D80"))
Name(UUID,
ToUUID("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66"))
Method(_DSM, 4) {
If(Arg0 == ^UUID) {
/*
* Enum functions
*/
If(Arg2 == Zero) {
Return(Buffer(One) {
0x60}
)
}
/*
* Function 1 - Get Device Constraints
*/
If(Arg2 == 1) {
Return(Package(5) {
0, Ones, Ones, Ones, Ones}
)
}
/*
* Function 2 - Get Crash Dump Device
*/
If(Arg2 == 2) {
Return(Buffer(One) {
0x0}
)
}
/*
* Function 3 - Display Off Notification
*/
If(Arg2 == 3) {
}
/*
* Function 4 - Display On Notification
*/
If(Arg2 == 4) {
}
/*
* Function 5 - Low Power S0 Entry Notification
*/
If(Arg2 == 5) {
/* Inform the EC */
If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) {
\_SB.PCI0.LPCB.EC0.S0IX(1)
}
/* provide board level s0ix hook */
If (CondRefOf (\_SB.MS0X)) {
\_SB.MS0X(1)
}
/*
* Save the current PM bits then
* enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG
*/
If (CondRefOf (\_SB.PCI0.EGPM))
{
\_SB.PCI0.EGPM ()
}
}
/*
* Function 6 - Low Power S0 Exit Notification
*/
If(Arg2 == 6) {
/* Inform the EC */
If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) {
\_SB.PCI0.LPCB.EC0.S0IX(0)
}
/* provide board level s0ix hook */
If (CondRefOf (\_SB.MS0X)) {
\_SB.MS0X(0)
}
/* Restore GPIO all Community PM */
If (CondRefOf (\_SB.PCI0.RGPM))
{
\_SB.PCI0.RGPM ()
}
}
}
Return(Buffer(One) {0x00})
} // Method(_DSM)
} // device (LPID)
} // End Scope(\_SB)