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sb/intel/common: Add smbus_set_slave_addr()

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Change-Id: I7dddb61fab00e0f4f67d4eebee0cfe8dcd99f4ab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38230
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2020-01-06 19:00:31 +02:00
parent 7cdcc38f29
commit 73451fdea2
17 changed files with 14 additions and 33 deletions
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2
src/include/device/smbus_host.h
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@ -35,6 +35,6 @@ int do_i2c_block_write(uintptr_t base, u8 device, size_t bytes, u8 *buf);
/* Upstream API */ /* Upstream API */
void smbus_host_reset(uintptr_t base); void smbus_host_reset(uintptr_t base);
void smbus_set_slave_addr(uintptr_t base, u8 slave_address);
#endif #endif

1
src/soc/intel/broadwell/include/soc/smbus.h
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@ -22,7 +22,6 @@
#define SMB_BASE 0x20 #define SMB_BASE 0x20
#define HOSTC 0x40 #define HOSTC 0x40
#define HST_EN (1 << 0) #define HST_EN (1 << 0)
#define SMB_RCV_SLVA 0x09
/* SMBus I/O bits. */ /* SMBus I/O bits. */
#define SMBHSTSTAT 0x0 #define SMBHSTSTAT 0x0

3
src/soc/intel/broadwell/smbus.c
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@ -24,7 +24,6 @@
#include <soc/iomap.h> #include <soc/iomap.h>
#include <soc/ramstage.h> #include <soc/ramstage.h>
#include <soc/smbus.h> #include <soc/smbus.h>
#include <southbridge/intel/common/smbus.h>
#include <device/smbus_host.h> #include <device/smbus_host.h>
static void pch_smbus_init(struct device *dev) static void pch_smbus_init(struct device *dev)
@ -40,7 +39,7 @@ static void pch_smbus_init(struct device *dev)
/* Set Receive Slave Address */ /* Set Receive Slave Address */
res = find_resource(dev, PCI_BASE_ADDRESS_4); res = find_resource(dev, PCI_BASE_ADDRESS_4);
if (res) if (res)
outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA); smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR);
} }
static int lsmbus_read_byte(struct device *dev, u8 address) static int lsmbus_read_byte(struct device *dev, u8 address)

4
src/soc/intel/cannonlake/include/soc/smbus.h
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@ -19,10 +19,6 @@
#ifndef _SOC_CANNONLAKE_SMBUS_H_ #ifndef _SOC_CANNONLAKE_SMBUS_H_
#define _SOC_CANNONLAKE_SMBUS_H_ #define _SOC_CANNONLAKE_SMBUS_H_
/* IO and MMIO registers under primary BAR */
/* Set address for PCH as SMBus slave role */
#define SMB_RCV_SLVA 0x09
/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ /* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
#define TCO1_STS 0x04 #define TCO1_STS 0x04
#define TCO_TIMEOUT (1 << 3) #define TCO_TIMEOUT (1 << 3)

4
src/soc/intel/common/block/smbus/smbus.c
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@ -13,14 +13,12 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <arch/io.h>
#include <device/device.h> #include <device/device.h>
#include <device/path.h> #include <device/path.h>
#include <device/smbus.h> #include <device/smbus.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <soc/smbus.h> #include <soc/smbus.h>
#include <southbridge/intel/common/smbus.h>
#include <device/smbus_host.h> #include <device/smbus_host.h>
#include "smbuslib.h" #include "smbuslib.h"
@ -63,7 +61,7 @@ static void pch_smbus_init(struct device *dev)
/* Set Receive Slave Address */ /* Set Receive Slave Address */
res = find_resource(dev, PCI_BASE_ADDRESS_4); res = find_resource(dev, PCI_BASE_ADDRESS_4);
if (res) if (res)
outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA); smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR);
} }
static void smbus_read_resources(struct device *dev) static void smbus_read_resources(struct device *dev)

2
src/soc/intel/denverton_ns/include/soc/smbus.h
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@ -25,7 +25,7 @@
#define HST_EN (1 << 0) #define HST_EN (1 << 0)
#define HOSTC_SMI_EN (1 << 1) #define HOSTC_SMI_EN (1 << 1)
#define HOSTC_I2C_EN (1 << 2) #define HOSTC_I2C_EN (1 << 2)
#define SMB_RCV_SLVA 0x09
/* SMBUS TCO base address. */ /* SMBUS TCO base address. */
#define TCOBASE 0x50 #define TCOBASE 0x50
#define MASK_TCOBASE 0xffe0 #define MASK_TCOBASE 0xffe0

4
src/soc/intel/icelake/include/soc/smbus.h
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@ -16,10 +16,6 @@
#ifndef _SOC_ICELAKE_SMBUS_H_ #ifndef _SOC_ICELAKE_SMBUS_H_
#define _SOC_ICELAKE_SMBUS_H_ #define _SOC_ICELAKE_SMBUS_H_
/* IO and MMIO registers under primary BAR */
/* Set address for PCH as SMBus slave role */
#define SMB_RCV_SLVA 0x09
/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ /* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
#define TCO1_STS 0x04 #define TCO1_STS 0x04
#define TCO_TIMEOUT (1 << 3) #define TCO_TIMEOUT (1 << 3)

3
src/soc/intel/skylake/include/soc/smbus.h
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@ -19,9 +19,6 @@
#ifndef _SOC_SMBUS_H_ #ifndef _SOC_SMBUS_H_
#define _SOC_SMBUS_H_ #define _SOC_SMBUS_H_
/* PCI Configuration Space (D31:F3): SMBus */
#define SMB_RCV_SLVA 0x09
/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ /* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
#define TCO1_STS 0x04 #define TCO1_STS 0x04
#define TCO_TIMEOUT (1 << 3) #define TCO_TIMEOUT (1 << 3)

2
src/soc/intel/tigerlake/include/soc/smbus.h
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@ -23,8 +23,6 @@
#define _SOC_TIGERLAKE_SMBUS_H_ #define _SOC_TIGERLAKE_SMBUS_H_
/* IO and MMIO registers under primary BAR */ /* IO and MMIO registers under primary BAR */
/* Set address for PCH as SMBus slave role */
#define SMB_RCV_SLVA 0x09
/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ /* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
#define TCO1_STS 0x04 #define TCO1_STS 0x04

1
src/southbridge/intel/bd82x6x/pch.h
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@ -238,7 +238,6 @@ void early_usb_init(const struct southbridge_usb_port *portmap);
#define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3) #define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3)
#define SMB_BASE 0x20 #define SMB_BASE 0x20
#define HOSTC 0x40 #define HOSTC 0x40
#define SMB_RCV_SLVA 0x09
/* HOSTC bits */ /* HOSTC bits */
#define I2C_EN (1 << 2) #define I2C_EN (1 << 2)

4
src/southbridge/intel/bd82x6x/smbus.c
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@ -20,8 +20,6 @@
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <arch/io.h>
#include <southbridge/intel/common/smbus.h>
#include <device/smbus_host.h> #include <device/smbus_host.h>
#include "pch.h" #include "pch.h"
@ -38,7 +36,7 @@ static void pch_smbus_init(struct device *dev)
/* Set Receive Slave Address */ /* Set Receive Slave Address */
res = find_resource(dev, PCI_BASE_ADDRESS_4); res = find_resource(dev, PCI_BASE_ADDRESS_4);
if (res) if (res)
outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA); smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR);
} }
static int lsmbus_read_byte(struct device *dev, u8 address) static int lsmbus_read_byte(struct device *dev, u8 address)

5
src/southbridge/intel/common/smbus.c
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@ -101,6 +101,11 @@ void smbus_host_reset(uintptr_t base)
host_and_or(base, SMBHSTSTAT, 0xff, 0); host_and_or(base, SMBHSTSTAT, 0xff, 0);
} }
void smbus_set_slave_addr(uintptr_t base, u8 slave_address)
{
host_outb(base, SMB_RCV_SLVA, slave_address);
}
static int host_completed(u8 status) static int host_completed(u8 status)
{ {
if (status & SMBHSTSTS_HOST_BUSY) if (status & SMBHSTSTS_HOST_BUSY)

2
src/southbridge/intel/common/smbus.h
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@ -32,4 +32,6 @@
#define SMBUS_PIN_CTL 0xf #define SMBUS_PIN_CTL 0xf
#define SMBSLVCMD 0x11 #define SMBSLVCMD 0x11
#define SMB_RCV_SLVA SMBTRNSADD
#endif #endif

1
src/southbridge/intel/ibexpeak/pch.h
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@ -232,7 +232,6 @@ void pch_enable(struct device *dev);
#define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3) #define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3)
#define SMB_BASE 0x20 #define SMB_BASE 0x20
#define HOSTC 0x40 #define HOSTC 0x40
#define SMB_RCV_SLVA 0x09
/* HOSTC bits */ /* HOSTC bits */
#define I2C_EN (1 << 2) #define I2C_EN (1 << 2)

4
src/southbridge/intel/ibexpeak/smbus.c
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@ -20,8 +20,6 @@
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <arch/io.h>
#include <southbridge/intel/common/smbus.h>
#include <device/smbus_host.h> #include <device/smbus_host.h>
#include "pch.h" #include "pch.h"
@ -38,7 +36,7 @@ static void pch_smbus_init(struct device *dev)
/* Set Receive Slave Address */ /* Set Receive Slave Address */
res = find_resource(dev, PCI_BASE_ADDRESS_4); res = find_resource(dev, PCI_BASE_ADDRESS_4);
if (res) if (res)
outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA); smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR);
} }
static int lsmbus_read_byte(struct device *dev, u8 address) static int lsmbus_read_byte(struct device *dev, u8 address)

1
src/southbridge/intel/lynxpoint/pch.h
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@ -440,7 +440,6 @@ void mainboard_config_superio(void);
#define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3) #define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3)
#define SMB_BASE 0x20 #define SMB_BASE 0x20
#define HOSTC 0x40 #define HOSTC 0x40
#define SMB_RCV_SLVA 0x09
/* HOSTC bits */ /* HOSTC bits */
#define I2C_EN (1 << 2) #define I2C_EN (1 << 2)

4
src/southbridge/intel/lynxpoint/smbus.c
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@ -20,8 +20,6 @@
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <arch/io.h>
#include <southbridge/intel/common/smbus.h>
#include <device/smbus_host.h> #include <device/smbus_host.h>
#include "pch.h" #include "pch.h"
@ -38,7 +36,7 @@ static void pch_smbus_init(struct device *dev)
/* Set Receive Slave Address */ /* Set Receive Slave Address */
res = find_resource(dev, PCI_BASE_ADDRESS_4); res = find_resource(dev, PCI_BASE_ADDRESS_4);
if (res) if (res)
outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA); smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR);
} }
static int lsmbus_read_byte(struct device *dev, u8 address) static int lsmbus_read_byte(struct device *dev, u8 address)