rk3288: update romstage & mainboard

BUG=chrome-os-partner:29778
TEST=Build coreboot

Change-Id: I877b4bf741f45f6cfd032ad5018a60e8a1453622
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 640da5ad5597803c62d9374a1a48832003077723
Original-Change-Id: I805d93e94f73418099f47d235ca920a91b4b2bfb
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209469
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8867
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/soc/rockchip/rk3288/Makefile.inc

@@ -21,14 +21,14 @@ IDBTOOL = util/rockchip/make_idb.py
 
 #bootblock-y += bootblock.c
 bootblock-y += cbmem.c
-bootblock-y += timer.c
-bootblock-y += monotonic_timer.c
-bootblock-y += media.c
 ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
 bootblock-$(CONFIG_DRIVERS_UART) += uart.c
 endif
+bootblock-y += timer.c
+bootblock-y += monotonic_timer.c
 bootblock-y += clock.c
 bootblock-y += spi.c
+bootblock-y += media.c
 
 romstage-y += cbmem.c
 romstage-y += timer.c

src/soc/rockchip/rk3288/cbmem.c

@@ -19,11 +19,9 @@
 
 #include <stddef.h>
 #include <cbmem.h>
-
-#define FB_SIZE_MB	4
+#include "soc.h"
 void *cbmem_top(void)
 {
-	return (void *)(CONFIG_SYS_SDRAM_BASE +
-			(CONFIG_DRAM_SIZE_MB - FB_SIZE_MB)*MiB);
+	return (void *)(get_fb_base_kb()*KiB);
 }
 

src/soc/rockchip/rk3288/clock.c

@@ -339,3 +339,34 @@ void rkclk_configure_spi(unsigned int bus, unsigned int hz)
 		printk(BIOS_ERR, "do not support this spi bus\n");
 	}
 }
+
+static u32 clk_gcd(u32 a, u32 b)
+{
+	while (b != 0) {
+		int r = b;
+		b = a % b;
+		a = r;
+	}
+	return a;
+}
+
+void rkclk_configure_i2s(unsigned int hz)
+{
+	int n, d;
+	int v;
+
+	/* i2s source clock: gpll
+	   i2s0_outclk_sel: clk_i2s
+	   i2s0_clk_sel: divider ouput from fraction
+	   i2s0_pll_div_con: 0*/
+	writel(RK_CLRSETBITS(1 << 15 | 1 << 12 | 3 << 8 | 0x7f << 0 ,
+			     1 << 15 | 0 << 12 | 1 << 8 | 0 << 0),
+			     &cru_ptr->cru_clksel_con[4]);
+
+	/* set frac divider */
+	v = clk_gcd(GPLL_HZ, hz);
+	n = (GPLL_HZ / v) & (0xffff);
+	d = (hz / v) & (0xffff);
+	assert(hz == GPLL_HZ / n * d);
+	writel(d << 16 | n, &cru_ptr->cru_clksel_con[8]);
+}

src/soc/rockchip/rk3288/clock.h

@@ -31,5 +31,6 @@ void rkclk_configure_spi(unsigned int bus, unsigned int hz);
 void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy);
 void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n);
 void rkclk_configure_ddr(unsigned int hz);
+void rkclk_configure_i2s(unsigned int hz);
 
 #endif	/* __SOC_ROCKCHIP_RK3288_CLOCK_H__ */

src/soc/rockchip/rk3288/timer.h

@@ -17,8 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#ifndef __ROCKCHIP_RK3288_TIMER_H__
-#define __ROCKCHIP_RK3288_TIMER_H__
+#ifndef __SOC_ROCKCHIP_RK3288_TIMER_H__
+#define __SOC_ROCKCHIP_RK3288_TIMER_H__
 
 #include "addressmap.h"
 
@@ -40,4 +40,4 @@ static struct rk3288_timer * const timer7_ptr = (void *)TIMER7_BASE;
 
 void rk3288_init_timer(void);
 
-#endif	/* __ROCKCHIP_RK3288_TIMER_H__ */
+#endif	/* __SOC_ROCKCHIP_RK3288_TIMER_H__ */