Add Intel FSP bd82x6x southbridge support
Add support for the bd82x6x using the Intel FSP. The FSP is different enough to warrant its own source files for now. The mrc/system agent chromebook solution does much more southbridge initialization and configuration than the FSP version. It may be combined in the future. Change-Id: Ie493945f3d321d854728d231979a0c172d2b36de Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4017 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Marc Jones
660
src/southbridge/intel/fsp_bd82x6x/lpc.c
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660
src/southbridge/intel/fsp_bd82x6x/lpc.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2013 Sage Electronic Engineering, LLC.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <pc80/mc146818rtc.h>
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#include <pc80/isa-dma.h>
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#include <pc80/i8259.h>
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#include <arch/io.h>
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#include <arch/ioapic.h>
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#include <arch/acpi.h>
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#include <cpu/cpu.h>
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#include <elog.h>
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#include "pch.h"
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#define NMI_OFF 0
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#define ENABLE_ACPI_MODE_IN_COREBOOT 0
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#define TEST_SMM_FLASH_LOCKDOWN 0
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typedef struct southbridge_intel_fsp_bd82x6x_config config_t;
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static void pch_enable_apic(struct device *dev)
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{
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int i;
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u32 reg32;
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volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
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volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
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/* Enable ACPI I/O and power management.
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* Set SCI IRQ to IRQ9
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*/
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pci_write_config8(dev, ACPI_CNTL, 0x80);
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*ioapic_index = 0;
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*ioapic_data = (1 << 25);
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/* affirm full set of redirection table entries ("write once") */
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*ioapic_index = 1;
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reg32 = *ioapic_data;
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*ioapic_index = 1;
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*ioapic_data = reg32;
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*ioapic_index = 0;
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reg32 = *ioapic_data;
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printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
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if (reg32 != (1 << 25))
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die("APIC Error\n");
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printk(BIOS_SPEW, "Dumping IOAPIC registers\n");
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for (i=0; i<3; i++) {
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*ioapic_index = i;
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printk(BIOS_SPEW, " reg 0x%04x:", i);
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reg32 = *ioapic_data;
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printk(BIOS_SPEW, " 0x%08x\n", reg32);
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}
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*ioapic_index = 3; /* Select Boot Configuration register. */
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*ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
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}
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static void pch_enable_serial_irqs(struct device *dev)
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{
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/* Set packet length and toggle silent mode bit for one frame. */
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pci_write_config8(dev, SERIRQ_CNTL,
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(1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
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#if !CONFIG_SERIRQ_CONTINUOUS_MODE
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pci_write_config8(dev, SERIRQ_CNTL,
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(1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
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#endif
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}
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/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
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* 0x00 - 0000 = Reserved
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* 0x01 - 0001 = Reserved
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* 0x02 - 0010 = Reserved
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* 0x03 - 0011 = IRQ3
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* 0x04 - 0100 = IRQ4
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* 0x05 - 0101 = IRQ5
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* 0x06 - 0110 = IRQ6
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* 0x07 - 0111 = IRQ7
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* 0x08 - 1000 = Reserved
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* 0x09 - 1001 = IRQ9
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* 0x0A - 1010 = IRQ10
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* 0x0B - 1011 = IRQ11
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* 0x0C - 1100 = IRQ12
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* 0x0D - 1101 = Reserved
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* 0x0E - 1110 = IRQ14
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* 0x0F - 1111 = IRQ15
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* PIRQ[n]_ROUT[7] - PIRQ Routing Control
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* 0x80 - The PIRQ is not routed.
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*/
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static void pch_pirq_init(device_t dev)
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{
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device_t irq_dev;
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
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pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
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pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
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pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
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pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
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pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
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pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
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pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
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/* Eric Biederman once said we should let the OS do this.
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* I am not so sure anymore he was right.
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*/
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for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
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u8 int_pin=0, int_line=0;
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if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
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continue;
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int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
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switch (int_pin) {
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case 1: /* INTA# */ int_line = config->pirqa_routing; break;
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case 2: /* INTB# */ int_line = config->pirqb_routing; break;
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case 3: /* INTC# */ int_line = config->pirqc_routing; break;
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case 4: /* INTD# */ int_line = config->pirqd_routing; break;
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}
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if (!int_line)
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continue;
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pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
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}
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}
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static void pch_gpi_routing(device_t dev)
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{
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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u32 reg32 = 0;
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/* An array would be much nicer here, or some
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* other method of doing this.
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*/
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reg32 |= (config->gpi0_routing & 0x03) << 0;
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reg32 |= (config->gpi1_routing & 0x03) << 2;
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reg32 |= (config->gpi2_routing & 0x03) << 4;
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reg32 |= (config->gpi3_routing & 0x03) << 6;
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reg32 |= (config->gpi4_routing & 0x03) << 8;
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reg32 |= (config->gpi5_routing & 0x03) << 10;
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reg32 |= (config->gpi6_routing & 0x03) << 12;
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reg32 |= (config->gpi7_routing & 0x03) << 14;
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reg32 |= (config->gpi8_routing & 0x03) << 16;
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reg32 |= (config->gpi9_routing & 0x03) << 18;
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reg32 |= (config->gpi10_routing & 0x03) << 20;
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reg32 |= (config->gpi11_routing & 0x03) << 22;
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reg32 |= (config->gpi12_routing & 0x03) << 24;
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reg32 |= (config->gpi13_routing & 0x03) << 26;
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reg32 |= (config->gpi14_routing & 0x03) << 28;
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reg32 |= (config->gpi15_routing & 0x03) << 30;
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pci_write_config32(dev, 0xb8, reg32);
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}
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static void pch_power_options(device_t dev)
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{
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u8 reg8;
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u16 reg16, pmbase;
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u32 reg32;
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const char *state;
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
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int nmi_option;
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/* Which state do we want to goto after g3 (power restored)?
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* 0 == S0 Full On
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* 1 == S5 Soft Off
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*
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* If the option is not existent (Laptops), use Kconfig setting.
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*/
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get_option(&pwr_on, "power_on_after_fail");
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reg16 = pci_read_config16(dev, GEN_PMCON_3);
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reg16 &= 0xfffe;
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switch (pwr_on) {
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case MAINBOARD_POWER_OFF:
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reg16 |= 1;
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state = "off";
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break;
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case MAINBOARD_POWER_ON:
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reg16 &= ~1;
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state = "on";
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break;
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case MAINBOARD_POWER_KEEP:
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reg16 &= ~1;
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state = "state keep";
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break;
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default:
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state = "undefined";
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}
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reg16 &= ~(3 << 4); /* SLP_S4# Assertion Stretch 4s */
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reg16 |= (1 << 3); /* SLP_S4# Assertion Stretch Enable */
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reg16 &= ~(1 << 10);
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reg16 |= (1 << 11); /* SLP_S3# Min Assertion Width 50ms */
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reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
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pci_write_config16(dev, GEN_PMCON_3, reg16);
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printk(BIOS_INFO, "Set power %s after power failure.\n", state);
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/* Set up NMI on errors. */
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reg8 = inb(0x61);
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reg8 &= 0x0f; /* Higher Nibble must be 0 */
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reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
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// reg8 &= ~(1 << 2); /* PCI SERR# Enable */
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reg8 |= (1 << 2); /* PCI SERR# Disable for now */
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outb(reg8, 0x61);
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reg8 = inb(0x70);
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nmi_option = NMI_OFF;
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get_option(&nmi_option, "nmi");
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if (nmi_option) {
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printk(BIOS_INFO, "NMI sources enabled.\n");
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reg8 &= ~(1 << 7); /* Set NMI. */
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} else {
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printk(BIOS_INFO, "NMI sources disabled.\n");
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reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
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}
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outb(reg8, 0x70);
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/* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
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reg16 = pci_read_config16(dev, GEN_PMCON_1);
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reg16 &= ~(3 << 0); // SMI# rate 1 minute
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reg16 &= ~(1 << 10); // Disable BIOS_PCI_EXP_EN for native PME
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#if DEBUG_PERIODIC_SMIS
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/* Set DEBUG_PERIODIC_SMIS in pch.h to debug using
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* periodic SMIs.
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*/
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reg16 |= (3 << 0); // Periodic SMI every 8s
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#endif
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pci_write_config16(dev, GEN_PMCON_1, reg16);
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// Set the board's GPI routing.
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pch_gpi_routing(dev);
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pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
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outl(config->gpe0_en, pmbase + GPE0_EN);
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outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN);
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/* Set up power management block and determine sleep mode */
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reg32 = inl(pmbase + 0x04); // PM1_CNT
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reg32 &= ~(7 << 10); // SLP_TYP
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reg32 |= (1 << 0); // SCI_EN
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outl(reg32, pmbase + 0x04);
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/* Clear magic status bits to prevent unexpected wake */
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reg32 = RCBA32(0x3310);
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reg32 |= (1 << 4)|(1 << 5)|(1 << 0);
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RCBA32(0x3310) = reg32;
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}
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static void pch_rtc_init(struct device *dev)
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{
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u8 reg8;
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int rtc_failed;
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reg8 = pci_read_config8(dev, GEN_PMCON_3);
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rtc_failed = reg8 & RTC_BATTERY_DEAD;
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if (rtc_failed) {
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reg8 &= ~RTC_BATTERY_DEAD;
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pci_write_config8(dev, GEN_PMCON_3, reg8);
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#if CONFIG_ELOG
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elog_add_event(ELOG_TYPE_RTC_RESET);
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#endif
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}
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printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
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rtc_init(rtc_failed);
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}
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/* CougarPoint PCH Power Management init */
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static void cpt_pm_init(struct device *dev)
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{
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printk(BIOS_DEBUG, "CougarPoint PM init\n");
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pci_write_config8(dev, 0xa9, 0x47);
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RCBA32_AND_OR(0x2238, ~0UL, (1 << 6)|(1 << 0));
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RCBA32_AND_OR(0x228c, ~0UL, (1 << 0));
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RCBA16_AND_OR(0x1100, ~0UL, (1 << 13)|(1 << 14));
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RCBA16_AND_OR(0x0900, ~0UL, (1 << 14));
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RCBA32(0x2304) = 0xc0388400;
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RCBA32_AND_OR(0x2314, ~0UL, (1 << 5)|(1 << 18));
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RCBA32_AND_OR(0x2320, ~0UL, (1 << 15)|(1 << 1));
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RCBA32_AND_OR(0x3314, ~0x1f, 0xf);
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RCBA32(0x3318) = 0x050f0000;
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RCBA32(0x3324) = 0x04000000;
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RCBA32_AND_OR(0x3340, ~0UL, 0xfffff);
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RCBA32_AND_OR(0x3344, ~0UL, (1 << 1));
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RCBA32(0x3360) = 0x0001c000;
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RCBA32(0x3368) = 0x00061100;
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RCBA32(0x3378) = 0x7f8fdfff;
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RCBA32(0x337c) = 0x000003fc;
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RCBA32(0x3388) = 0x00001000;
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RCBA32(0x3390) = 0x0001c000;
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RCBA32(0x33a0) = 0x00000800;
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RCBA32(0x33b0) = 0x00001000;
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RCBA32(0x33c0) = 0x00093900;
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RCBA32(0x33cc) = 0x24653002;
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RCBA32(0x33d0) = 0x062108fe;
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RCBA32_AND_OR(0x33d4, 0xf000f000, 0x00670060);
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RCBA32(0x3a28) = 0x01010000;
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RCBA32(0x3a2c) = 0x01010404;
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RCBA32(0x3a80) = 0x01041041;
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RCBA32_AND_OR(0x3a84, ~0x0000ffff, 0x00001001);
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RCBA32_AND_OR(0x3a84, ~0UL, (1 << 24)); /* SATA 2/3 disabled */
|
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RCBA32_AND_OR(0x3a88, ~0UL, (1 << 0)); /* SATA 4/5 disabled */
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RCBA32(0x3a6c) = 0x00000001;
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RCBA32_AND_OR(0x2344, 0x00ffff00, 0xff00000c);
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RCBA32_AND_OR(0x80c, ~(0xff << 20), 0x11 << 20);
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RCBA32(0x33c8) = 0;
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RCBA32_AND_OR(0x21b0, ~0UL, 0xf);
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}
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|
||||
/* PantherPoint PCH Power Management init */
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||||
static void ppt_pm_init(struct device *dev)
|
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{
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printk(BIOS_DEBUG, "PantherPoint PM init\n");
|
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pci_write_config8(dev, 0xa9, 0x47);
|
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RCBA32_AND_OR(0x2238, ~0UL, (1 << 0));
|
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RCBA32_AND_OR(0x228c, ~0UL, (1 << 0));
|
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RCBA16_AND_OR(0x1100, ~0UL, (1 << 13)|(1 << 14));
|
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RCBA16_AND_OR(0x0900, ~0UL, (1 << 14));
|
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RCBA32(0x2304) = 0xc03b8400;
|
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RCBA32_AND_OR(0x2314, ~0UL, (1 << 5)|(1 << 18));
|
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RCBA32_AND_OR(0x2320, ~0UL, (1 << 15)|(1 << 1));
|
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RCBA32_AND_OR(0x3314, ~0x1f, 0xf);
|
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RCBA32(0x3318) = 0x054f0000;
|
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RCBA32(0x3324) = 0x04000000;
|
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RCBA32_AND_OR(0x3340, ~0UL, 0xfffff);
|
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RCBA32_AND_OR(0x3344, ~0UL, (1 << 1)|(1 << 0));
|
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RCBA32(0x3360) = 0x0001c000;
|
||||
RCBA32(0x3368) = 0x00061100;
|
||||
RCBA32(0x3378) = 0x7f8fdfff;
|
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RCBA32(0x337c) = 0x000003fd;
|
||||
RCBA32(0x3388) = 0x00001000;
|
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RCBA32(0x3390) = 0x0001c000;
|
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RCBA32(0x33a0) = 0x00000800;
|
||||
RCBA32(0x33b0) = 0x00001000;
|
||||
RCBA32(0x33c0) = 0x00093900;
|
||||
RCBA32(0x33cc) = 0x24653002;
|
||||
RCBA32(0x33d0) = 0x067388fe;
|
||||
RCBA32_AND_OR(0x33d4, 0xf000f000, 0x00670060);
|
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RCBA32(0x3a28) = 0x01010000;
|
||||
RCBA32(0x3a2c) = 0x01010404;
|
||||
RCBA32(0x3a80) = 0x01040000;
|
||||
RCBA32_AND_OR(0x3a84, ~0x0000ffff, 0x00001001);
|
||||
RCBA32_AND_OR(0x3a84, ~0UL, (1 << 24)); /* SATA 2/3 disabled */
|
||||
RCBA32_AND_OR(0x3a88, ~0UL, (1 << 0)); /* SATA 4/5 disabled */
|
||||
RCBA32(0x3a6c) = 0x00000001;
|
||||
RCBA32_AND_OR(0x2344, 0x00ffff00, 0xff00000c);
|
||||
RCBA32_AND_OR(0x80c, ~(0xff << 20), 0x11 << 20);
|
||||
RCBA32_AND_OR(0x33a4, ~0UL, (1 << 0));
|
||||
RCBA32(0x33c8) = 0;
|
||||
RCBA32_AND_OR(0x21b0, ~0UL, 0xf);
|
||||
}
|
||||
|
||||
static void enable_hpet(void)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
/* Move HPET to default address 0xfed00000 and enable it */
|
||||
reg32 = RCBA32(HPTC);
|
||||
reg32 |= (1 << 7); // HPET Address Enable
|
||||
reg32 &= ~(3 << 0);
|
||||
RCBA32(HPTC) = reg32;
|
||||
}
|
||||
|
||||
#if CONFIG_HAVE_SMI_HANDLER
|
||||
static void pch_lock_smm(struct device *dev)
|
||||
{
|
||||
#if TEST_SMM_FLASH_LOCKDOWN
|
||||
u8 reg8;
|
||||
#endif
|
||||
|
||||
if (acpi_slp_type != 3) {
|
||||
#if ENABLE_ACPI_MODE_IN_COREBOOT
|
||||
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
|
||||
outb(0xe1, 0xb2); // Enable ACPI mode
|
||||
printk(BIOS_DEBUG, "done.\n");
|
||||
#else
|
||||
printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
|
||||
outb(0x1e, 0xb2); // Disable ACPI mode
|
||||
printk(BIOS_DEBUG, "done.\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Don't allow evil boot loaders, kernels, or
|
||||
* userspace applications to deceive us:
|
||||
*/
|
||||
smm_lock();
|
||||
|
||||
#if TEST_SMM_FLASH_LOCKDOWN
|
||||
/* Now try this: */
|
||||
printk(BIOS_DEBUG, "Locking BIOS to RO... ");
|
||||
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
|
||||
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
|
||||
(reg8&1)?"rw":"ro");
|
||||
reg8 &= ~(1 << 0); /* clear BIOSWE */
|
||||
pci_write_config8(dev, 0xdc, reg8);
|
||||
reg8 |= (1 << 1); /* set BLE */
|
||||
pci_write_config8(dev, 0xdc, reg8);
|
||||
printk(BIOS_DEBUG, "ok.\n");
|
||||
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
|
||||
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
|
||||
(reg8&1)?"rw":"ro");
|
||||
|
||||
printk(BIOS_DEBUG, "Writing:\n");
|
||||
*(volatile u8 *)0xfff00000 = 0x00;
|
||||
printk(BIOS_DEBUG, "Testing:\n");
|
||||
reg8 |= (1 << 0); /* set BIOSWE */
|
||||
pci_write_config8(dev, 0xdc, reg8);
|
||||
|
||||
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
|
||||
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
|
||||
(reg8&1)?"rw":"ro");
|
||||
printk(BIOS_DEBUG, "Done.\n");
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
static void pch_disable_smm_only_flashing(struct device *dev)
|
||||
{
|
||||
u8 reg8;
|
||||
|
||||
printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");
|
||||
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
|
||||
reg8 &= ~(1 << 5);
|
||||
pci_write_config8(dev, 0xdc, reg8);
|
||||
}
|
||||
|
||||
static void pch_fixups(struct device *dev)
|
||||
{
|
||||
u8 gen_pmcon_2;
|
||||
|
||||
/* Indicate DRAM init done for MRC S3 to know it can resume */
|
||||
gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2);
|
||||
gen_pmcon_2 |= (1 << 7);
|
||||
pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2);
|
||||
|
||||
}
|
||||
|
||||
static void pch_decode_init(struct device *dev)
|
||||
{
|
||||
config_t *config = dev->chip_info;
|
||||
|
||||
printk(BIOS_DEBUG, "pch_decode_init\n");
|
||||
|
||||
pci_write_config32(dev, LPC_GEN1_DEC, config->gen1_dec);
|
||||
pci_write_config32(dev, LPC_GEN2_DEC, config->gen2_dec);
|
||||
pci_write_config32(dev, LPC_GEN3_DEC, config->gen3_dec);
|
||||
pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec);
|
||||
}
|
||||
|
||||
static void lpc_init(struct device *dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "pch: lpc_init\n");
|
||||
|
||||
/* Set the value for PCI command register. */
|
||||
pci_write_config16(dev, PCI_COMMAND, 0x000f);
|
||||
|
||||
/* IO APIC initialization. */
|
||||
pch_enable_apic(dev);
|
||||
|
||||
pch_enable_serial_irqs(dev);
|
||||
|
||||
/* Setup the PIRQ. */
|
||||
pch_pirq_init(dev);
|
||||
|
||||
/* Setup power options. */
|
||||
pch_power_options(dev);
|
||||
|
||||
/* Initialize power management */
|
||||
switch (pch_silicon_type()) {
|
||||
case PCH_TYPE_CPT: /* CougarPoint */
|
||||
cpt_pm_init(dev);
|
||||
break;
|
||||
case PCH_TYPE_PPT: /* PantherPoint */
|
||||
ppt_pm_init(dev);
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_ERR, "Unknown Chipset: 0x%04x\n", dev->device);
|
||||
}
|
||||
|
||||
/* Set the state of the GPIO lines. */
|
||||
//gpio_init(dev);
|
||||
|
||||
/* Initialize the real time clock. */
|
||||
pch_rtc_init(dev);
|
||||
|
||||
/* Initialize ISA DMA. */
|
||||
isa_dma_init();
|
||||
|
||||
/* Initialize the High Precision Event Timers, if present. */
|
||||
enable_hpet();
|
||||
|
||||
setup_i8259();
|
||||
|
||||
/* The OS should do this? */
|
||||
/* Interrupt 9 should be level triggered (SCI) */
|
||||
i8259_configure_irq_trigger(9, 1);
|
||||
|
||||
pch_disable_smm_only_flashing(dev);
|
||||
|
||||
#if CONFIG_HAVE_SMI_HANDLER
|
||||
pch_lock_smm(dev);
|
||||
#endif
|
||||
|
||||
pch_fixups(dev);
|
||||
}
|
||||
|
||||
static void pch_lpc_read_resources(device_t dev)
|
||||
{
|
||||
struct resource *res;
|
||||
config_t *config = dev->chip_info;
|
||||
u8 io_index = 0;
|
||||
|
||||
/* Get the normal PCI resources of this device. */
|
||||
pci_dev_read_resources(dev);
|
||||
|
||||
/* Add an extra subtractive resource for both memory and I/O. */
|
||||
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
|
||||
res->base = 0;
|
||||
res->size = 0x1000;
|
||||
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
|
||||
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
|
||||
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
|
||||
res->base = 0xff800000;
|
||||
res->size = 0x00800000; /* 8 MB for flash */
|
||||
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
|
||||
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
|
||||
res = new_resource(dev, 3); /* IOAPIC */
|
||||
res->base = IO_APIC_ADDR;
|
||||
res->size = 0x00001000;
|
||||
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
|
||||
/* Set PCH IO decode ranges if required.*/
|
||||
if ((config->gen1_dec & 0xFFFC) > 0x1000) {
|
||||
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
|
||||
res->base = config->gen1_dec & 0xFFFC;
|
||||
res->size = (config->gen1_dec >> 16) & 0xFC;
|
||||
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
|
||||
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
}
|
||||
|
||||
if ((config->gen2_dec & 0xFFFC) > 0x1000) {
|
||||
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
|
||||
res->base = config->gen2_dec & 0xFFFC;
|
||||
res->size = (config->gen2_dec >> 16) & 0xFC;
|
||||
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
|
||||
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
}
|
||||
|
||||
if ((config->gen3_dec & 0xFFFC) > 0x1000) {
|
||||
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
|
||||
res->base = config->gen3_dec & 0xFFFC;
|
||||
res->size = (config->gen3_dec >> 16) & 0xFC;
|
||||
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
|
||||
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
}
|
||||
|
||||
if ((config->gen4_dec & 0xFFFC) > 0x1000) {
|
||||
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
|
||||
res->base = config->gen4_dec & 0xFFFC;
|
||||
res->size = (config->gen4_dec >> 16) & 0xFC;
|
||||
res->flags = IORESOURCE_IO| IORESOURCE_SUBTRACTIVE |
|
||||
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
}
|
||||
}
|
||||
|
||||
static void pch_lpc_enable_resources(device_t dev)
|
||||
{
|
||||
pch_decode_init(dev);
|
||||
return pci_dev_enable_resources(dev);
|
||||
}
|
||||
|
||||
static void pch_lpc_enable(device_t dev)
|
||||
{
|
||||
pch_enable(dev);
|
||||
}
|
||||
|
||||
static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
|
||||
{
|
||||
if (!vendor || !device) {
|
||||
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
|
||||
pci_read_config32(dev, PCI_VENDOR_ID));
|
||||
} else {
|
||||
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
|
||||
((device & 0xffff) << 16) | (vendor & 0xffff));
|
||||
}
|
||||
}
|
||||
|
||||
static struct pci_operations pci_ops = {
|
||||
.set_subsystem = set_subsystem,
|
||||
};
|
||||
|
||||
static struct device_operations device_ops = {
|
||||
.read_resources = pch_lpc_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pch_lpc_enable_resources,
|
||||
.init = lpc_init,
|
||||
.enable = pch_lpc_enable,
|
||||
.scan_bus = scan_static_bus,
|
||||
.ops_pci = &pci_ops,
|
||||
};
|
||||
|
||||
|
||||
/* IDs for LPC device of Intel 6 Series Chipset, Intel 7 Series Chipset, and
|
||||
* Intel C200 Series Chipset
|
||||
*/
|
||||
|
||||
static const unsigned short pci_device_ids[] = { 0x1c46, 0x1c47, 0x1c49, 0x1c4a,
|
||||
0x1c4b, 0x1c4c, 0x1c4d, 0x1c4e,
|
||||
0x1c4f, 0x1c50, 0x1c52, 0x1c54,
|
||||
0x1e55, 0x1c56, 0x1e57, 0x1c5c,
|
||||
0x1e5d, 0x1e5e, 0x1e5f, 0x2310,
|
||||
0 };
|
||||
|
||||
static const struct pci_driver pch_lpc __pci_driver = {
|
||||
.ops = &device_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.devices = pci_device_ids,
|
||||
};
|
||||
|
||||
|
||||
Reference in New Issue
Block a user