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soc/intel/tigerlake: Disable VT-d and no DMAR table for pre-QS platform

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Enabling VT-d on pre-QS silicon may have issues like rendering the
Thunderbolt driver useless. This change will ensure that VT-d is
disabled for pre-QS silicon and enabled for QS.

BUG=b:152242800,161215918,158519322
TEST=Validated VT-d is disabled for pre-QS (cpu:0x806c0) and enabled for
QS (cpu:0x806c1). Kernel walks through ACPI tables. If VT-d is disabled
and no DMAR table exists, IOMMU will not be enabled.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I98a9f6df185002a4e68eaa910f867acd0b96ec2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
John Zhao
2020-07-17 11:36:00 -07:00
committed by Patrick Georgi
parent ec321094f6
commit 7417bb0e5a
1 changed files with 27 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
src/soc/intel/tigerlake/romstage/fsp_params.c
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@ -5,6 +5,7 @@
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <fsp/util.h> #include <fsp/util.h>
#include <intelblocks/cpulib.h> #include <intelblocks/cpulib.h>
#include <intelblocks/mp_init.h>
#include <soc/gpio_soc_defs.h> #include <soc/gpio_soc_defs.h>
#include <soc/iomap.h> #include <soc/iomap.h>
#include <soc/msr.h> #include <soc/msr.h>
@ -17,7 +18,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
const struct soc_intel_tigerlake_config *config) const struct soc_intel_tigerlake_config *config)
{ {
unsigned int i; unsigned int i;
uint32_t mask = 0; uint32_t cpu_id, mask = 0;
const struct device *dev; const struct device *dev;
dev = pcidev_path_on_root(SA_DEVFN_IGD); dev = pcidev_path_on_root(SA_DEVFN_IGD);
@ -182,18 +183,31 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); sizeof(m_cfg->PchHdaAudioLinkSndwEnable));
/* Vt-D config */ /* Vt-D config */
m_cfg->VtdDisable = 0; cpu_id = cpu_get_cpuid();
m_cfg->VtdIgdEnable = 0x1; if (cpu_id == CPUID_TIGERLAKE_A0) {
m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; /* Disable VT-d support for pre-QS platform */
m_cfg->VtdIpuEnable = 0x1; m_cfg->VtdDisable = 1;
m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS; } else {
m_cfg->VtdIopEnable = 0x1; /* Enable VT-d support for QS platform */
m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS; m_cfg->VtdDisable = 0;
m_cfg->VtdItbtEnable = 0x1; m_cfg->VtdIgdEnable = 0x1;
m_cfg->VtdBaseAddress[3] = TBT0_BASE_ADDRESS; m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS;
m_cfg->VtdBaseAddress[4] = TBT1_BASE_ADDRESS; m_cfg->VtdIpuEnable = 0x1;
m_cfg->VtdBaseAddress[5] = TBT2_BASE_ADDRESS; m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS;
m_cfg->VtdBaseAddress[6] = TBT3_BASE_ADDRESS; m_cfg->VtdIopEnable = 0x1;
m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS;
if (m_cfg->TcssDma0En || m_cfg->TcssDma1En)
m_cfg->VtdItbtEnable = 0x1;
if (m_cfg->TcssItbtPcie0En)
m_cfg->VtdBaseAddress[3] = TBT0_BASE_ADDRESS;
if (m_cfg->TcssItbtPcie1En)
m_cfg->VtdBaseAddress[4] = TBT1_BASE_ADDRESS;
if (m_cfg->TcssItbtPcie2En)
m_cfg->VtdBaseAddress[5] = TBT2_BASE_ADDRESS;
if (m_cfg->TcssItbtPcie3En)
m_cfg->VtdBaseAddress[6] = TBT3_BASE_ADDRESS;
}
/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
m_cfg->VmxEnable = CONFIG(ENABLE_VMX); m_cfg->VmxEnable = CONFIG(ENABLE_VMX);