mb/system76: Enable dGPUs

Change-Id: I4ca91ff631dd4badbfba72e69651f03753323a54
Signed-off-by: Tim Crawford <tcrawford@system76.com>

src/mainboard/system76/addw1/Kconfig

@@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC

src/mainboard/system76/addw1/Makefile.mk

@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

src/mainboard/system76/addw1/acpi/mainboard.asl

@@ -1,11 +1,19 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <variant/gpio.h>
+
 #define EC_GPE_SCI 0x03 /* GPP_K3 */
 #define EC_GPE_SWI 0x06 /* GPP_K6 */
 #include <ec/system76/ec/acpi/ec.asl>
 
 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		Device (PEGP) {
+			Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
+			#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
+		}
+	}
 }
 
 Scope (\_GPE) {

src/mainboard/system76/addw1/devicetree.cb

@@ -55,6 +55,12 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device ref igpu		on	end
 		device ref dptf		on

src/mainboard/system76/addw1/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 static const struct cnl_mb_cfg memcfg = {
 	.spd[0] = {
@@ -20,5 +22,17 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+
 	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
 }

src/mainboard/system76/addw1/variants/addw1/include/variant/gpio.h

@@ -3,7 +3,16 @@
 #ifndef VARIANT_GPIO_H
 #define VARIANT_GPIO_H
 
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_C12
+#define DGPU_SSID	0x65d11558
+
+#ifndef __ACPI__
 void variant_configure_early_gpios(void);
 void variant_configure_gpios(void);
+#endif
 
 #endif

src/mainboard/system76/addw1/variants/addw2/include/variant/gpio.h

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_C12
+#define DGPU_SSID	0x65e11558
+
+#ifndef __ACPI__
+void variant_configure_early_gpios(void);
+void variant_configure_gpios(void);
+#endif
+
+#endif

src/mainboard/system76/adl/Kconfig

@@ -35,10 +35,12 @@ config BOARD_SYSTEM76_GALP6
 
 config BOARD_SYSTEM76_GAZE17_3050
 	select BOARD_SYSTEM76_ADL_COMMON
+	select DRIVERS_GFX_NVIDIA
 	select EC_SYSTEM76_EC_DGPU
 
 config BOARD_SYSTEM76_GAZE17_3060_B
 	select BOARD_SYSTEM76_ADL_COMMON
+	select DRIVERS_GFX_NVIDIA
 	select EC_SYSTEM76_EC_DGPU
 	select MAINBOARD_USES_IFD_GBE_REGION
 
@@ -48,11 +50,15 @@ config BOARD_SYSTEM76_LEMP11
 
 config BOARD_SYSTEM76_ORYP9
 	select BOARD_SYSTEM76_ADL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC_DGPU
 
 config BOARD_SYSTEM76_ORYP10
 	select BOARD_SYSTEM76_ADL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
 	select EC_SYSTEM76_EC_DGPU
 
 if BOARD_SYSTEM76_ADL_COMMON
@@ -107,6 +113,12 @@ config CONSOLE_POST
 config D3COLD_SUPPORT
 	default n
 
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP
+	default 45 if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
+
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX
+	default 25 if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
+
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
 

src/mainboard/system76/adl/Makefile.mk

@@ -2,6 +2,10 @@
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
 
+ifeq ($(CONFIG_DRIVERS_GFX_NVIDIA),y)
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
+endif
+
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
 

src/mainboard/system76/adl/acpi/mainboard.asl

@@ -1,5 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#if CONFIG(DRIVERS_GFX_NVIDIA)
+#include <variant/gpio.h>
+#endif
+
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
 #include <ec/system76/ec/acpi/ec.asl>
@@ -8,5 +12,11 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+
+#if CONFIG(DRIVERS_GFX_NVIDIA)
+		Scope (PEG2) {
+			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
+		}
+#endif
 	}
 }

src/mainboard/system76/adl/variants/gaze17-3050/include/variant/gpio.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_B2
+#define DGPU_PWR_EN	GPP_A14
+#define DGPU_GC6	GPP_F13
+#define DGPU_SSID	0x866d1558
+
+#endif

src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb

@@ -40,6 +40,10 @@ chip soc/intel/alderlake
 				.clk_req = 3,
 				.flags = PCIE_RP_LTR,
 			}"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+			end
 		end
 		device ref pcie4_0 on
 			# PCIe PEG0 x4, Clock 0 (SSD2)

src/mainboard/system76/adl/variants/gaze17-3050/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -17,6 +19,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
 	// Set primary display to internal graphics
 	mupd->FspmConfig.PrimaryDisplay = 0;
 

src/mainboard/system76/adl/variants/gaze17-3060-b/include/variant/gpio.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_B2
+#define DGPU_PWR_EN	GPP_A14
+#define DGPU_GC6	GPP_F13
+#define DGPU_SSID	0x867c1558
+
+#endif

src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb

@@ -40,6 +40,10 @@ chip soc/intel/alderlake
 				.clk_req = 3,
 				.flags = PCIE_RP_LTR,
 			}"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+			end
 		end
 		device ref igpu on
 			# DDIA is eDP

src/mainboard/system76/adl/variants/gaze17-3060-b/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -17,6 +19,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
 	// Set primary display to internal graphics
 	mupd->FspmConfig.PrimaryDisplay = 0;
 

src/mainboard/system76/adl/variants/oryp10/include/variant/gpio.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_B2
+#define DGPU_PWR_EN	GPP_A14
+#define DGPU_GC6	GPP_A7
+#define DGPU_SSID	0x65f51558
+
+#endif

src/mainboard/system76/adl/variants/oryp10/overridetree.cb

@@ -25,6 +25,10 @@ chip soc/intel/alderlake
 				.clk_req = 3,
 				.flags = PCIE_RP_LTR,
 			}"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+			end
 		end
 		device ref igpu on
 			register "ddi_portA_config" = "1"

src/mainboard/system76/adl/variants/oryp10/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -20,6 +22,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
 	// Set primary display to internal graphics
 	mupd->FspmConfig.PrimaryDisplay = 0;
 

src/mainboard/system76/adl/variants/oryp9/include/variant/gpio.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_B2
+#define DGPU_PWR_EN	GPP_A14
+#define DGPU_GC6	GPP_A7
+#define DGPU_SSID	0x65f51558
+
+#endif

src/mainboard/system76/adl/variants/oryp9/overridetree.cb

@@ -25,6 +25,10 @@ chip soc/intel/alderlake
 				.clk_req = 3,
 				.flags = PCIE_RP_LTR,
 			}"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+			end
 		end
 		device ref igpu on
 			register "ddi_portA_config" = "1"

src/mainboard/system76/adl/variants/oryp9/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -17,6 +19,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
 	// Set primary display to internal graphics
 	mupd->FspmConfig.PrimaryDisplay = 0;
 

src/mainboard/system76/bonw14/Kconfig

@@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC

src/mainboard/system76/bonw14/devicetree.cb

@@ -58,12 +58,13 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 7 (NVIDIA GPU)
 			register "PcieClkSrcUsage[7]" = "0x40"
 			register "PcieClkSrcClkReq[7]" = "7"
-
+			chip drivers/gfx/nvidia
 				device pci 00.0 on end # VGA controller
 				device pci 00.1 on end # Audio device
 				device pci 00.2 on end # USB xHCI Host controller
 				device pci 00.3 on end # USB Type-C UCSI controller
 			end
+		end
 		device ref dptf		on	end
 		device ref thermal	on	end
 		device ref xhci		on

src/mainboard/system76/gaze15/Kconfig

@@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_DGPU

src/mainboard/system76/gaze15/Makefile.mk

@@ -1,6 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

src/mainboard/system76/gaze15/acpi/mainboard.asl

@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <variant/gpio.h>
+
 #define EC_GPE_SCI 0x03 /* GPP_K3 */
 #define EC_GPE_SWI 0x06 /* GPP_K6 */
 #include <ec/system76/ec/acpi/ec.asl>
@@ -8,6 +10,10 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+		Device (PEGP) {
+			Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
+			#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
+		}
 	}
 }
 

src/mainboard/system76/gaze15/devicetree.cb

@@ -54,6 +54,12 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device ref igpu		on
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"

src/mainboard/system76/gaze15/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 static const struct cnl_mb_cfg memcfg = {
 	.spd[0] = {
@@ -20,5 +22,17 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+
 	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
 }

src/mainboard/system76/gaze15/variants/gaze14/include/variant/gpio.h

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_K21
+#define DGPU_SSID	0x85501558
+
+#ifndef __ACPI__
+void variant_configure_early_gpios(void);
+void variant_configure_gpios(void);
+#endif
+
+#endif

src/mainboard/system76/gaze15/variants/gaze15/include/variant/gpio.h

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_K21
+#define DGPU_SSID	0x85201558
+
+#ifndef __ACPI__
+void variant_configure_early_gpios(void);
+void variant_configure_gpios(void);
+#endif
+
+#endif

src/mainboard/system76/oryp5/Kconfig

@@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC

src/mainboard/system76/oryp5/acpi/mainboard.asl

@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <mainboard/gpio.h>
+
 #define EC_GPE_SCI 0x17 /* GPP_B23 */
 #define EC_GPE_SWI 0x26 /* GPP_G6 */
 #include <ec/system76/ec/acpi/ec.asl>
@@ -9,6 +11,10 @@ Scope (\_SB)
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+		Device (PEGP) {
+			Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
+			#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
+		}
 	}
 }
 

src/mainboard/system76/oryp5/devicetree.cb

@@ -62,6 +62,12 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device ref igpu		on
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"

src/mainboard/system76/oryp5/include/mainboard/gpio.h

@@ -3,7 +3,16 @@
 #ifndef MAINBOARD_GPIO_H
 #define MAINBOARD_GPIO_H
 
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_C12
+#define DGPU_SSID	0x95e61558
+
+#ifndef __ACPI__
 void mainboard_configure_early_gpios(void);
 void mainboard_configure_gpios(void);
+#endif
 
 #endif

src/mainboard/system76/oryp5/romstage.c

@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
+#include <mainboard/gpio.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
 
@@ -20,6 +22,18 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+
 	// Allow memory speeds higher than 2666 MT/s
 	memupd->FspmConfig.SaOcSupport = 1;
 

src/mainboard/system76/oryp6/Kconfig

@@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC

src/mainboard/system76/oryp6/Makefile.mk

@@ -1,6 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

src/mainboard/system76/oryp6/acpi/mainboard.asl

@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <variant/gpio.h>
+
 #define EC_GPE_SCI 0x03 /* GPP_K3 */
 #define EC_GPE_SWI 0x06 /* GPP_K6 */
 #include <ec/system76/ec/acpi/ec.asl>
@@ -8,6 +10,10 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+		Device (PEGP) {
+			Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
+			#include <drivers/gfx/nvidia/acpi/coffeelake.asl>
+		}
 	}
 }
 

src/mainboard/system76/oryp6/devicetree.cb

@@ -59,6 +59,12 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device ref igpu		on
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"

src/mainboard/system76/oryp6/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 #include <variant/romstage.h>
 
 static const struct cnl_mb_cfg memcfg = {
@@ -21,6 +23,18 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+
 	variant_configure_fspm(memupd);
 
 	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);

src/mainboard/system76/oryp6/variants/oryp6/include/variant/gpio.h

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_K21
+#define DGPU_SSID	0x50d31558
+
+#ifndef __ACPI__
+void variant_configure_early_gpios(void);
+void variant_configure_gpios(void);
+#endif
+
+#endif

src/mainboard/system76/oryp6/variants/oryp7/include/variant/gpio.h

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_K21
+#define DGPU_SSID	0x65e51558
+
+#ifndef __ACPI__
+void variant_configure_early_gpios(void);
+void variant_configure_gpios(void);
+#endif
+
+#endif

src/mainboard/system76/rpl/Kconfig

@@ -27,6 +27,8 @@ config BOARD_SYSTEM76_RPL_COMMON
 
 config BOARD_SYSTEM76_ADDW3
 	select BOARD_SYSTEM76_RPL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
 	select DRIVERS_INTEL_DTBT
 	select EC_SYSTEM76_EC_DGPU
 	select MAINBOARD_USES_IFD_GBE_REGION
@@ -35,12 +37,16 @@ config BOARD_SYSTEM76_ADDW3
 
 config BOARD_SYSTEM76_ADDW4
 	select BOARD_SYSTEM76_RPL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
 	select EC_SYSTEM76_EC_DGPU
 	select PCIEXP_HOTPLUG
 	select SOC_INTEL_ALDERLAKE_PCH_S
 
 config BOARD_SYSTEM76_BONW15
 	select BOARD_SYSTEM76_RPL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
 	select DRIVERS_INTEL_DTBT
 	select EC_SYSTEM76_EC_DGPU
 	select PCIEXP_HOTPLUG
@@ -48,6 +54,8 @@ config BOARD_SYSTEM76_BONW15
 
 config BOARD_SYSTEM76_BONW15_B
 	select BOARD_SYSTEM76_RPL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
 	select DRIVERS_INTEL_DTBT
 	select EC_SYSTEM76_EC_DGPU
 	select PCIEXP_HOTPLUG
@@ -65,6 +73,8 @@ config BOARD_SYSTEM76_GALP7
 
 config BOARD_SYSTEM76_GAZE18
 	select BOARD_SYSTEM76_RPL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
 	select EC_SYSTEM76_EC_DGPU
 	select SOC_INTEL_ALDERLAKE_PCH_P
 
@@ -76,12 +86,16 @@ config BOARD_SYSTEM76_LEMP12
 
 config BOARD_SYSTEM76_ORYP11
 	select BOARD_SYSTEM76_RPL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
 	select EC_SYSTEM76_EC_DGPU
 	select SOC_INTEL_ALDERLAKE_PCH_P
 	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 
 config BOARD_SYSTEM76_ORYP12
 	select BOARD_SYSTEM76_RPL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
 	select DRIVERS_I2C_TAS5825M
 	select DRIVERS_INTEL_DTBT
 	select EC_SYSTEM76_EC_DGPU
@@ -90,6 +104,8 @@ config BOARD_SYSTEM76_ORYP12
 
 config BOARD_SYSTEM76_SERW13
 	select BOARD_SYSTEM76_RPL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
 	select DRIVERS_INTEL_DTBT
 	select EC_SYSTEM76_EC_DGPU
 	select PCIEXP_HOTPLUG
@@ -162,6 +178,17 @@ config CONSOLE_POST
 config D3COLD_SUPPORT
 	default n
 
+config DRIVERS_GFX_NVIDIA_BRIDGE
+	default 0x02 if BOARD_SYSTEM76_BONW15 || BOARD_SYSTEM76_BONW15_B
+
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP
+	default 45 if BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_ORYP12
+	default 55 if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_ADDW4 || BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_SERW13
+	default 80 if BOARD_SYSTEM76_BONW15 || BOARD_SYSTEM76_BONW15_B
+
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX
+	default 25 if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_ADDW4 || BOARD_SYSTEM76_BONW15 || BOARD_SYSTEM76_BONW15_B || BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_ORYP12 || BOARD_SYSTEM76_SERW13
+
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"
 

src/mainboard/system76/rpl/Makefile.mk

@@ -2,6 +2,10 @@
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
 
+ifeq ($(CONFIG_DRIVERS_GFX_NVIDIA),y)
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
+endif
+
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
 

src/mainboard/system76/rpl/acpi/mainboard.asl

@@ -1,5 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#if CONFIG(DRIVERS_GFX_NVIDIA)
+#include <variant/gpio.h>
+#endif
+
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
 #include <ec/system76/ec/acpi/ec.asl>
@@ -8,5 +12,17 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+
+#if CONFIG(DRIVERS_GFX_NVIDIA)
+#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) || CONFIG(BOARD_SYSTEM76_BONW15) || CONFIG(BOARD_SYSTEM76_BONW15_B)
+		Scope (PEG2) {
+			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
+		}
+#else
+		Scope (PEG1) {
+			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
+		}
+#endif
+#endif // CONFIG(DRIVERS_GFX_NVIDIA)
 	}
 }

src/mainboard/system76/rpl/variants/addw3/include/variant/gpio.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_R16
+#define DGPU_PWR_EN	GPP_F9
+#define DGPU_GC6	GPP_F8
+#define DGPU_SSID	0xa6711558
+
+#endif

src/mainboard/system76/rpl/variants/addw3/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -22,6 +24,15 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
 	// Set primary display to internal graphics
 	mupd->FspmConfig.PrimaryDisplay = 0;
 

src/mainboard/system76/rpl/variants/addw4/include/variant/gpio.h

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_R16
+#define DGPU_PWR_EN	GPP_F9
+#define DGPU_SSID	0x03531558
+
+#endif

src/mainboard/system76/rpl/variants/addw4/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -22,6 +24,15 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
 	// Set primary display to hybrid graphics
 	mupd->FspmConfig.PrimaryDisplay = 4;
 

src/mainboard/system76/rpl/variants/bonw15-b/include/variant/gpio.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_R16
+#define DGPU_PWR_EN	GPP_F22
+#define DGPU_GC6	GPP_F8
+#define DGPU_SSID	0x37021558
+
+#endif

src/mainboard/system76/rpl/variants/bonw15-b/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -22,6 +24,15 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
 	// Set primary display to internal graphics
 	mupd->FspmConfig.PrimaryDisplay = 0;
 

src/mainboard/system76/rpl/variants/bonw15/include/variant/gpio.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_R16
+#define DGPU_PWR_EN	GPP_F22
+#define DGPU_GC6	GPP_F8
+#define DGPU_SSID	0x37021558
+
+#endif

src/mainboard/system76/rpl/variants/bonw15/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -22,6 +24,15 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
 	// Set primary display to internal graphics
 	mupd->FspmConfig.PrimaryDisplay = 0;
 

src/mainboard/system76/rpl/variants/gaze18/include/variant/gpio.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_B2
+#define DGPU_PWR_EN	GPP_A14
+#define DGPU_GC6	GPP_F13
+#define DGPU_SSID	0x56301558
+
+#endif

src/mainboard/system76/rpl/variants/gaze18/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -19,6 +21,15 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
 	// Set primary display to internal graphics
 	mupd->FspmConfig.PrimaryDisplay = 0;
 

src/mainboard/system76/rpl/variants/oryp11/include/variant/gpio.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_B2
+#define DGPU_PWR_EN	GPP_A14
+#define DGPU_GC6	GPP_F13
+#define DGPU_SSID	0x66a21558
+
+#endif

src/mainboard/system76/rpl/variants/oryp11/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -19,6 +21,15 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
 	// Set primary display to internal graphics
 	mupd->FspmConfig.PrimaryDisplay = 0;
 

src/mainboard/system76/rpl/variants/oryp12/include/variant/gpio.h

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_R16
+#define DGPU_PWR_EN	GPP_F9
+#define DGPU_SSID	0x66a61558
+
+#endif

src/mainboard/system76/rpl/variants/oryp12/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -22,6 +24,15 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
 	// Set primary display to hybrid graphics
 	mupd->FspmConfig.PrimaryDisplay = 4;
 

src/mainboard/system76/rpl/variants/serw13/include/variant/gpio.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_R16
+#define DGPU_PWR_EN	GPP_F9
+#define DGPU_GC6	GPP_A11
+#define DGPU_SSID	0xd5021558
+
+#endif

src/mainboard/system76/rpl/variants/serw13/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -22,6 +24,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
 	// Set primary display to internal graphics
 	mupd->FspmConfig.PrimaryDisplay = 0;
 

src/mainboard/system76/tgl-h/Kconfig

@@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M if BOARD_SYSTEM76_ORYP8
 	select EC_SYSTEM76_EC

src/mainboard/system76/tgl-h/Makefile.mk

@@ -1,6 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
 
 bootblock-y += bootblock.c
 bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

src/mainboard/system76/tgl-h/acpi/mainboard.asl

@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <variant/gpio.h>
+
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
 #include <ec/system76/ec/acpi/ec.asl>
@@ -8,5 +10,8 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+		Scope (PEG1) {
+			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
+		}
 	}
 }

src/mainboard/system76/tgl-h/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 #include <variant/romstage.h>
 
 static const struct mb_cfg board_cfg = {
@@ -21,9 +23,21 @@ static const struct mem_spd spd_info = {
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
-	variant_memory_init_params(mupd);
-
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	mupd->FspmConfig.PrimaryDisplay = 0;
+
+	variant_memory_init_params(mupd);
+
 	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
 }

src/mainboard/system76/tgl-h/variants/gaze16-3050/include/variant/gpio.h

@@ -3,7 +3,16 @@
 #ifndef VARIANT_GPIO_H
 #define VARIANT_GPIO_H
 
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F8
+#define DGPU_PWR_EN	GPP_F9
+#define DGPU_GC6	GPP_K11
+#define DGPU_SSID	0x50151558
+
+#ifndef __ACPI__
 void variant_configure_early_gpios(void);
 void variant_configure_gpios(void);
+#endif
 
 #endif

src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb

@@ -8,15 +8,11 @@ chip soc/intel/tigerlake
 			# PCIe PEG2 (remapped to PEG1 by FSP) x8, Clock 0 (DGPU)
 			register "PcieClkSrcUsage[0]" = "0x42"
 			register "PcieClkSrcClkReq[0]" = "0"
-			chip soc/intel/common/block/pcie/rtd3
+			chip drivers/gfx/nvidia
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN
+				device pci 00.0 on end # VGA controller
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH
+				device pci 00.1 on end # Audio device
-				register "enable_delay_ms" = "16"
+				device pci 00.2 on end # USB xHCI Host controller
-				register "enable_off_delay_ms" = "4"
+				device pci 00.3 on end # USB Type-C UCSI controller
-				register "reset_delay_ms" = "10"
-				register "reset_off_delay_ms" = "4"
-				register "srcclk_pin" = "0" # GFX_CLKREQ0#
-				device generic 0 on end
 			end
 		end
 		device ref igpu on

src/mainboard/system76/tgl-h/variants/gaze16-3060/include/variant/gpio.h

@@ -3,7 +3,16 @@
 #ifndef VARIANT_GPIO_H
 #define VARIANT_GPIO_H
 
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F8
+#define DGPU_PWR_EN	GPP_F9
+#define DGPU_GC6	GPP_K11
+#define DGPU_SSID	0x50e11558
+
+#ifndef __ACPI__
 void variant_configure_early_gpios(void);
 void variant_configure_gpios(void);
+#endif
 
 #endif

src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb

@@ -8,15 +8,11 @@ chip soc/intel/tigerlake
 			# PCIe PEG1 x16, Clock 9 (DGPU)
 			register "PcieClkSrcUsage[9]" = "0x41"
 			register "PcieClkSrcClkReq[9]" = "9"
-			chip soc/intel/common/block/pcie/rtd3
+			chip drivers/gfx/nvidia
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN
+				device pci 00.0 on end # VGA controller
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH
+				device pci 00.1 on end # Audio device
-				register "enable_delay_ms" = "16"
+				device pci 00.2 on end # USB xHCI Host controller
-				register "enable_off_delay_ms" = "4"
+				device pci 00.3 on end # USB Type-C UCSI controller
-				register "reset_delay_ms" = "10"
-				register "reset_off_delay_ms" = "4"
-				register "srcclk_pin" = "9" # PEG_CLKREQ#
-				device generic 0 on end
 			end
 		end
 		device ref igpu on

src/mainboard/system76/tgl-h/variants/oryp8/include/variant/gpio.h

@@ -3,7 +3,16 @@
 #ifndef VARIANT_GPIO_H
 #define VARIANT_GPIO_H
 
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F8
+#define DGPU_PWR_EN	GPP_F9
+#define DGPU_GC6	GPP_K11
+#define DGPU_SSID	0x65f11558
+
+#ifndef __ACPI__
 void variant_configure_early_gpios(void);
 void variant_configure_gpios(void);
+#endif
 
 #endif

src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb

@@ -21,15 +21,11 @@ chip soc/intel/tigerlake
 			# PCIe PEG1 x16, Clock 9 (DGPU)
 			register "PcieClkSrcUsage[9]" = "0x41"
 			register "PcieClkSrcClkReq[9]" = "9"
-			chip soc/intel/common/block/pcie/rtd3
+			chip drivers/gfx/nvidia
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN
+				device pci 00.0 on end # VGA controller
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH
+				device pci 00.1 on end # Audio device
-				register "enable_delay_ms" = "16"
+				device pci 00.2 on end # USB xHCI Host controller
-				register "enable_off_delay_ms" = "4"
+				device pci 00.3 on end # USB Type-C UCSI controller
-				register "reset_delay_ms" = "10"
-				register "reset_off_delay_ms" = "4"
-				register "srcclk_pin" = "9" # PEG_CLKREQ#
-				device generic 0 on end
 			end
 		end
 		device ref peg0 on

src/mainboard/system76/tgl-u/Kconfig

@@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
+	select DRIVERS_GFX_NVIDIA if BOARD_SYSTEM76_GALP5
 	select DRIVERS_I2C_HID
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_INTEL_USB4_RETIMER
@@ -73,4 +74,15 @@ config UART_FOR_CONSOLE
 config USE_PM_ACPI_TIMER
 	default n
 
+# For galp5 with dGPU
+if DRIVERS_GFX_NVIDIA
+
+config ONBOARD_VGA_IS_PRIMARY
+	default y
+
+config DRIVERS_GFX_NVIDIA_BRIDGE
+	default 0x1c
+
+endif # DRIVERS_GFX_NVIDIA
+
 endif

src/mainboard/system76/tgl-u/acpi/mainboard.asl

@@ -1,5 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#if CONFIG(BOARD_SYSTEM76_GALP5)
+#include <variant/gpio.h>
+#endif
+
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
 #include <ec/system76/ec/acpi/ec.asl>
@@ -8,5 +12,10 @@ Scope (\_SB) {
 	#include "sleep.asl"
 	Scope (PCI0) {
 		#include "backlight.asl"
+#if CONFIG(BOARD_SYSTEM76_GALP5)
+		Scope (RP01) { // Remapped from RP05
+			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
+		}
+#endif
 	}
 }

src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb

@@ -146,15 +146,11 @@ chip soc/intel/tigerlake
 			register "PcieRpLtrEnable[4]" = "1"
 			register "PcieClkSrcUsage[2]" = "4"
 			register "PcieClkSrcClkReq[2]" = "2"
-			chip soc/intel/common/block/pcie/rtd3
+			chip drivers/gfx/nvidia
-				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_U5)" # DGPU_PWR_EN
+				device pci 00.0 on end # VGA controller
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_U4)" # DGPU_RST#_PCH
+				device pci 00.1 on end # Audio device
-				register "enable_delay_ms" = "16"
+				device pci 00.2 on end # USB xHCI Host controller
-				register "enable_off_delay_ms" = "4"
+				device pci 00.3 on end # USB Type-C UCSI controller
-				register "reset_delay_ms" = "10"
-				register "reset_off_delay_ms" = "4"
-				register "srcclk_pin" = "2" # PEG_CLKREQ#
-				device generic 0 on end
 			end
 		end
 		device ref pcie_rp9 on

src/mainboard/system76/tgl-u/variants/galp5/romstage.c

@@ -1,8 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <fsp/util.h>
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -18,5 +19,17 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	mupd->FspmConfig.PrimaryDisplay = 0;
+
 	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
 }